Patent Application
20240347576
Many modern-day electronic devices contain integrated circuits. Some integrated circuits are constructed as stacked integrated circuit assemblies, which can be referred to as three-dimensional integrated circuits. Three-dimensional integrated circuits involve fabricating a plurality of integrated circuit portions on wafers and bonding the wafers, portions of the wafers (e.g., dies), or combinations thereof together, making electrical connections at one or more interfaces, to form integrated circuits comprising multiple pieces of mechanically and electrically joined semiconductor material. The stacking of multiple pieces of joined semiconductor material allows circuits of higher complexity to be fabricated and allows finer pitches (closer spacings between adjacent elements, such as pixel elements) which can, for example, in the context of an image sensor, increase image resolution.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
A stacked integrated circuit structure with shield structures providing signal integrity preservation, such as shielding or parasitic capacitance reduction, around electrically conductive pads on both sides of mating die surfaces is described. Stacking of integrated circuit structures allows three-dimensional integration of circuitry. The ability to extend circuitry in a third dimension can reduce the amount of area occupied in the other two dimensions, which can increase density of arrays of circuit elements, such as circuit elements for pixels in an image sensor. However, interconnections in the third dimension between stacked integrated circuit structures can be susceptible to signal integrity degradation, for example, from interference, such as crosstalk, between adjacent interconnections or, for example, from a low-pass filtering effect of parasitic capacitance arising from dielectric material between interconnections. In accordance with at least one embodiment, shield structures are provided, which may, for example, be of electrically conductive material, either isolated by dielectric material or connected to a voltage source, to shield an interconnection comprising two mating electrically conductive pads or which may, for example, be of low-dielectric-constant (low-K) material to reduce parasitic capacitance.
A plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are disposed in common plane 100. In the example, each electrically conductive pad provides an electrical connection for one corresponding pixel 120. A plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 are disposed in common plane 100. The plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 are disposed in interstitial region 101. Interstitial region 101 is spaced by dielectric margins 191, 192, 193, 194, 195, 196, 197, 198, and 199, respectively, away from electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182. In some embodiments, interstitial region 101 is itself dielectric.
In some embodiments, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 have individual top geometries with smaller areas than individual top geometries of the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182. In some embodiments, each of the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 is surrounded by a plurality of the shield structures (e.g., 103, 113, etc.), which are evenly spaced in a closed path individual to and surrounding that conductive pad.
The plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 block electrical crosstalk between the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 and/or reduce capacitive coupling between the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182. Hence, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 shield the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 from each other. Further, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 may be regarded as signal integrity preservation structures, signal integrity protection features, or the like.
By shielding the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182, performance of a three-dimensional (e.g., stacked) integrated circuit accommodating the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 and the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 is enhanced. In the case of an image sensor where neighboring conductive pads are simultaneously carrying signals during image readout, crosstalk and/or capacitive coupling may negatively impact image quality of the image sensor. Hence, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 may enhance image quality.
Further, crosstalk and/or capacitive coupling increase as the three-dimensional integrated circuit is scaled down and the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 get closer and closer together. Because of the shielding by the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129, the three-dimensional integrated circuit may reach smaller sizes without compromising performance.
For each of the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182, several of the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 are located peripherally to the electrically conductive pad of the electrically conductive pads. For example, for electrically conductive pad 102, shield structures 103, 104, 105, and 114 are peripheral to electrically conductive pad 102. Shield structures 103, 104, 105, and 114 surround electrically conductive pad 102. Shield structures 103, 104, 105, and 114 are disposed within interstitial region 101, which is spaced a dielectric margin 191 away from electrically conductive pad 102. As another example, for electrically conductive pad 112, shield structures 113, 114, 115, and 124 are peripheral to electrically conductive pad 112. Shield structures 113, 114, 115, and 124 surround electrically conductive pad 112. Shield structures 113, 114, 115, and 124 are disposed within interstitial region 101, which is spaced a dielectric margin 192 away from electrically conductive pad 112.
The shield structures peripheral to one electrically conductive pad need not be exclusively peripheral to that single electrically conductive pad but can be peripheral to a different electrically conductive pad as well. For example, shield structure 114 is peripheral to both electrically conductive pad 102 and electrically conductive pad 112. The shield structures that participate in surrounding one electrically conductive pad need not be exclusive in participating to surrounding that single electrically conductive pad but can also participate in surrounding a different electrically conductive pad. For example, shield structure 114 participates, along with shield structures 103, 104, and 105, in surrounding electrically conductive pad 102 but also participates, along with shield structures 113, 115, and 124, in surrounding electrically conductive pad 112.
While shield structure 114 is shown as bisecting a distance between electrically conductive pad 102 and electrically conductive pad 112 in line with the closest proximity of electrically conductive pad 102 to electrically conductive pad 112, a shield structure need not be equidistant from two electrically conductive pads and need not be situated along a line between the points of two electrically conductive pads at which the two electrically conductive pads are closest to one another. Rather, shield structures may be disposed anywhere within an interstitial region 101 separated by dielectric margins, such as dielectric margins 191, 192, 193, 194, 195, 196, 197, 198, and 199, from electrically conductive pads, such as electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182. Examples of various placements of shield structures relative to electrically conductive pads will be described further below.
In some embodiments, at least some of the first floating electrical shielding structures surround an electrically conductive pad at a first distance that bisects a first spacing of the electrically conductive pad from rectilinearly adjacent electrically conductive pads.
In some embodiments, the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are or comprise aluminum, copper, aluminum copper, some other suitable metals, or any combination of the foregoing. In some embodiments, the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 have larger areas than the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129. In some embodiments, the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are representative (e.g., in terms of material, size, shape, etc.) of the additional electrically conductive pads hereafter introduced and described.
In some embodiments, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 are conductive. For example, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 may be or comprise aluminum, copper, aluminum copper, some other suitable metals, or any combination of the foregoing. In some of such embodiments, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 are electrically floating. In other embodiments, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 are biased to ground or some other suitable potential.
In other embodiments, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 are dielectric. For example, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 may be or comprise a low k dielectric and/or the like. A low k dielectric may, for example, be or comprise a dielectric having a dielectric constant less than about 3.9, 2.0, or some other suitable value, and/or may, for example, be or comprise a dielectric having a dielectric constant less than dielectric margins 191, 192, 193, 194, 195, 196, 197, 198, and 199.
To the extent that the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 are conductive, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 may reduce crosstalk between the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182. To the extent that the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 are or comprise a low k dielectric, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 may reduce capacitive coupling between the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182.
In some embodiments, the plurality of shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 are representative (e.g., in terms of material, size, shape, etc.) of the additional shield structures hereafter introduced and described.
An integrated circuit chip 260 lies below bonding interface plane 210, and an integrated circuit chip 270 lies above bonding interface plane 210. An interface circuit chip may, for example, additionally or alternatively be regarded as an integrated circuit die, a wafer portion, or the like. The integrated circuit chip 260 comprises a substrate 111 covered by a dielectric layer 190, and the integrated circuit chip 270 comprises a substrate 211 and a dielectric layer 290 underlying substrate 211. The substrate 211 accommodates the photodiodes 202, and the dielectric layer 190 and the dielectric layer 290 directly contact at bonding interface plane 210.
Electrically conductive pad 132 of integrated circuit chip 260 is ohmically connected to electrically conductive pad 232 of integrated circuit chip 270 at bonding interface plane 210. Electrically conductive pad 142 of integrated circuit chip 260 is ohmically connected to electrically conductive pad 242 of integrated circuit chip 270 at bonding interface plane 210. Electrically conductive pad 152 of integrated circuit chip 260 is ohmically connected to electrically conductive pad 252 of integrated circuit chip 270 at bonding interface plane 210. Electrically conductive pads 132, 142, 152 are in dielectric layer 190, whereas electrically conductive pads 232, 242, 252 are in dielectric layer 290.
Because dielectric layer 190 and dielectric layer 290 directly contact at bonding interface plane 210, bonding interface plane 210 has a dielectric-to-dielectric bond. Further, because electrically conductive pads 132, 142, 152 electrically couple respectively with electrically conductive pads 232, 242, 252 at bonding interface plane 210, bonding interface plane 210 has a conductor-to-conductor bond. Hence, bonding interface plane 210 may be regarded as a metal-to-metal (M-M) and dielectric-to-dielectric (D-D) bonding plane, and integrated circuit chip 260 and integrated circuit chip 270 may be regarded as being M-M and D-D bonded together.
In some aspects, electrically conductive pads 132, 142, 152 can be disposed in dielectric layer 190, and electrically conductive pads 232, 242, and 252 can be disposed in dielectric layer 290. In some aspects, a liner may be provided between electrically conductive pads 132, 142, 152 and dielectric layer 190 or between electrically conductive pads 232, 242, 252 and dielectric layer 290. A liner layer between electrically conductive pads 132, 142, 152 and dielectric layer 190 may, for example, cover bottom surfaces and sidewalls of electrically conductive pads 132, 142, 152. In some embodiments, the liner layer may have a U-shaped shaped profile or some other suitable profile wrapping around a bottom of each electrically conductive pad 132, 142, 152. Similarly, a liner layer between electrically conductive pads 232, 242, and 252 and dielectric layer 290 may, for example, cover top surfaces and sidewalls of electrically conductive pads 232, 242, and 252. In some embodiments, the liner layer may have an inverted U-shaped shaped profile or some other suitable profile wrapping around a top of each electrically conductive pad 232, 242, and 252. In some embodiments, the liner layer of electrically conductive pads 132, 142, 152 and/or the liner layer of electrically conductive pads 232, 242, and 252 may, for example, be conductive and/or configured as a diffusion barrier for material of the conductive paths.
A surface of electrically conductive pad 132 opposite the surface connected to electrically conductive pad 232 is ohmically connected to an electrically conductive contact 131. A surface of electrically conductive pad 142 opposite the surface connected to electrically conductive pad 242 is ohmically connected to an electrically conductive contact 141. A surface of electrically conductive pad 152 opposite the surface connected to electrically conductive pad 252 is ohmically connected to an electrically conductive contact 151. A surface of electrically conductive pad 232 opposite the surface connected to electrically conductive pad 132 is ohmically connected to an electrically conductive contact 231. A surface of electrically conductive pad 242 opposite the surface connected to electrically conductive pad 142 is ohmically connected to an electrically conductive contact 241. A surface of electrically conductive pad 252 opposite the surface connected to electrically conductive pad 152 is ohmically connected to an electrically conductive contact 251.
An end of electrically conductive contact 131 opposite the end connected to electrically conductive pad 132 is ohmically connected to an electrically conductive feature 161. An end of electrically conductive contact 141 opposite the end connected to electrically conductive pad 142 is ohmically connected to an electrically conductive feature 171. An end of electrically conductive contact 151 opposite the end connected to electrically conductive pad 152 is ohmically connected to an electrically conductive feature 181. An end of electrically conductive contact 231 opposite the end connected to electrically conductive pad 232 is ohmically connected to an electrically conductive feature 261. An end of electrically conductive contact 241 opposite the end connected to electrically conductive pad 242 is ohmically connected to an electrically conductive layer feature 271. An end of electrically conductive contact 251 opposite the end connected to electrically conductive pad 252 is ohmically connected to an electrically conductive layer feature 281. Electrically conductive layer pads, such as electrically conductive features 161, 171, and 181, may be formed in an electrically conductive layer, such as a metal layer, for example, a top metal layer. In some aspects, a barrier layer may be provided, for example, between electrically conductive features 161, 171, or 181 and substrate 111 or between electrically conductive features 261, 271, or 281 and substrate 211.
Shield structures 106, 116, 126, and 136 are disposed peripherally with respect to electrically conductive pads 132, 142, and 152. As examples, shield structures 106 and 116 are disposed peripherally with respect to electrically conductive pad 132, shield structures 116 and 126 are disposed peripherally with respect to electrically conductive pad 142, and shield structures 126 and 136 are disposed peripherally with respect to electrically conductive pad 152. As examples, shield structure 116 is peripheral to both electrically conductive pad 132 and electrically conductive pad 142, and shield structure 126 is peripheral to both electrically conductive pad 142 and electrically conductive pad 152.
Shield structures 206, 216, 226, and 236 are disposed peripherally with respect to electrically conductive pads 232, 242, and 252. As examples, shield structures 206 and 216 are disposed peripherally with respect to electrically conductive pad 232, shield structures 216 and 226 are disposed peripherally with respect to electrically conductive pad 242, and shield structures 226 and 236 are disposed peripherally with respect to electrically conductive pad 252. As examples, shield structure 216 is peripheral to both electrically conductive pad 232 and electrically conductive pad 242, and shield structure 226 is peripheral to both electrically conductive pad 242 and electrically conductive pad 252.
A surface of shield structure 106 in or near bonding interface plane 210 faces a surface of shield structure 206 in or near bonding interface plane 210. A surface of shield structure 116 in or near bonding interface plane 210 faces a surface of shield structure 216 in or near bonding interface plane 210. A surface of shield structure 126 in or near bonding interface plane 210 faces a surface of shield structure 226 in or near bonding interface plane 210. A surface of shield structure 136 in or near bonding interface plane 210 faces a surface of shield structure 236 in or near bonding interface plane 210. The opposing surfaces of shield structures may be in contact with one another or in close proximity. For example, the proximity may be close enough such that the capacitive coupling of one shield structure, such as shield structure 106, to its opposing shield structure, such as shield structure 206, is of low capacitive reactance at frequencies of signals for which shielding is provided, such as a signal being communicated between electrically conductive pad 132 and electrically conductive pad 232, so as to provide effective shielding.
Because shield structures 106, 116, 126, 136 in integrated circuit chip 260 are paired respectively with shield structures 206, 216, 226, 236 in integrated circuit chip 270, shielding is symmetrical about bonding interface plane 210. In some embodiments, shield structures 106, 116, 126, 136 have individual top geometries that are respectively the same as individual top geometries of shield structures 206, 216, 226, 236. In some embodiments, shield structures 106, 116, 126, 136 have individual top geometries that are circular, square, or the like.
In some embodiments, the plurality of electrically conductive pads 132, 142, 152, 232, 242, 252 are or comprise aluminum, copper, aluminum copper, some other suitable metals, or any combination of the foregoing. Other electrically conductive pads hereafter introduced and described are conductive and may, for example, be or comprise a same material as the plurality of electrically conductive pads 132, 142, 152, 232, 242, 252.
In some embodiments, the plurality of shield structures 106, 116, 126, 136, 206, 216, 226, 236 are conductive. For example, the plurality of shield structures 106, 116, 126, 136, 206, 216, 226, 236 may be or comprise aluminum, copper, aluminum copper, some other suitable metals, or any combination of the foregoing. In some of such embodiments, the plurality of shield structures 106, 116, 126, 136, 206, 216, 226, 236 are electrically floating. In other embodiments, the plurality of shield structures 106, 116, 126, 136, 206, 216, 226, 236 are biased to ground or some other suitable potential.
In other embodiments, the plurality of shield structures 106, 116, 126, 136, 206, 216, 226, 236 are dielectric. For example, the plurality of shield structures 106, 116, 126, 136, 206, 216, 226, 236 may be or comprise a low k dielectric and/or the like. A low k dielectric may, for example, be or comprise a dielectric having a dielectric constant less than about 3.9, 2.0, or some other suitable value, and/or may, for example, be or comprise a dielectric having a dielectric constant less than dielectric material immediately surrounding the plurality of shield structures 106, 116, 126, 136, 206, 216, 226, 236 (e.g., dielectric layers 190, 290).
Other shield structures hereafter introduced and described may, for example, be or comprise a same material as the plurality of shield structures 106, 116, 126, 136, 206, 216, 226, 236. For example, such other shield structures may be conductive or dielectric, floating or biased, and so on.
A plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are disposed in common plane 300. In the example, each electrically conductive pad provides an electrical connection for one corresponding pixel. Shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 are disposed in plane 300 and centered between centers of adjacent electrically conductive pads, such as between two adjacent electrically conductive pads among electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182, which are also disposed in plane 300. For example, shield structure 114 is centered between centers of electrically conductive pads 102 and 112, bisecting a line between closest points of electrically conductive pad 102 to electrically conductive pad 112. As another example, shield structure 124 is centered between centers of electrically conductive pads 112 and 122, bisecting a line between closest points of electrically conductive pad 112 to electrically conductive pad 122. Likewise, along an orthogonal axis, shield structure 105 is centered between centers of electrically conductive pads 102 and 132, bisecting a line between closest points of electrically conductive pad 102 to electrically conductive pad 132. As another example, shield structure 115 is centered between centers of electrically conductive pads 112 and 142, bisecting a line between closest points of electrically conductive pad 112 to electrically conductive pad 142. The axes along which the shield structures are located relative to the electrically conductive pads for which they provide shielding are aligned with the axes of the pixel array for which the electrically conductive pads provide signal communication.
As an example, shield structures can be thought of as being in front of, in back of, to the left of, and to the right of an electrically conductive pad. For example, electrically conductive pad 142 has shield structure 115 in front of it, shield structure 117 in back of it, shield structure 116 to the left of it, and shield structure 126 to the right of it. Thus, four shield structures are peripheral to electrically conductive pad 142.
In some embodiments, the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are in a plurality of rows (e.g., x dimension) and a plurality of columns (e.g., y dimension). Further, the shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, and 129 alternate one to one with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 along the rows and the columns.
A plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are disposed in common plane 400. In the example, each electrically conductive pad provides an electrical connection for one corresponding pixel. The example shown in
The shield structures in the front left, front right, rear left, and rear right locations relative to an electrically conductive pad are centered between the centers of four electrically conductive pads in a square or rectangular relationship. For example, shield structure 457 is centered between the centers of electrically conductive pads 142, 152, 172, and 182.
In some embodiments, the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are in a plurality of rows (e.g., x dimension) and a plurality of columns (e.g., y dimension). The shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 118, 128, 138, 109, 119, 129, 433, 443, 453, 463, 435, 445, 455, 465, 437, 447, 457, 467, 439, 449, 459, and 469 (the shield structures) alternate one to one with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 along the rows and the columns. Further, the shield structures alternate one to one with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 diagonally (e.g., transverse to the rows and the columns).
A plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are disposed in common plane 500. In the example, each electrically conductive pad provides an electrical connection for one corresponding pixel. As shown in
For example, electrically conductive pad 142 is surrounded by eight shield structures 115, 515, 116, 556, 117, 557, 126, and 526 at 45-degree increments around electrically conductive pad 142. Shield structure 115 is located in front of electrically conductive pad 142. Shield structure 515 is located at the front left of electrically conductive pad 142, 45 degrees clockwise from shield structure 115, as viewed from above. Shield structure 116 is located at the front left of electrically conductive pad 142, 45 degrees clockwise from shield structure 515, as viewed from above. Shield structure 556 is located at the front left of electrically conductive pad 142, 45 degrees clockwise from shield structure 116, as viewed from above. Shield structure 117 is located at the front left of electrically conductive pad 142, 45 degrees clockwise from shield structure 556, as viewed from above. Shield structure 557 is located at the front left of electrically conductive pad 142, 45 degrees clockwise from shield structure 117, as viewed from above. Shield structure 126 is located at the front left of electrically conductive pad 142, 45 degrees clockwise from shield structure 557, as viewed from above. Shield structure 526 is located at the front left of electrically conductive pad 142, 45 degrees clockwise from shield structure 126, as viewed from above.
As another example, electrically conductive pad 102 is surrounded by eight shield structures 103, 503, 104, 504, 105, 545, 114, and 514 at 45-degree increments around electrically conductive pad 102. As another example, electrically conductive pad 112 is surrounded by eight shield structures 113, 513, 114, 554, 115, 555, 124, and 524 at 45-degree increments around electrically conductive pad 112. For example, electrically conductive pad 122 is surrounded by eight shield structures 123, 523, 124, 564, 125, 565, 134, and 534 at 45-degree increments around electrically conductive pad 122. For example, electrically conductive pad 132 is surrounded by eight shield structures 105, 505, 106, 506, 107, 547, 116, and 516 at 45-degree increments around electrically conductive pad 132. For example, electrically conductive pad 152 is surrounded by eight shield structures 125, 525, 126, 566, 127, 567, 136, and 536 at 45-degree increments around electrically conductive pad 152. For example, electrically conductive pad 162 is surrounded by eight shield structures 107, 507, 108, 508, 109, 509, 118, and 518 at 45-degree increments around electrically conductive pad 162. For example, electrically conductive pad 172 is surrounded by eight shield structures 117, 517, 118, 548, 119, 519, 128, and 528 at 45-degree increments around electrically conductive pad 172. For example, electrically conductive pad 182 is surrounded by eight shield structures 127, 527, 128, 558, 129, 529, 138, and 538 at 45-degree increments around electrically conductive pad 182.
Different numbers of shield structures can surround an electrically conductive pad at increments of different numbers of degrees. The increments may be, or need not be, equal in angular spacing. A shield structure may serve to surround more than one electrically conductive pad. For example, shield structure 116 surrounds electrically conductive pad 142 on its left side and surrounds electrically conductive pad 132 on its right side. As another example, shield structure 126 surrounds electrically conductive pad 142 on its right side and surrounds electrically conductive pad 152 on its left side. As yet another example, shield structure 115 surrounds electrically conductive pad 142 on its front side and surrounds electrically conductive pad 112 on its back side. While some shield structures, such as shield structures 116, 126, and 115, discussed above, may be located at a constant radius from each of two different electrically conductive pads, and the respective constant radii of the two different electrically conductive pads may be the same or different, other shield structures may be located at a constant radius from a particular single electrically conductive pad to which they are proximate, such as shield structures 515, 556, 557, and 526, proximate to electrically conductive pad 142. A shield structure may be located at unequal distances from two electrically conductive pads between which it lies. For example, shield structure 557 may be located closer to electrically conductive pad 142 and farther from electrically conductive pad 182 along a line between the centers of electrically conductive pad 142 and electrically conductive pad 182. Along that same line, shield structure 527 is located closer to electrically conductive pad 182 and farther from electrically conductive pad 142. As both shield structure 557 and shield structure 527 lie between electrically conductive pad 142 and electrically conductive pad 182, both shield structure 557 and shield structure 527 can contribute to improving signal communication performance for both electrically conductive pad 142 and electrically conductive pad 182. Thus, a single shield structure can contribute to improving signal communication performance for a plurality of electrically conductive pads. As one example, a shield structure can be electrically conductive and can provide a shielding function to electrically shield a signal being communicated via one electrically conductive pad from interference, such as crosstalk, from a different signal being communicated via a different electrically conductive pad. As a further example, an electrically conductive shield structure may be made of a magnetic material to provide magnetic and electrical shielding. As another example, a shield structure may be made of a low-dielectric-constant (low-K) material to reduce the parasitic capacitance between two electrically conductive pads according to C=K ε0 A/d, where K is the dielectric constant, ε0 is the permittivity of space, A is the area of the capacitor plates, and d is the distance between the capacitor plates (where the A/d terms are simplified in relation to “plates” as compared with the three-dimensional features of the electrically conductive pads). The reduction of parasitic capacitance between electrically conductive pads reduces coupling (e.g., crosstalk) of signals between the electrically conductive pads.
In some embodiments, the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are in a plurality of rows (e.g., x dimension) and a plurality of columns (e.g., y dimension). The shield structures 103, 113, 123, et al. (the shield structures) alternate one to one with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 along the rows and the columns. Further, the shield structures alternate many to one with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 diagonally (e.g., transverse to the rows and the columns).
The example of
In some embodiments, the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are in a plurality of rows (e.g., x dimension) and a plurality of columns (e.g., y dimension). The shield structures 103, 113, 123, et al. (the shield structures) alternate one to one with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 along the rows and the columns. Further, the shield structures alternate one to one with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 diagonally (e.g., transverse to the rows and the columns). The shield structures alternating diagonally with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 have individual top geometries that are larger (e.g., span a larger area) than the shield structures alternating with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 along the rows and the columns. In some embodiments, the shield structures alternating diagonally with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 have individual top geometries that are the same as individual top geometries of the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182.
A plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are disposed in common plane 700. In the example, each electrically conductive pad provides an electrical connection for one corresponding pixel. The example of
In some embodiments, the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are in a plurality of rows (e.g., x dimension) and a plurality of columns (e.g., y dimension). The shield structures 103, 113, 123, et al. (the shield structures) alternate one to one with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 along the rows and the columns. The shield structures alternating with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 along the rows have individual top geometries that are rectangular and elongated (e.g., have greatest dimensions) orthogonal to the rows. The shield structures alternating with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 along the columns have individual top geometries that are rectangular and elongated (e.g., have greatest dimensions) orthogonal to the columns.
The example of
In some embodiments, the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are in a plurality of rows (e.g., x dimension) and a plurality of columns (e.g., y dimension). The shield structures 803, 813, 823, 833, et al. (the shield structures) alternate one to one with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 diagonally (e.g., transverse to the rows and the columns).
The example of
In some embodiments, the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 are in a plurality of rows (e.g., x dimension) and a plurality of columns (e.g., y dimension). The shield structures 103, 113, 123, 104, 114, 124, 134, 105, 115, 125, 106, 116, 126, 136, 107, 117, 127, 108, 113, 128, 138, 109, 119, and 129 alternate one to one with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 along the rows and the columns. Further, the shield structures 803, 813, 823, 833, 805, 815, 825, 835, 807, 817, 827, 837, 809, 819, 829, and 839 alternate one to one with the plurality of electrically conductive pads 102, 112, 122, 132, 142, 152, 162, 172, and 182 diagonally.
The example of
Shield structures in the form of parallel strips aligned with a first axis of a rectilinear pixel array include shield structures 103, 113, and 123 forming a first strip aligned with the first axis, shield structures 105, 115, and 125 forming a second strip aligned with the first axis, shield structures 107, 117, and 127 forming a third strip aligned with the first axis, shield structures 109, 119, and 129 forming a fourth strip aligned with the first axis, shield structures 104, 106, and 108 forming a first strip aligned with a second axis of the rectilinear pixel array, the second axis orthogonal to the first axis, shield structures 114, 116, and 118 forming a second strip aligned with the second axis, shield structures 124, 126, and 128 forming a third strip aligned with the second axis, and shield structures 134, 136, and 138 forming a fourth strip aligned with the second axis.
The continuous rectilinear grid can be left floating or can be connected to a voltage source. As one example, the voltage source may be ground. As one example, a continuous rectilinear grid made of low-K material may be left floating.
After fabrication of integrated circuit chip 1060 and integrated circuit chip 1070, a bond surface, such as a M-M and D-D bond surface of a bond layer, such as a M-M and D-D bond layer, in which electrically conductive pads, such as electrically conductive pad 132, and shield structures, such as shield structures 106, 116, are disposed in integrated circuit chip 1060 is mated to a bond surface, such as a M-M and D-D bond surface, of a bond layer, such as a M-M and D-D bond layer in which electrically conductive pads, such as electrically conductive pad 232, and shield structures, such as shield structure 216 are disposed in integrated circuit chip 1070. For example, such mating aligns electrically conductive pad 132 with electrically conductive pad 232 and establishes contact between them to provide an ohmic connection. As yet another example, such mating aligns shield structure 216 with shield structure 116. The mating can provide contact between shield structure 216 and shield structure 116 to provide an ohmic connection. Alternatively, an ohmic connection need not be established. In the case of a low-k dielectric material, a gap between shield structure 216 and shield structure 116 would not be inconsistent with providing low-k material within the regions of shield structure 216, shield structure 116, and any gap therebetween. In the case of an electrically conductive material, a gap between shield structure 216 and shield structure 116 would allow capacitive coupling of the shield structures, and the resulting capacitive connection could have a low enough capacitive reactance to provide similarly effective shielding as compared to an ohmic connection.
As
A dielectric region 1132, which, for example, may be an insulator layer (e.g., an oxide layer), of integrated circuit chip 1180 is joined to a dielectric layer 1133, which, for example, may be an insulator layer (e.g., an oxide layer), of integrated circuit chip 1190. Further, integrated circuit chip 1190 is joined to integrated circuit chip 1060 along bonding interface plane 210. After fabrication of at least a portion of integrated circuit chip 1180 and integrated circuit chip 1190, a dielectric-to-dielectric (e.g., oxide-to-oxide) bond is made between dielectric region 1132 and dielectric layer 1133. Through-oxide vias (TOVs) are formed, and other features are formed, as will be discussed below with reference to
After fabrication of integrated circuit chip 1060 and integrated circuit chip 1190, a bond surface, such as a M-M and D-D bond surface, of a bond layer, such as a M-M and D-D bond layer, in which electrically conductive pads, such as electrically conductive pad 132, and shield structures, such as shield structures 106, 116, are disposed in integrated circuit chip 1060 is mated to a bond surface, such as a M-M and D-D bond surface, of a bond layer, such as a M-M and D-D bond layer, in which electrically conductive pads, such as electrically conductive pad 232, and shield structures, such as shield structures 206, 216 are disposed in integrated circuit chip 1190. For example, such mating aligns electrically conductive pad 132 with electrically conductive pad 232 and establishes contact between them to provide an ohmic connection. As yet another example, such mating aligns shield structure 106 with shield structure 206. The mating can provide contact between shield structure 106 and shield structure 206 to provide an ohmic connection. Alternatively, an ohmic connection need not be established. In the case of a low-k dielectric material, a gap between shield structure 106 and shield structure 206 would not be inconsistent with providing low-k dielectric material within the regions of shield structure 106, shield structure 206, and any gap therebetween. In the case of an electrically conductive material, a gap between shield structure 106 and shield structure 206 would allow capacitive coupling of the shield structures, and the resulting capacitive connection could have a low enough capacitive reactance to provide similarly effective shielding as compared to an ohmic connection.
As
The TOVs of
Integrated circuit chip 1280 is mated to integrated circuit chip 1290 along bonding interface plane 210. After fabrication of integrated circuit chip 1280 and integrated circuit chip 1290, a bond surface, such as a M-M and D-D bond surface, of a bond layer, such as a M-M and D-D bond layer, in which electrically conductive pads, such as electrically conductive pad 132, and shield structures, such as shield structures 106, 116, are disposed in integrated circuit chip 1290 is mated to a bond surface, such as a M-M and D-D bond surface, of a bond layer, such as a M-M and D-D bond layer, in which electrically conductive pads, such as electrically conductive pad 232, and shield structures, such as shield structures 206, 216, are disposed in integrated circuit chip 1280.
For example, such mating aligns electrically conductive pad 132 with electrically conductive pad 232 and establishes contact between them to provide an ohmic connection. As another example, such mating aligns shield structure 106 with shield structure 206. The mating can provide contact between shield structure 106 and shield structure 206 to provide an ohmic connection. Alternatively, an ohmic connection need not be established. In the case of a low-k dielectric material, a gap between shield structure 106 and shield structure 206 would not be inconsistent with providing low-k dielectric material within the regions of shield structure 106, shield structure 206, and any gap therebetween. In the case of an electrically conductive material, a gap between shield structure 106 and shield structure 206 would allow capacitive coupling of the shield structures, and the resulting capacitive connection could have a low enough capacitive reactance to provide similarly effective shielding as compared to an ohmic connection.
Integrated circuit chip 1060 is mated to integrated circuit chip 1290 along bonding interface plane 1210. After fabrication of integrated circuit chip 1060 and integrated circuit chip 1290, a bond surface, such as a M-M and D-D bond surface, of a bond layer, such as a M-M and D-D bond layer, in which electrically conductive pads, such as electrically conductive pads 1207, 1217, 1227, and shield structures, such as shield structure 1225, are disposed in integrated circuit chip 1060 is mated to a bond surface, such as a M-M and D-D bond surface, of a bond layer, such as a M-M and D-D bond layer, in which electrically conductive pads, such as electrically conductive pads 1207, 1217, and shield structures, such as shield structures 1206, 1226, are disposed in integrated circuit chip 1290.
For example, such mating aligns shield structure 1225 with shield structure 1226. The mating can provide contact between shield structure 1225 and shield structure 1226 to provide an ohmic connection. Alternatively, an ohmic connection need not be established. Other elements shown in
A circuit portion of integrated circuit chip 1060 is connected to electrically conductive contact 131, which is connected to electrically conductive pad 132, which mates to electrically conductive pad 232 of integrated circuit chip 1070 at bonding interface plane 210. Electrically conductive pad 232 is connected to electrically conductive contact 231. Shield structures 106 and 116 are disposed proximate to and peripheral to electrically conductive pad 132. Shield structures 206 and 216 are disposed proximate to and peripheral to electrically conductive pad 232.
Photonic signals corresponding to illumination of pixel 120 are received correspondingly at photodiodes 202. Anodes of photodiodes 202 are connected to ground 1307. Cathode of photodiodes 202 are connected correspondingly to terminals of transfer gate transistors 1015 via contacts 1387. Terminals of transfer gate transistor 1015 are connected correspondingly to floating diffusion regions 1017 via conductors 1303. Terminals of reset transistors 1025 are connected correspondingly to floating diffusion regions 1017 via conductors 1302. Reset voltages at nodes 1301 are connected correspondingly to terminals of reset transistors 1025. Floating diffusion regions 1017 are referenced to ground 1307. Floating diffusion regions 1017 are connected correspondingly to gate terminals of source follower transistors 1045 via conductors 1304. Voltages at nodes 1305 are connected correspondingly to terminals of source follower transistors 1045. Terminals of source follower transistors 1045 are connected correspondingly to conductors 1306, which are connected correspondingly to terminals of select transistors 1035. Terminals of select transistors 1035 are connected correspondingly to electrically conductive contacts 231, 241. Electrically conductive contacts 231, 241 are connected correspondingly to electrically conductive pad 232, 242.
Photonic signals corresponding to illumination of pixel 120 are received correspondingly at photodiodes 202. Anodes of photodiodes 202 are connected to ground 1307. Cathode of photodiodes 202 are connected correspondingly to terminals of transfer gate transistors 1015 via contacts 1387. Terminals of transfer gate transistor 1015 are connected correspondingly to floating diffusion regions 1017 via conductors 1303. Terminals of reset transistors 1025 are connected correspondingly to floating diffusion regions 1017 via conductors 1302. Reset voltages at nodes 1301 are connected correspondingly to terminals of reset transistors 1025. Floating diffusion regions 1017 are referenced to ground 1307. Floating diffusion regions 1017 are connected correspondingly to gate terminals of source follower transistors 1045 via conductors 1304. Voltages at nodes 1305 are connected correspondingly to terminals of source follower transistors 1045. Terminals of source follower transistors 1045 are connected correspondingly to conductors 1306, which are connected correspondingly to terminals of select transistors 1035. Terminals of select transistors 1035 are connected correspondingly to electrically conductive contacts 231, 241. Electrically conductive contacts 231, 241 are connected correspondingly to electrically conductive pad 232, 242.
Electrically conductive pads 232, 242 of integrated circuit chip 1280 mate respectively to electrically conductive pads 132, 142 of integrated circuit chip 1290 at bonding interface plane 210. Electrically conductive pad 132 is connected to electrically conductive contact 131. Electrically conductive contact 131 is connected to in-pixel circuit 1411 of integrated circuit chip 1290. In-pixel circuit 1411 is connected to integrated circuit chip 1060. Shield structures 106, 116 are disposed proximate to and peripheral to electrically conductive pad 132. Shield structures 206, 216 are disposed proximate to and peripheral to electrically conductive pad 232. Shield structure 206 mates with shield structure 106. Shield structure 216 mates with shield structure 116.
Photonic signals corresponding to illumination of pixel 120 are received correspondingly at photodiodes 202. Anodes of photodiodes 202 are connected to ground 1307. Cathode of photodiodes 202 are connected correspondingly to terminals of transfer gate transistors 1015 via contacts 1387. Terminals of transfer gate transistor 1015 are connected correspondingly to electrically conductive pads 132, 142. Electrically conductive pads 232, 242 of integrated circuit chip 1280 mate with electrically conductive pad 132, 142 of integrated circuit chip 1290. Electrically conductive pads 232, 242 are correspondingly coupled to floating diffusion regions 1517. Floating diffusion region 1517 are correspondingly connected to terminals of reset transistor 1212. Terminals of reset transistors 1212 are correspondingly connected to reset voltage correspondingly 1501. Floating diffusion regions 1517 are correspondingly connected to gate terminals of source follower transistor correspondingly 1202. Floating diffusion regions 1517 are referenced to ground 1307. Voltages at nodes 1503 are correspondingly connected to terminals of source follower transistors 1202. Terminals of source follower transistors 1202 are correspondingly connected to terminals of select transistors 1222. Terminals of select transistors 1222 are correspondingly connected to electrically conductive pads, such as electrically conductive pad 1208.
Shield structures 206, 216, 226 are disposed proximate to and peripheral to electrically conductive pads 232, 242. Shield structures 106, 116, 126 are disposed proximate to and peripheral to electrically conductive pad 132, 142. Shield structures 206, 216, 226 mate respectively with shield structures 106, 116, 126.
Photonic signals corresponding to illumination of pixel 120 are received correspondingly at photodiodes 202. Anodes of photodiodes 202 are connected to ground 1307. Cathode of photodiodes 202 are connected correspondingly to terminals of transfer gate transistors 1015 via contacts 1387. Terminals of transfer gate transistor 1015 are connected correspondingly to electrically conductive pads 132, 142. Electrically conductive pads 232, 242 of integrated circuit chip 1280 mate with electrically conductive pad 132, 142 of integrated circuit chip 1290. Electrically conductive pads 232, 242 are correspondingly coupled to floating diffusion regions 1517. Floating diffusion region 1517 are correspondingly connected to terminals of reset transistor 1212. Terminals of reset transistors 1212 are correspondingly connected to reset voltage correspondingly 1601. Floating diffusion regions 1517 are correspondingly connected to gate terminals of source follower transistor correspondingly 1202. Floating diffusion regions 1517 are referenced to ground 1307. Voltages at nodes 1603 are correspondingly connected to terminals of source follower transistors 1202. Terminals of source follower transistors 1202 are correspondingly connected to terminals of select transistors 1222. Terminals of select transistors 1222 are correspondingly connected to in-pixel circuits 1611. In-pixel circuits 1611 are correspondingly connected to electrically conductive pads, such as electrically conductive pad 1218.
Electrically conductive pad 1207 is ohmically connected to electrically conductive contact 1902. Electrically conductive contact 1902 is ohmically connected to electrically conductive feature 2012 of electrically conductive features 1006. Electrically conductive pad 1217 is ohmically connected to electrically conductive contact 1904. Electrically conductive contact 1904 is ohmically connected to electrically conductive feature 2002 of electrically conductive features 1006. Shield structures 2004, 2008, 1225 are formed in layer 2090. Planarization can be performed to bring the surfaces of electrically conductive pads 1207, 2006, 1217, 1227 and shield structures 2004, 2008, 1225, along with the surface of dielectric region 1021, to a planar surface, along bonding interface plane 2010. Such a planar surface is ready to be mated to another planar surface with corresponding electrically conductive pads and shield structures.
In some embodiments, a process for forming electrically conductive pads 1207, 2006, 1217, 1227 and shield structures 2004, 2008, 1225 comprises: 1) patterning dielectric region 1021 to concurrently form openings corresponding to electrically conductive pads 1207, 2006, 1217, 1227 and shield structures 2004, 2008, 1225; 2) depositing a conductive layer to fill the openings; and 3) performing a planarization into the conductive layer. In other embodiments, the process comprises: 1) patterning dielectric region 1021 to form first openings corresponding to electrically conductive pads 1207, 2006, 1217, 1227; 2) depositing a first conductive layer to fill the first openings; 3) performing a first planarization into the first conductive layer; 4) after the first planarization, patterning dielectric region 1021 to form second openings corresponding to shield structures 2004, 2008, 1225; 5) depositing a second conductive layer or a low-k dielectric layer to fill the second openings; and 6) performing a second planarization into the second conductive layer or a low-k dielectric layer.
In
In some embodiments, a process for forming electrically conductive pad 132 and shield structures 106, 116 comprises: 1) patterning dielectric region 1211 to concurrently form openings corresponding to electrically conductive pad 132 and shield structures 106, 116; 2) depositing a conductive layer to fill the openings; and 3) performing a planarization into the conductive layer. In other embodiments, the process comprises: 1) patterning dielectric region 1211 to form first openings corresponding to electrically conductive pad 132; 2) depositing a first conductive layer to fill the first openings; 3) performing a first planarization into the first conductive layer; 4) after the first planarization, patterning dielectric region 1211 to form second openings corresponding to shield structures 106, 116; 5) depositing a second conductive layer or a low-k dielectric layer to fill the second openings; and 6) performing a second planarization into the second conductive layer or a low-k dielectric layer.
In
In some embodiments, a process for forming electrically conductive pads 1208, 2902, 1218, 2906 and shield structures 1206, 2904, 1226 comprises: 1) patterning dielectric region 1221 to concurrently form openings corresponding to electrically conductive pads 1208, 2902, 1218, 2906 and shield structures 1206, 2904, 1226; 2) depositing a conductive layer to fill the openings; and 3) performing a planarization into the conductive layer. In other embodiments, the process comprises: 1) patterning dielectric region 1221 to form first openings corresponding to electrically conductive pads 1208, 2902, 1218, 2906; 2) depositing a first conductive layer to fill the first openings; 3) performing a first planarization into the first conductive layer; 4) after the first planarization, patterning dielectric region 1221 to form second openings corresponding to shield structures 1206, 2904, 1226; 5) depositing a second conductive layer or a low-k dielectric layer to fill the second openings; and 6) performing a second planarization into the second conductive layer or a low-k dielectric layer.
In
In
In some embodiments, a process for forming electrically conductive pad 232 and shield structures 206, 216 comprises: 1) patterning dielectric region 1291 to concurrently form openings corresponding to electrically conductive pad 232 and shield structures 206, 216; 2) filling the openings with a conductive layer; and 3) performing a planarization into the conductive layer. In other embodiments, the process comprises: 1) patterning dielectric region 1291 to form first openings corresponding to electrically conductive pad 232; 2) depositing a first conductive layer to fill the first openings; 3) performing a first planarization into the first conductive layer; 4) after the first planarization, patterning dielectric region 1291 to form second openings corresponding to shield structures 206, 216; 5) depositing a second conductive layer or a low-k dielectric layer to fill the second openings; and 6) performing a second planarization into the second conductive layer or a low-k dielectric layer.
In some embodiments, a process for forming electrically conductive pad 232 and shield structures 206, 216 comprises: 1) patterning dielectric region 1022 to concurrently form openings corresponding to electrically conductive pad 232 and shield structures 206, 216; 2) depositing a conductive layer to fill the openings; and 3) performing a planarization into the conductive layer. In other embodiments, the process comprises: 1) patterning dielectric region 1022 to form a first opening corresponding to electrically conductive pad 232; 2) depositing a first conductive layer to fill the first openings; 3) performing a first planarization into the first conductive layer; 4) after the first planarization, patterning dielectric region 1022 to form second openings corresponding to shield structures 206, 216; 5) depositing a second conductive layer or a low-k dielectric layer to fill the second openings; and 6) performing a second planarization into the second conductive layer or a low-k dielectric layer.
Along with electrically conductive pad 232, shield structures 206, 216 are formed in a layer (e.g., a M-M and D-D bond layer) at the surface 5210, at bonding interface plane 210, of dielectric region 1022. Planarization can be performed to bring the surfaces of electrically conductive pad 232 and shield structures 206, 216, along with the surface of dielectric region 1022, to a planar surface, along bonding interface plane 210. Such a planar surface is ready to be mated to another planar surface with corresponding electrically conductive pads and shield structures.
Also in
Note that the methods of
At act 5401, for a first integrated circuit chip, patterning a top electrically conductive layer (e.g., a metal layer) is performed. At act 5402, for the first integrated circuit chip, an interlayer dielectric is formed, for example, over the top electrically conductive layer. At act 5403, portions of the interlayer dielectric are removed to provide cavities for electrically conductive contacts. At act 5404, the electrically conductive contacts are formed in the cavities. At act 5405, a first plurality of electrically conductive pads are formed abutting the electrically conductive contacts, and a first plurality of first electrical shield structures are formed. In some embodiments, each electrically conductive pad of the first plurality of electrically conductive pads has a pad interface surface lying in an interface plane. In some embodiments, each first electrical shield structure of the first plurality of first electrical shield structures has a shielding structure interface surface lying in the interface plane. In some embodiments, the first plurality of first electrical shield structures are disposed interstitially to the first plurality of first electrically conductive pads. At act 5406, the first plurality of electrically conductive pads are mated to corresponding electrically conductive pads of a second integrated circuit chip along a mating plane. Acts 5401 through 5406 can correspond, for example, to the structure previously illustrated in
In some embodiments, a satellite-type bond (e.g., M-M and D-D bond) signal integrity preservation technique is provided. The technique can prevent degradation of signal integrity from interference (e.g., crosstalk) by providing signal shielding and can prevent degradation of signal integrity from low-pass filtering and loss by reducing parasitic capacitance.
Stacking of at least partially fabricated integrated circuit components (e.g., wafer stacking, die stacking, etc.) and interconnection of stacked integrated circuit components across an interface plane (e.g., through M-M and D-D bonding at a bonding plane) allows integrated circuit features (e.g., pixel elements) to be made smaller, but, as the pixel size is made smaller and the interconnection structures (e.g., electrically conductive (e.g., M-M bond) pads) is made closer, it can be easier for signal integrity issues to arise, so techniques for preserving signal integrity are useful.
Another aspect pertinent to signal integrity is that complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixel values are typically read sequentially across an CIS (e.g., from left to right, column by column), so the signals conveyed without regard to signal integrity preservation could easily interfere with each other.
However, by providing for preservation of signal integrity (e.g., mitigating potential interference between floating-diffusion (FD) regions), accurate communication of signals can be provided. Reduction of crosstalk from a signal of a FD region of one pixel (or group of pixels) to a signal of a FD region of another pixel (or another group of pixels) can reduce degradation of image quality and provide better images. Implementation can be applied to stacked-chip CISs, for example, two-chip CIS architectures and three-chip CIS architectures. Implementation can be applied to pixel-sharing CIS architectures (e.g., 2×2 pixel-sharing architectures).
In a stacked integrated circuit, a first chip in the stack can be referred to as a Tier 1 integrated circuit component. A second chip in the stack can be referred to as a Tier 2 integrated circuit component. In stacks of more than two chips, a third chip in the stack can be referred to as a Tier 3 integrated circuit component, and so on.
Abbreviations that may be seen are TX (or TG) for transfer gate, SF for source follower, RST for reset, SEL (or select) or row select, FD for floating diffusion region, DoP for device-on-photodiode, and M-M for metal-to-metal, D-D for dielectric-to-dielectric. M-M and D-D may be used to refer to bonds of metal-to-metal and dielectric-to-dielectric, as well as features associated with such bonds, such as a M-M and D-D layer in which M-M bond pads are formed and such as a M-M contact for providing an electrical connection to a M-M bond pad.
In some embodiments, electrically conductive elements, such as electrically conductive pads and electrically conductive contacts can be made of metal, such as copper or other metal, alloy, ceramic (e.g., indium tin oxide), etc.
In some embodiments, a two-tier (e.g., two-wafer, two-die, etc.) stacked integrated circuit structure may be made. As an example, an application-specific integrated circuit (ASIC) may be implemented on a first die or wafer, and features or functions such as PD, TX, SF, RST, and SEL may be implemented on a second die or wafer, with the first and second dies or wafers mated at a bonding interface to provide mechanical and electrical connections between the first and second dies or wafers.
In some embodiments, a three-tier (e.g., three-wafer, three-die, etc.) stacked integrated circuit structure may be made. As an example, an application-specific integrated circuit (ASIC) may be implemented on an integrated circuit component (e.g., a die or a wafer), features or functions such as SF, RST, and SEL may be implemented on a system-on-chip 2 (SoC2) integrated circuit component, and features or functions such as PD and TX may be implemented on a SoC1 integrated circuit component, with the SoC1 and SoC2 integrated circuit components mated at a bonding interface to provide mechanical and electrical connections between the SoC1 and SoC2 integrated circuit components, and an opposite side of the SoC2 integrated circuit component may be mated to the ASIC component to provide mechanical and electrical connections between the SoC2 and ASIC components.
In some embodiments, a shield structure can be fabricated in an interface layer, such as a M-M and D-D bond layer. In some embodiments, floating dummy electrically conductive pads (e.g., M-M bond pads) can be fabricated between electrically conductive pads (e.g., M-M bond pads) used for communicating signals. The signal integrity protection structure may be arranged as a satellite-type shielding structure, with signal integrity protection elements (e.g., electrically conductive (e.g., metal, alloy, a ceramic (e.g., indium tin oxide), etc.) or low-k dielectric elements) located at a constant radius from the center or edge of an electrically conductive pad, giving an appearance reminiscent of satellites orbiting a planet. In some embodiments, a slot-type shielding structure can be implemented, with elongated slots which can be filled with an electrically conductive material or a low-k dielectric material. In some embodiments, a mesh-type shielding structure can be implemented, with elongated slots intersecting along non-parallel (e.g., orthogonal) axes to form extended continuous regions of connected electrically conductive material or a low-k dielectric material. An electrically conductive mesh-type shielding structure can either be left unconnected or can be connected to a voltage source, for example, applying a bias voltage (e.g., ground or some other voltage) to the material.
In some embodiments, a signal integrity protection feature (e.g., an individual shield structure) may have a size of 10 percent to 80 percent of the size of an electrically conductive pad (e.g., a M-M bond pad). In some embodiments, the signal integrity protection feature may be formed in the shape of a circle, a square, a rectangle, an ellipse, a polygon, a cross (e.g., a plus-sign), an arc, or the like. In some embodiments, such as those with elongated signal integrity protection features (e.g., slot-type), such features may have a width of 10 percent to 80 percent of the size of an electrically conductive pad (e.g., a M-M bond pad) and a length of 10 percent to 200 percent of the size of an electrically conductive pad (e.g., a M-M bond pad). In the case of cross-type signal integrity protection feature, each of the crossed portions may have, for example, a width of 10 percent to 80 percent of the size of an electrically conductive pad (e.g., a M-M bond pad) and a length of 10 percent to 200 percent the size of an electrically conductive pad (e.g., a M-M bond pad). In the case of a mesh-type signal integrity protection feature, each of the crossed portions may have a width of 10 percent to 80 percent of the size of an electrically conductive pad (e.g., a M-M bond pad). In some embodiments, such as those with dummy pads (e.g., dummy M-M bond pads), signal integrity protection features may have a size equal to a size of an electrically conductive pad (e.g., a M-M bond pad).
In some embodiments, such as those with elongated signal integrity protection features (e.g., slot-type, cross-type, mesh-type, or the like), the signal integrity protection features can be constructed to be less adherent to opposing signal integrity protection features to which they are to be mated. For example, an elongated signal integrity protection feature can be recessed, either uniformly or non-uniformly, below the bonding plane to provide relief, which can, for example, help promote the escape of gas during the process of wafer bonding to avoid bubbles.
In some embodiments, with elongated signal integrity protection features, such as those which provide electrical continuity across several array elements, such as across several pixels of an image sensor array, the elongated signal integrity protection features can be left disconnected from external voltages, or the elongated signal integrity protection features can be connected to a voltage source (e.g., ground or some other voltage). Such a connection can, for example, be located outside the pixel array. An elongated signal integrity protection feature connected to a voltage source can be useful, for example, for electric field shielding applications.
In some embodiments, signal integrity protection features as described herein can be implemented in a two-chip CIS/ASIC three-dimensional integrated circuit. In some embodiments, signal integrity protection features as described herein can be implemented in a three-chip CIS/ASIC three-dimensional integrated circuit. An example of a three-chip CIS/ASIC three-dimensional integrated circuit can include, for example, a SoI-DoP implementation with through-oxide vias (TOVs) used to connect two chips and symmetric pairs of electrically conductive contacts and electrically conductive pads (e.g., a M-M bond interface) used to connect an ASIC chip to one of the other two chips. Another example of a three-chip CIS/ASIC three-dimensional integrated circuit can include a three-chip stacked pixel implementation with backside through-substrate vias (BTSVs) used to convey signals through as substrate to implement electrical connections on opposite sides of the middle chip of the stack of chips. Symmetric pairs of electrically conductive contacts and electrically conductive pads (e.g., a M-M bond interface) can be implemented on one or both of the opposite sides of the middle chip and the chips to which those sides mate to preserve signal integrity in a three-chip stacked pixel implementation. The term “chip” can refer to a semiconductor wafer, a semiconductor-on-insulator (SoI) (e.g., silicon-on-insulator) structure, at any of various stages of fabrication, or portions thereof (e.g., a die, a group of dies, or the like) which can be mechanically mated using at least one set of symmetric pairs of electrically conductive contacts and electrically conductive pads (e.g., a M-M bond interface).
An electrically conductive contact and an electrically conductive pad can be used to convey a signal originating from a single photodiode or from a group of photodiodes. As examples, two photodiodes, three photodiodes, four photodiodes, or more than four photodiodes can be grouped together to provide such a signal. A plurality of such signals can be communicated over time.
In some embodiments of the present disclosure, the present disclosure relate to an IC, including: a first IC chip including a first dielectric layer; a second IC chip bonded to the first IC chip at a bond interface and including a second dielectric layer directly contacting the first dielectric layer at the bond interface; a first pair of conductive pads respectively in the first and second dielectric layers and directly contacting at the bond interface; a second pair of conductive pads respectively in the first and second dielectric layers and directly contacting at the bond interface; and a pair of shield structures respectively in the first and second dielectric layers and directly contacting at the bond interface, wherein the pair of shield structures separate the first pair of conductive pads from the second pair of conductive pads. In some embodiments, the integrated circuit further includes: a first pair of conductive contacts extending away from the bond interface respectively from the first pair of conductive pads; and a second pair of conductive contacts extending away from the bond interface respectively from the second pair of conductive pads. In some embodiments, the pair of shield structures repeat circumferentially around the first pair of conductive pads. In some embodiments, the first pair of conductive pads and the second pair of conductive pads are arranged in a row, wherein the pair of shield structures have a rectangular top geometry with a greatest dimension extending transverse to the row. In some embodiments, a top geometry of the pair of shield structures has a lesser area than a top geometry of the first pair of conductive pads. In some embodiments, a top geometry of the pair of shield structures is a same as a top geometry of the first pair of conductive pads. In some embodiments, the pair of shield structures has a grid-shaped top geometry.
In some embodiments of the present disclosure, the present disclosure relates to another integrated circuit, including: a first IC chip including a plurality of photodiode blocks in a plurality of rows and a plurality of columns, and further including a plurality of first conductive pads, wherein the plurality of first conductive pads include a conductive pad per photodiode block; a second IC chip bonded to the first IC chip at a bond interface and including a plurality of second conductive pads, wherein the plurality of second conductive pads respectively and directly contact the plurality of first conductive pads at the bond interface; and a plurality of pairs of shield structures at the bond interface and separating the plurality of first conductive pads from each other along the rows and along the columns. In some embodiments, the plurality of pairs of shield structures further separate the plurality of first conductive pads from each other diagonally in a direction transverse to the plurality of columns and the plurality of rows. In some embodiments, the plurality of pairs of shield structures individually have a first top geometry along the rows and the columns and a second, different top geometry diagonally in the direction. In some embodiments, the plurality of pairs of shield structures alternate one to one with the first conductive pads along the rows and the columns, wherein the plurality of pairs of shield structures alternate many to one with the first conductive pads diagonally in the direction. In some embodiments, the plurality of first conductive pads include only one conductive pad per photodiode block, wherein each of the plurality of photodiode blocks includes a multi-dimensional subarray of photodiodes. In some embodiments, the plurality of pairs of shield structures are conductive. In some embodiments, the first IC chip and the second IC chip respectively include a first dielectric layer and a second dielectric layer directly contacting at the bond interface, wherein the plurality of pairs of shield structures include a low k dielectric material having a lower dielectric constant than the first and second dielectric layers.
In some embodiments of the present disclosure, the present disclosure relates to a method including: forming a first IC chip, wherein the forming of the first IC chip includes forming a plurality of first transistors on a first substrate and depositing a first dielectric layer covering the plurality of first transistors; forming a pair of first conductive pads and a first shield structure recessed into the first dielectric layer, wherein the first shield structure separates the first conductive pads; forming a second IC chip, wherein the forming of the second IC chip includes forming a plurality of second transistors on a second substrate and depositing a second dielectric layer covering the plurality of second transistors; forming a pair of second conductive pads and a second shield structure recessed into the second dielectric layer; and bonding the first IC chip to the second IC chip, wherein the first conductive pads respectively and directly contact the second conductive pads at a bond interface and the first and second shield structures directly contact at the bond interface. In some embodiments, the bonding electrically couples the first transistors respectively to the second transistors through the pairs of first and second conductive pads. In some embodiments, the forming of the first IC chip includes forming a plurality of photodiodes in the first substrate, respectively adjacent to the first transistors, wherein the plurality of photodiodes are grouped into multi-dimensional blocks in a plurality of rows and columns, and wherein the pair of first conductive pads respectively and directly underlie corresponding ones of the multi-dimensional blocks. In some embodiments, the forming of the pair of first conductive pads and the first shield structure includes: patterning the first dielectric layer to form pad openings and a shield opening; depositing a conductive layer filling the pad openings and a shield opening; and performing a planarization into the conductive layer. In some embodiments, the forming of the pair of first conductive pads and the first shield structure includes: patterning the first dielectric layer to form pad openings; depositing a conductive layer filling the pad openings; performing a first planarization into the conductive layer; patterning the first dielectric layer to form a shield opening; depositing a low k dielectric layer filling the shield opening; and performing a second planarization into the low k dielectric layer. In some embodiments, the method further includes: forming a plurality of shield structures, including the first shield structure, evenly spaced in a first closed path around a first one of the pair of first conductive pads and evenly spaced in a second closed path around a second one of the pair of first conductive pads, wherein the first and second closed paths are only partially overlapping.
It will be appreciated that in this written description, as well as in the claims below, the terms “first”, “second”, “second”, “third” etc. are merely generic identifiers used for ease of description to distinguish between different elements of a figure or a series of figures. In and of themselves, these terms do not imply any temporal ordering or structural proximity for these elements, and are not intended to be descriptive of corresponding elements in different illustrated embodiments and/or un-illustrated embodiments. For example, “a first dielectric layer” described in connection with a first figure may not necessarily correspond to a “first dielectric layer” described in connection with another figure, and may not necessarily correspond to a “first dielectric layer” in an un-illustrated embodiment.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
