Patent Application
20050138458
Certain types of data transfer techniques employ a source-synchronous clocking protocol to transfer data from a data source to a destination for such data. A common example is a data transfer between a memory controller and associated memory, such as for performing a read or write operation.
In a typical source synchronous clocking protocol, a strobe signal is associated with data to facilitate data transfer. The strobe signal may be delayed relative to the data signal to mitigate errors associated with reading and/or writing data. The delay is typically implemented using a trace delay along the signal path or by employing an on-chip delay element. Variations in the delay between the strobe signal and the data signal may result in timing uncertainty as well as reduced performance.
One embodiment of the present invention may comprise a system that includes a data path that provides a data signal at a first frequency corresponding to a first clock signal. A strobe generator generates a strobe signal at the first frequency, the strobe signal being synchronized with the data signal based on a second clock signal having a second frequency that is different from the first frequency.
A another embodiment of the present invention may comprise a system includes a synchronization component that provides a synchronization signal by propagating a first clock signal to define the synchronization signal based on a second clock signal. The second clock signal has a different frequency from a frequency of the first clock signal. A data path provides a data signal at the frequency of the first clock signal. A strobe generator generates a strobe signal synchronized with the data signal based on the synchronization signal and the second clock signal.
Yet another embodiment of the present invention may comprise a method that includes providing a first signal based on input data, the first signal having a desired frequency corresponding to a first clock signal. The method also can include providing a second signal that is synchronized with the first signal by employing a second clock signal having a frequency that is a multiple of the desired frequency.
This disclosure relates generally to synchronizing a strobe signal with a data signal, such as for use in source synchronous timing. First and second clock signals are employed to propagate data through a data path and to generate a corresponding strobe signal. The first and second clock signals are at different frequencies that facilitate implementing a desired phase shift between the strobe and the data signals. This approach helps to ensure proper synchronization between the first and second signals by mitigating uncertainty associated with signal paths. As a result, PVT (process, voltage, temperature) variations, crosstalk, clock jitter can be reduced relative to many existing approaches. Additionally, the approach described herein enables a design to be implemented with reduced hardware resources, which can further improve timing certainty in signal timing.
The system 10 includes a data path 12 for propagating the input data (DATA IN) to a desired destination. The data path 12 can comprise one or more components, such as logic elements or other circuitry, configured to propagate the input data (DATA IN) as a corresponding output DATA signal. The data path 12 provides the DATA signal at a desired frequency based on a clock (CK) signal. The CK signal, for example, can be a core clock signal associated with an integrated circuit (IC) chip implementing the system 10.
The input data (DATA IN) can be provided by any data source (not shown) as one or more (M) bits of data, where M is a positive integer (M 1). Examples of possible input data sources include a central processing unit (CPU) or other processor coupled to the system 10 via a system bus (not shown). Input data (DATA IN) from a processor can be propagated through the data path 12 for writing the DATA to associated memory. Alternatively, the system 10 can be employed to read (or fetch) the DATA from one or more memory modules, such as in response to an appropriate instruction to read such data. For purposes of simplicity of explanation, this disclosure generally describes implementing write operations, although the approach is applicable to any source synchronous timing strategy. It is to be appreciated that the direction of the DATA through the data path 12 will generally depend on whether the system 10 is being implemented to read or write the DATA to a memory (not shown).
A synchronization block 14 also receives the CK signal and another clock signal, indicated at X*CK, where X denotes a frequency multiplier (e.g., X>1) identifying the relationship between frequencies of the clock signals. The clock signals CK and X*CK can be provided as having proportional frequencies (e.g., integer multiples of each other) with little or no clock skew. The synchronization block 14 provides a synchronization (SYNC) signal based on the pair of clock signals CK and X*CK. The synchronization block 14 provides the SYNC signal to the data path 12. The synchronization block 14 can provide the SYNC signal at the frequency of the CK signal and phase shifted (or delayed) a desired amount relative to the CK signal. For example, the SYNC signal may be phase shifted a desired amount by propagating the SYNC signal based on the X*CK signal. The particular amount of phase shift between SYNC and CK can vary according to the relative frequencies of the CK and X*CK signals as well as the particular logic utilized to implement the synchronization block 14.
The system 10 also includes a strobe generator 16 that provides the STROBE signal based on the SYNC and X*CK signals. The strobe generator 16 can provide the STROBE signal at substantially the same frequency as the DATA signal. Additionally, the X*CK signal enables the strobe generator 16 to implement the STROBE signal with a desired amount of phase shift relative to the DATA signal provided by the data path 12. The amount of phase shift can vary based on the relative frequencies between the CK and X*CK signals, their duty cycles, and the configuration of the system 10. For example, by selecting the frequency and duty cycle of the X*CK signal appropriately, different edges of the X*CK signal can be employed to implement a stable and fixed amount of phase delay between the DATA and STROBE signals. For example, the synchronization block 14 can employ a rising or falling edge of the X*CK signal to provide the SYNC signal, and the strobe generator 16 can employ a different respective clock edge of the X*CK signal to propagate the SYNC signal for driving the STROBE signal synchronously with the DATA signal.
By way of example, the system 10 can be utilized for writing a multi-bit (e.g., two bit) input signal (DATA IN) to associated memory (not shown). The memory can include one or more dynamic random access memory (DRAM) modules (e.g., double data rate (DDR) synchronous DRAM). The JEDEC Solid State Technology Association (once known as the Joint Electron Device Engineering Council) is the semiconductor engineering standardization body of the Electronic Industries Alliance that provides various standards for implementing different types of memory architectures, including the DDR and DDR II specifications. It is to be understood that the system 10 can be utilized for transmitting data synchronously with a strobe signal to satisfy any of the JEDEC specifications (e.g., JESD79-2 for DDR II) as well as other specifications. For the DDR II specification, the X*CK signal may be provided at twice the frequency of CK (i.e., X=2). This enables a desired quarter cycle phase shift between the STROBE signal and the DATA signal. It is to be appreciated that other amounts of phase shift (e.g., other fractional parts of a cycle or period) between the STROBE and DATA signals can be implemented.
Additionally, the CK and X*CK signals can be provided by a clock generator based on a reference clock signal. By employing a single clock generator (e.g., a PLL or delay locked loop (DLLs)) to provide both the CK and X*CK signals, clock skew can be mitigated. By mitigating clock skew between the respective clock signals (CK and X*CK), the system 10 can provide a desired timing relationship between the DATA and STROBE signals that exhibits improved timing certainty.
The clock generation system 52 provides the CK signal to a synchronization component 58 that is operative to provide a selection signal SEL based on the CK and Y*CK signals. The synchronization component 58, for example, can be implemented as a register, latch or flip flop that is operative to propagate the CK signal based on the Y*CK signal. By providing the SEL signal based on the Y*CK signal, which has a greater frequency than the CK input signal, the SEL signal can be shifted a desired amount relative to the CK signal. The synchronization component 58 provides the SEL signal to a data path 60 as well as to a strobe generator 62. The CK signal also is provided to the data path 60 to facilitate propagating input data to a desired destination.
In this example, the data path 60 includes data path logic 64 that receives the input data as one or more inputs, which can be fed to one or more corresponding inputs of the data path. Any available data source can provide the input data to the data path 60, such as at one or more corresponding inputs, via a system bus. The data path logic 64 is configured to provide N inputs to the data selector, where N is an integer corresponding to the number of bits of input data provided by the data source (N 1). The data path logic 64 provides a corresponding output comprising the input data to a data selector 66, such as arranged in a parallel format by the data path logic. The data selector 66 is operative to propagate the N bits of data as output DATA based on the SEL signal provided by the synchronization component 58. For example, the data selector 66 is operative to propagate each of the N inputs based on the SEL signal into a serial data stream comprising the DATA.
The strobe generator 62 is operative to provide the STROBE signal based on the SEL signal and the Y*CK signal. The strobe generator 62 thus includes circuitry (e.g., arrangement of logic and driver circuitry) that employs the SEL signal to provide the STROBE signal at the same frequency as the SEL signal, but shifted a desired amount based on the Y*CK signal. The amount of shifting can be the same or different from that imposed on the CK signal by the synchronization component 58, which is also based on the Y*CK signal.
Because the synchronization component 58 and strobe generator can both be clocked based on the Y*CK signal, which is at a greater frequency that the CK signal, the STROBE signal can be provided at the same frequency as the DATA signal, but phase shifted by a desired amount. The amount of phase shift can vary according to the frequencies of the clock signals CK and Y*CK provided by the clock generation system 52, and based on the particular type of logic implemented as the synchronization component 58 and strobe generator. For example, by implementing Y=2 (e.g., Y*CK is at twice the frequency of CK), a corresponding quarter cycle shift between the DATA and STROBE signals can be realized. Timing margins in the signals can be improved further by implementing the strobe generator 62 to include additional circuitry (e.g., a data selector) corresponding to the data selector 66.
The synchronization system 102 includes a data path portion 106 and a strobe generation portion 108. The data path portion 106 includes a pair of registers 110 and 112 that receive corresponding input signals INPUT1 and INPUT2 signals. For example, the INPUT1 and INPUT2 signals can be provided as two-bit data from an associated source, which has been de-multiplexed into separate data paths. A data source can include a CPU or other computing device that provides input data via a corresponding system bus.
A clock signal CK having a desired frequency is provided at an internal node 114 of the system 102. The CK signal, for example, corresponds to a core clock signal having a desired frequency (e.g., 200-300 MHz) for propagating data through the chip 100. The particular frequency can vary according to the implementation and specification requirements. The CK signal is provided to the registers 110 and 112 for clocking the data contained in the INPUT1 and INPUT2 signals respectively through the registers.
The register 112 provides an output signal (e.g., one or more bits), indicated at D1, to an input of a multiplexer 116 according to the CK signal. The register 110 provides an output signal (e.g., one or more bits) D2 to another register 118 corresponding to the INPUT2 signal. The register 118 propagates the D2 signal to another input of the multiplexer 110 as data D2A. In the example of
The CK signal also is provided to an input of another register 120. The register 120 provides a multiplexer selection signal (S1) to the multiplexer 116 based on another clock signal indicated at Z*CK, where Z denotes a frequency multiplier corresponding to the relationship between frequencies of the CK and Z*CK clock signals (e.g., Z>1). The Z*CK signal is provided at an internal node 122 of the chip 100. Z can be fixed or programmable, for example. The clock signal Z*CK is provided at a desired frequency that is a proportional multiple of the CK signal corresponding to the multiplier Z (e.g., 400-600 MHz). Since the register 120 provides the S1 signal based on the negative edge of the Z*CK signal, the S1 signal can be provided with a desired amount of phase shift relative to the CK signal. The register 120 thus operates as synchronization logic that propagates the CK signal as the S1 signal to each of the data path portion 106 and the strobe generation portion 108.
By way of example, the respective clock signals CK and Z*CK can be provided by clock generation circuitry (e.g., PLL or DLL circuitry), which may be located internal or external relative to the chip 100. Alternatively separate clock generation circuitry can be utilized to generate the respective signals. However, it will be appreciated that by generating the CK and Z*CK signals from a single clock generator, reduced clock skew and improved timing margins can be achieved in the system 102.
The multiplexer 116 selectively provides an output signal to a buffer/driver 124 based on the S1 signal. The output signal corresponds to D1 or D2A depending on the S1 signal. The buffer/driver 124, in turn, provides the DATA signal to the memory 104. The DATA signal thus corresponds to a serial stream comprising the data D1 and D2A based on the operation of the multiplexer 116 according to the S1 signal.
The S1 signal and the Z*CK clock signal also are provided to the strobe generation portion 108. In the example of
The operation of the synchronization system 102 will be better appreciated with reference to
Referring between
As mentioned above, the S1 signal cascades to the strobe path logic so that the resulting STROBE signal has a desired phase relationship and frequency (e.g., it is synchronized) relative to the DATA signal provided by the data path portion 106. The register 122 propagates the S1 signal based on the positive or rising edge of the Z*CK signal (indicated at time T0) to provide the S2 signal. Since the multiplexer select signal S2 for the multiplexer 126 is clocked off the rising edge of the Z*CK signal, the multiplexer 126 provide a corresponding output signal to the buffer/driver 126, which signal is synchronized with the signal provided by the data path multiplexer 116. Additionally, the multiplexer 126 in the strobe path and the multiplexer 116 in the data path portion 106 the strobe path can be substantially equalized (e.g., matched circuitry) to improve the timing margin.
It is to be further appreciated that in the approach depicted in
In view of the foregoing structural and functional features described above, certain methodologies that can be implemented will be better appreciated with reference to
It is to be further understood that the following methodology can be implemented in hardware, such as one or more integrated circuits, software, or any combination thereof. For example, in one embodiment, a method can be implemented as logical actions performed by circuit components (digital and/or logical components) arranged to implement a desired method.
At 310, input data is received. The input data can be received from any source (e.g., a CPU) that aspires to transmit data to a corresponding destination. The input data can be provided as single or multi-bit data, depending generally on the implementation. A selection signal (S1) is generated at 320. The selection signal (S1) can be generated by propagating the first clock signal through a circuit component based on the faster second clock signal (CK2). For the example where the second clock signal (CK2) is at twice the frequency as the first clock signal (CK1), the selection signal (S1) can be provided at the same frequency and with a quarter cycle shift relative to the first clock signal (CK1). This result can be achieved, for example, by using a negative edge of the second clock signal (CK2) to propagate the first clock signal (CK1).
At 330, the selection signal (S1) can be employed to provide the input data as output data having a desired frequency and phase characteristics. For example, the selection signal (S1) can be provided as a control input to a multiplexer or other selection device capable of selectively providing the output data signal (at 330) based on the selection signal (S1).
At 340, the selection signal is shifted a desired amount to provide another selections signal (S2). The second selection signal (S2) can be generated, for example, by propagating the first selection signal (S1) through circuitry based on an edge of the second clock signal (CK2) that is different from the edge employed to provide the first selection signal (S1) at 320. Continuing with the above example where the second clock signal (CK2) is at twice the frequency as the first clock signal (CK1), the second selection signal (S2) can be provided at the same frequency and with a quarter cycle shift relative to the first selection signal (S1). This relationship can be achieved by propagating the first selection signal through such circuitry using a positive edge of the second clock signal (CK2), where a negative edge of CK2 is used to provide the first selection signal (S1).
At 350, the strobe signal can be provided based on the second selection signal (S2). From 350, the method can return to 300 and repeat for the next cycle for synchronously providing data and strobe signals. It is to be appreciated that the strobe signal has desired frequency and deterministic phase characteristics relative to the data signal. The method enables the strobe to be provided synchronously with the data signal so as to mitigate duty cycle jitter and distortion. As a result, the overall timing margin can be significantly improved.
What have been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims.
