Patent Application
20250118720
The subject matter disclosed herein relates to microelectronics packaging and integrated circuits (IC) packaging. More particularly, the subject matter disclosed herein relates to a package architecture featuring bridges.
Semiconductor devices may connect to additional devices and circuitry on different substrates. Forming connections between substrates can provide increased computation. However, forming connections between substrates can cause complications. Packaging describes the general method for connecting and integrating multiple computational components together in an integrated unit, and may involve multiple different types of integrated circuits on multiple substrates which may combine into a single unit. Packaging may also describe the method for which multiple computational components within a single unit are protected by the use of various techniques to provide thermal, physical and electrical protection. Background concepts discussed herein are for informational purposes only and are not intended to limit the present disclosure. Nor should the background or field described herein be intended to limit the disclosure herein to a particular use or concept.
An example embodiment provides a device including a first layer, the first layer including a first compute device, a first multi-device package, and a second multi-device package. The first compute device may be between the first multi-device package and the second multi-device package. A second layer may include a first redistribution layer on a first side of the second layer facing the first layer, the first redistribution layer electrically connecting the first compute device to the first multi-device package and the first redistribution layer electrically connecting the first compute device to the second multi-device package. The first layer may include a third multi-device package and a fourth multi-device package, with the first compute device between the third multi-device package and the fourth multi-device package. The first redistribution layer may electrically connect the first compute device to the third multi-device package and the first redistribution layer may electrically connect the first compute device to the fourth multi-device package. The first compute device may be between the second multi-device package and fourth multi-device package. The first layer may include a second compute device, a fifth multi-device package, and a sixth multi-device package, with the second compute device between the sixth multi-device package and the fifth multi-device package. The first redistribution layer may electrically connect the second compute device and the sixth multi-device package and the first redistribution layer may electrically connect the second compute device and the fifth multi-device package. The second layer may include a second redistribution layer on a second side of the second layer, the second side opposite the first side. A first bridge may be arranged between the first redistribution layer and the second redistribution layer. The first multi-device package may include at least a first device stack and a second device stack on a first multi-device die. The first device stack may include one or more of a memory device and a processing device. The first multi-device die may electrically connect the first device stack and the second device stack to the first redistribution layer.
An example embodiment provides a system, the system including a first layer with a first compute device, a first multi-device package, and a second multi-device package. The first compute device may between the first multi-device package and the second multi-device package. A second layer may include a first bridge and a second bridge, the first bridge electrically coupling the first compute device to the first multi-device package and the second bridge electrically coupling the first compute device to the second multi-device package. The first layer may include a second compute device, a third multi-device package and a fourth multi-device package. The second layer may include a third bridge and a fourth bridge, with the third bridge electrically connecting the second compute device to the third multi-device package and the fourth bridge electrically connecting the second compute device to the fourth multi-device package. The second layer may include a first redistribution layer on a first side of the second layer, the first redistribution layer between the first bridge and the first multi-device package. The second layer may include a second redistribution layer, the second redistribution layer on a second side of the second layer, opposite the first side, the first bridge between the first redistribution layer and the second redistribution layer. The first multi-device package may include at least one memory device or processing device. The first layer may include a base die, the base die between the first compute device and the first bridge.
An example embodiment provides a method including forming an interposer with a first bridge and a second bridge; forming a first redistribution layer on a first side of the interposer, the first redistribution layer communicatively coupled to the first bridge and the second bridge; mounting a compute device on the interposer and on the first redistribution layer; mounting a first multi-device package and a second multi-device package on the interposer and on the first redistribution layer, the compute device arranged between the first multi-device package and the second multi-device package; depositing a dielectric layer over the interposer, coupling the first multi-device package to the compute device via the first bridge; and coupling the second multi-device package to the compute device via the second bridge. The first multi-device package and the second multi-device package may have substantially the same devices. Mounting the compute device on the interposer may include mounting a base die on the first redistribution layer and mounting the compute device on the base die. Forming the interposer may include forming a second redistribution layer on a second side of the interposer, the second side opposite the first side. Depositing the dielectric layer over the interposer may include deposition dielectric material between the first multi-device package, the second multi-device package, and the compute device.
In the following section, the aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments illustrated in the figures, in which:
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. It will be understood, however, by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail to not obscure the subject matter disclosed herein.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment disclosed herein. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” or “according to one embodiment” (or other phrases having similar import) in various places throughout this specification may not necessarily all be referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not to be construed as necessarily preferred or advantageous over other embodiments. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. Similarly, a hyphenated term (e.g., “two-dimensional,” “pre-determined,” etc.) may be occasionally interchangeably used with a corresponding non-hyphenated version (e.g., “two dimensional,” “predetermined, etc.), and a capitalized entry (e.g., “Counter Clockwise,” “Three-Dimensional,” etc.) may be interchangeably used with a corresponding non-capitalized version (e.g., “counter clockwise,” “three-dimensional,” etc.). Such occasional interchangeable uses shall not be considered inconsistent with each other.
Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. It is further noted that various figures (including component diagrams) shown and discussed herein are for illustrative purpose only, and are not drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.
The terminology used herein is for the purpose of describing some example embodiments only and is not intended to be limiting of the claimed subject matter. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element or layer is referred to as being on, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
The terms “first,” “second,” etc., as used herein, are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. Such usage is, however, for simplicity of illustration and ease of discussion only; it does not imply that the construction or architectural details of such components or units are the same across all embodiments or such commonly-referenced parts/modules are the only way to implement some of the example embodiments disclosed herein.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein substrates may refer to a variety of materials and structures, including wafers using silicon, wafers using silicon on an insulator (SOI) such as glass, wafers of other semiconductor materials such as germanium, as well as other semiconductor materials on an insulator. In some embodiments, a substrate may include an organic material. In some embodiments, the substrates may be referred to as wafers, dies, and chips alone or in combination. Bonding substrates may be thus known in some embodiments as die-to-die (D2D) bonding, wafer-to-wafer bonding (W2W) or die-to-wafer bonding (D2W). In some embodiments, the substrates may contain circuits such as integrated circuits including central processing units (CPUs), logic chips, memory such as static random-access memory (SRAM), dynamic random-access memory (DRAM), synchronous dynamic random-access memory (SDRAM), double data rate DRAM or DDR DRAM, application processors (AP), graphical processing units (GPUs), other forms of auxiliary processing units (xPU), Artificial intelligence (AI) chips, High bandwidth memory (HBM) interfaces, and other application-specific integrated circuits (ASIC). In some embodiments, a combination of circuits may be present on a substrate. In some embodiments, a substrate may include a packaged chip.
As used herein, high bandwidth memory or HBM, may refer to a chip structure including one or more HBM modules. In some embodiments, the HBM may be manufactured by an advance silicon node process.
As used herein packaging refers to a process of forming interconnections between substrates. In some embodiments, the interconnections may be between direct surfaces and involve W2W, D2D, and D2W bonding. In other embodiments, techniques including wire bonding and other forms of indirect bonding may be performed alone or in combination with W2W, D2D, and D2W bonding. In some embodiments, circuits may be bonded directly facing each other, while in other embodiments a flip-chip bonding may be used. In some embodiments, interconnections may be made between substrates on a front or circuit side of the substrate. In other embodiments, interconnections may be made on a rear or back side of the substrate opposite from the circuit structure. In some embodiments, an interconnection may include through-silicon vias (TSVs) or other forms of through-chip vias where one or more substrates may be connected using a via traveling through an interposer such as another substrate or chip. In some embodiments, an interconnection may be formed using connections on a surface of a substrate, such as a pad, and may use additional materials between the pads such as solder to form an interconnection.
As used herein, conductors may refer to a variety of conductive materials, including which materials may be used alone or in combination with other materials such as in the form of an alloy. In some embodiments the conductor is copper (Cu). In some embodiments, copper (Cu) may be in the form of Cu (II), Cu (III) or other forms of copper, alone or in combination with additional elements, including cobalt (Co) and Ruthenium (Ru). Such a listing of elements is not intended to be exhaustive, and in other embodiments, any known other type of conductive material may be used.
As used herein, a device stack or stack of devices may refer to a combination of memory and supporting circuit architecture, for example, chiplets and dies containing individual memory elements, supporting processing units, input output (I/O) circuitry, and other forms of integrated chips. As used herein, hybrid bonding may be defined as bonding both conductive portions to conductive portions such as a metal-metal bond, and bonding dielectric portions to dielectric portions such as a dielectric-dielectric bond.
As used herein, a bridge refers to a substrate, die, or other material having one or more conductive pathways able to form connection between one or more semiconductor devices, as well as substrates, interposers, or other package structures. A bridge may include one or more traces, the traces forming a connection pathway along the bridge between one or more devices coupled to the bridge. An embedded bridge, as used herein, may refer to a bridge in a layer within a semiconductor package, and may be used interchangeably with bridge.
Disclosed herein are various embodiments of devices, systems and methods related to packaging architecture to modularly create a stack logic and memory building block architecture. Increasing the number of devices and number of device stacks may utilize additional methods of connecting compute devices to device stacks to allow denser computation. A stack logic and memory building block architecture may include a base chip providing logic, routing, and power delivery to one or more device stacks. A multiple-stack die may include one or more device stacks on a shared substrate. The multiple-stack die may then be mounted on a shared interposer with a compute device and additional multiple-stack dies. Signals between the compute devices and the device stacks may be routed via the shared interposer, including via one or more bridges which may be embedded in the shared interposer between two or more redistribution layers. As used herein, a device stack or stack of devices may refer to a combination of memory and supporting circuit architecture, for example, chiplets and dies containing individual memory elements, supporting processing units, I/O circuitry, and other forms of integrated chips.
In some embodiments, a back-side power delivery network (BSPDN) may be formed on the backside of a substrate, with a signal network formed on the front side of the same substrate. In some embodiments, the BSPDN and signal network may be formed on separate substrates and transferred to the same substrate. The BSPDN and signal network may be separated by a transistor layer. The transistor layer may include a plurality of transistors. The transistors may provide different functions and take different forms, including a logic layer. The BSPDN and signal network may form a single monolithic structure on the same die in a semiconductor foundry process. A stacked device module may separately be formed in a semiconductor foundry process, the same semiconductor foundry process, or may have multiple components formed in multiple semiconductor foundry processes and assembled in a packaging assembly process.
The one or more multi-device packages 112 may include a multi-device die 120 upon which are mounted multiple devices in the form of chips or dies. In the embodiment of
The number of devices within each stack of devices may vary, and the number of devices and type of devices provided may vary based on the relative amount of computing desired for each device. For example, a desired ratio between core dies and memory dies may be desired, for example 1 core per 4 memory dies may be desired in some embodiments. However, in other embodiments, the ratio may vary, for example, and in some embodiments the ratio may be greater and include 1 core per 5, 6, 10, or even 16 memory die.
Additionally, as seen in the exemplary view of
In some embodiments, one or more central encapsulation layers 136 may surround the compute devices including the first compute device 108 and the second compute device 109. In the example embodiment of
On the one or more multi-device packages 112, the first device 122 and the second device 124 may be electrically coupled to one or more wiring layers 121 within the multi-device die 120. The one or more wiring layers 121 within the multi-device die 120 may in turn couple the first device 122 and the second device 124 to the interposer 104. The interposer 104 may include one or more redistribution layers 105 allowing the first device 122 and the second device 124 to electrically couple to the first compute device 108 and/or the second compute device 109 via the base die 106. The base die 106 may further include a base redistribution layer 107 allowing the first compute device 108 and the second compute device 109 to communicate with the supporting substrate 102.
While in the exemplary embodiments of
Although referred to as wiring layers, the one or more wiring layers 121 may take the form of series of pads, bumps, vias, through-vias, traces, redistribution layers and other forms of connection for redistributing signals in various combinations. Similarly, the one or more redistribution layers 105 and the base redistribution layer 107 may also take the form of series of pads, bumps, vias, through-vias, traces, redistribution layers and other forms of connection for redistributing signals in various combinations.
In some embodiments, the supporting substrate 102 may be an organic substrate such as a polymer, while in other embodiments an inorganic substrate such as a semiconductor including silicon may be used, or alternatively a SOI substrate such as glass. In some embodiments, the interposer 104 may be made of silicon, while in other embodiments another form of semiconductor such as germanium may be used. In some embodiments, multiple interposer substrates may be shared on a single supporting substrate. In some embodiments, the supporting substrate 102 may be multiple substrates, and in some embodiments may be multiple substrates stacked upon each other. The supporting substrate 102 may have the interposer 104 mounted thereon in a variety of ways and may include pads, bumps, microbumps, pillars, balls, and other forms such as controlled-collapse chip connection (C4) bumps, alone or in combination. As used herein, a C4 bump refers to a form of solder bumps placed on pads on a top surface of a substrate prior to flipping the substrate to form a flip-chip. The mounting method may further include a dielectric material, which may include a material such as an adhesive, resin, or elastomer which may form a connection in addition to a conductive connection. In some embodiments, the combination of a conductive connection and a dielectric connection may form a hybrid bond.
The interposer 104 may contain additional devices in addition to or in alternative to the compute devices and the multi-device packages. In the exemplary embodiment of
Additionally, as shown in the exemplary embodiment of
Also shown in
The one or more embedded bridges 602 may include a first embedded bridge 620 to connect the base die 106 to the first multi-device package 113, a second embedded bridge 621 to connect the base die 106 to the second multi-device package 114, a third embedded bridge 622 to connect the base die 106 to the third multi-device package 115, a fourth embedded bridge 623 to connect the base die 106 to the fourth multi-device package 116, a fifth embedded bridge 624 to connect the base die 106 to the fifth multi-device package 117, and a sixth embedded bridge 625 to connect the base die 106 to the sixth multi-device package 118.
In addition, the bridge interposer 604 includes a first redistribution layer (RDL) 612 on the bottom side of the bridge interposer 604 and a second RDL 614 on the top side of the bridge interposer 604. Furthermore, conductive pillars 606 may electrically connect the first RDL 612 to the second RDL 614. The bridge interposer 604 may include a molding layer 608 between the first RDL 612 and the second RDL 614. In some embodiments, the molding layer 608 may be a dielectric material providing thermal insulation, mechanical separation, and electrical insulation between the first RDL 612, the second RDL 614 and conductive pillars 606. The first RDL 612 may provide a series of pads, bumps, vias, through-vias, traces, and other forms of connection for redistributing signals from the supporting substrate 102 to the bridge interposer 604. The second RDL 614 in turn may provide a series of pads, bumps, vias, through-vias, traces, and other forms of connection for redistributing signals from the bridge interposer 604 to the compute devices of the base die 106, and the one or more multi-device packages 112. The first RDL 612 and the second RDL 614 with the conductive pillars 606 thus may provide a connection between the supporting substrate 102, the compute devices of the base die 106, and the one or more multi-device packages 112.
Also depicted in the exemplary embodiment of
After the packaged devices 825 are mounted to the bridge interposer 604, and one or more overmolding layers 152 may be deposited over the first packaged device 804, the second packaged device 806 and the third packaged device 808. The overmolding layers 152 may be deposited to encapsulate the first packaged device 804, the second packaged device 806 and the third packaged device 808 to the bridge interposer 604, as well as to provide mechanical support, thermal insulation, and electrical separation. In some embodiments, the overmolding layers 152 may be one or more layers of a dielectric material, and may be an over molding process. In some embodiments, any excess material deposited on to the devices may be subject to a process to smooth and or planarize the surface of the devices, the process including one or more grinding, polishing, and smoothing processes, including CMP. In some embodiments, a thermal processing step or heat treatment step may be used to secure the overmolding layers 152 in place.
Additionally, at S960, interconnections may be prepared for mounting the bridge interposer 604 on to the supporting substrate 102. The interconnections may include pads, bumps, microbumps, pillars, balls, and other forms such as C4 bumps, alone or in combination. In some embodiments, a dielectric layer or adhesive layer, including underfill may also be included.
Additionally, the stiffener 130 may be formed upon the supporting substrate 102 to surround the bridge interposer 604. The stiffener 130 may be formed directly upon the supporting substrate 102, such as by additive manufacturing of a suitable material to provide additional stiffness to the supporting substrate 102, or may be formed separately and mounted on the supporting substrate 102 using either a bonding process, or an adhesive such as an epoxy or resin. In some embodiments, an additional layer of molding material or encapsulation materials may be deposited between the bridge interposer 604 and the stiffener 130. In some embodiments, a lid may be further mounted on to the device package architecture 100 and be attached to the stiffener 130.
While this specification may contain many specific implementation details, the implementation details should not be construed as limitations on the scope of any claimed subject matter, but rather be construed as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.
Thus, particular embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, the actions set forth in the claims may be performed in a different order and still achieve desirable results. Additionally, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.
As will be recognized by those skilled in the art, the innovative concepts described herein may be modified and varied over a wide range of applications. Accordingly, the scope of claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but is instead defined by the following claims.
This application claims the priority benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application Ser. No. 63/543,504 filed on Oct. 10, 2023 and U.S. Provisional Patent Application Ser. No. 63/543,505 filed on Oct. 10, 2023, the disclosures of which are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63543504 | Oct 2023 | US | |
| 63543505 | Oct 2023 | US |
