This application claims the priority benefit of French patent application number 11/59445, filed on Oct. 19, 2011, which is hereby incorporated by reference to the maximum extent allowable by law.
1. Technical Field
The present disclosure relates to the protection of an integrated circuit chip against laser attacks.
2. Discussion of the Related Art
Some integrated circuit chips may be the target of external attacks aiming at disturbing the normal operation of the integrated circuit or at obtaining protected confidential data. To intentionally cause disturbances in the circuits of a chip, an attack mode comprises bombarding chip areas with a laser beam while the chip is operating. Due to the presence of interconnection metal tracks on the front surface side of the chip, laser attacks are often carried out on the back side.
To avoid fraud, chips comprising attack detection devices have been provided. The attack detection device is coupled to a chip protection circuit. When an attack is detected, the protection circuit implements measures of protection, modification, or destruction of the critical data. For example, it may be provided, when an attack is detected, to interrupt the power supply of the chip or to cause its resetting, in order to reduce the time during which the attacker can study the chip response to a disturbance.
European patent EP2109139 describes an embodiment of an integrated circuit chip associated with a device for detecting a laser attack.
A heavily-doped P-type contact region 12, extending at the surface of well 2, is intended to be directly connected to ground GND. A heavily-doped N-type contact region 24, extending at the surface of well 4, is intended to be connected to a source of voltage Vdd.
N-channel transistor T2 of well 2 is inverter-assembled with P-channel transistor T1 of well 4, that is, the gate of the N-channel transistor is connected to the gate of the P-channel transistor, forming input terminal IN of an inverter, and the drain of the N-channel transistor is connected to the drain of the P-channel transistor, forming output terminal OUT of the inverter. In operation, the source of the P-channel transistor is at high power supply voltage Vdd. The source of the N-channel transistor is at ground GND.
The chip comprises an N-type buried layer 16 extending in substrate 1 under wells 2, 4. Buried layer 16 is in contact with N-type well 4. An N-type region 18 extends in substrate 1 from the upper surface of the substrate all the way to buried layer 16. Region 18, with N-type well 4, totally surrounds P-type well 2. A heavily N-type doped contact region 19 extends at the surface of region 18. Contacts 24 and 19 are intended to bias N-type wells 4 and buried layer 16 to voltage Vdd. A heavily-doped P-type contact region 21, extending at the surface of substrate 1, is intended to be directly connected to ground GND. Contact 21 for example has the shape of a ring surrounding wells 2 and 4. Voltage Vdd is provided by a power supply source 26 associated with a detection circuit 28.
When a laser beam reaches the rear surface of the chip, buried layer 16 tends to capture electrons originating from electron/hole pairs photogenerated in the substrate. These electrons are attracted by the positive voltage applied on contacts 19 and 24, and cause parasitic signals which are detected by detection circuit 28.
An embodiment of power supply source 26 and of detection circuit 28 is described in detail in above-mentioned European patent EP2109139.
A disadvantage of the system for detecting a laser attack described in relation with
A system for a detecting a laser attack on an integrated circuit chip is thus needed, the detection system being unlikely to be disturbed by the noise induced by the normal operation of the chip components.
An embodiment provides a system for detecting a laser attack on an integrated circuit chip, the detection system being unlikely to be disturbed by the noise induced by the normal operation of the chip components.
An embodiment provides a system for detecting a laser attack on an integrated circuit chip formed in a semiconductor substrate, comprising a detection device capable of detecting voltage variations of the substrate.
According to an embodiment, the upper portion of the substrate is of type P and the chip comprises: first P-type wells and second N-type wells extending in the upper portion of the substrate; an N-type buried layer extending under a portion at least of the first and second wells; first contacts for biasing the second wells and the buried layer; second contacts to ground of the first wells; and third contacts for detecting the substrate voltage, surrounding the first and second wells under which the buried layer extends; and the detection device comprises: a resistor having a terminal connected to the second ground contacts of the first wells and its other terminal connected to the third contacts for detecting the substrate voltage; and a comparator connected in parallel with the resistor, capable of detecting a potential difference across the resistor.
According to an embodiment, the buried layer is in contact with the first wells and the second wells under which it extends.
According to an embodiment, each first well under which the buried layer extends is surrounded with N-type areas extending from the upper surface of the substrate all the way to the buried layer.
According to an embodiment, the N-type areas are some of the second wells under which the buried layer, or first N-type regions extending from the upper surface of the substrate all the way to the buried layer, extend.
According to an embodiment, the third contacts for detecting the substrate voltage discontinuously surround the first wells and the second wells under which the buried layer extends.
According to an embodiment, the upper portion of the substrate is doped with a doping level lower than 5.1016 atoms/cm3.
According to an embodiment, the chip further comprises fourth contacts to ground of the substrate.
According to an embodiment, the chip further comprises second N-type regions extending from the upper surface of the substrate between the third contacts for detecting the substrate voltage and the fourth contacts to ground of the substrate, the second regions surrounding the third contacts for detecting the substrate voltage.
According to an embodiment, the width of the third contacts for detecting the voltage of the substrate is greater than that of the fourth contacts to ground of the substrate.
The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
As usual in the representation of integrated circuits, the various drawings are not to scale.
The elements of
Heavily-doped P-type regions 31 correspond to regions 21 of
To detect a laser attack in an integrated circuit chip of the type illustrated in
In the example illustrated in
When a laser beam reaches the rear surface of the chip, electron/hole pairs are photogenerated in P-type substrate 1. The electrons cross N-type buried layer 16 and are attracted by voltage Vdd applied on contacts 19 and 24. The holes are attracted by contacts 31 for detecting the voltage of substrate 1 connected, via resistor 41, to ground contacts 12 of wells 2. A current I1 then flows from contacts 31 to contacts 12 through resistor 41, and a potential difference appears across resistor 41. As soon as this potential difference exceeds a given threshold, output OUT of the comparator delivers a laser attack detection signal. Output OUT for example switches from a low level to a high level. Various measures of protection, modification, or destruction of the confidential data of the chip may then be implemented.
Comparator 43 should has a sufficiently fast response to detect a current corresponding to an attack with a pulse laser having pulses shorter than 10 ns. A comparator 43 having a bandwidth of at least 100 MHz will for example be selected.
Since substrate 1 is insulated from wells 2 and 4 under which buried layer 16 extends, contacts 31 for detecting the substrate voltage are free of the noise due to the normal operation of the chip components in wells 2 and 4. Further, the noise on ground contacts GND is generally lower than on contacts connected to voltage Vdd. Indeed, in the general design of an integrated circuit, ground contacts GND are well distributed across the entire circuit and are interconnected by the largest possible connection rails while, generally, the contacts to voltage Vdd are connected by smaller rails to a regulator delivering voltage Vdd, this regulator being subjected to the circuit switching noise. An additional advantage of such a detection system lies in the use of a particularly simple detection device.
An N-type region 48 extends from the upper surface of substrate 1 and surrounds contact 31 for detecting the voltage of the substrate which surrounds wells 2 and 4 under which buried layer 16 extends. A heavily-doped P-type contact region 52, extending at the surface of substrate 1, is intended to be connected to ground network GND of the circuit. N-type region 48 extends between substrate voltage detection contact 31 and contact 52. Contact 52 for example has the shape of a ring discontinuously surrounding region 48, as shown in
In a laser attack, the holes originating from the electron/hole pairs photogenerated in the substrate, under buried layer(s) 16, are likely to be attracted mainly by substrate voltage detection contacts 31 or by ground contacts 52 of the substrate.
Call Isub the hole current generated in the substrate from the electron/hole pairs. As schematically shown in
To optimize the detection of a laser attack, hole current Isub is desired to be mainly directed towards contacts 31, and not towards contacts 52. To achieve this, the present inventors provide a sum of resistances Repi2 and RP2 of access to contacts 52 much greater than the sum of resistances Repi1 and RP1 of access to contacts 31 and of resistance Rext of the detection device. The upper portion of substrate 1, where wells 2, 4 and buried layer 16 extend, is preferably lightly doped, for example, between 1015 and 1016 atoms/cm3, so that resistance Repi2 is high. Further, a width W1 of contacts 31 greater than width W2 of contacts 52 may be provided, so that resistance RP1 of access to contact 31 is smaller than resistance RP2 of access to contact 52. A good ground network is further provided so that the voltage on the terminal of resistor 41 connected to ground contacts 12 and 52 is as low as possible.
As a practical example, for a resistor 41 having a value Rext on the order of the value of access resistor Repi2, approximately half of current Isub is collected by contacts 31. For a value of Isub on the order of 10 mA and a value Rext on the order of 100 ohms, a potential difference on the order of 500 mV will then be obtained across resistor 41, which difference will be detected by comparator 43. It is however sufficient to have a portion of current Isub reaching substrate voltage detection contacts 31 for the detection device to deliver a laser attack detection signal.
In
Specific embodiments have been described. Various alterations, modifications, and improvements will readily occur to those skilled in the art. In particular, although a detection device comprising a resistor connected in parallel with a comparator has been described, those skilled in the art may of course use any other detection device capable of detecting substrate voltage variations.
Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention.
Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.