Claims
- 1. A method for preventing excess silicon consumption in a semiconductor wafer, comprising the steps of:depositing a metal layer on top of a native oxide layer that resides upon a silicide layer; and reducing the native oxide layer to form low resistance contacts, using a rapid thermal annealing process within a temperature range greater than 350° C. and less than 615° C.
- 2. The method as recited in claim 1, wherein the temperature range is about 485° C. to 550° C.
- 3. The method as recited in claim 1, wherein the temperature range is approximately 485° C.
- 4. The method as recited in claim 1, wherein excess silicon consumption is substantially reduced.
- 5. The method as recited in claim 1, wherein excess silicon consumption is reduced to approximately zero.
- 6. The method as recited in claim 1, wherein the metal layer comprises a metal selected from the group consisting of Ti, Co, W, Ni and Pt.
- 7. The method as recited in claim 1, wherein the metal layer is Ti.
- 8. The method as recited in claim 1, wherein the silicide layer is CoSi2.
- 9. A method for preventing excess silicon consumption in a semiconductor wafer, comprising the steps of:depositing a metal layer on top of a native oxide layer that resides upon a CoSi2layer; and reducing the native oxide layer to form low resistance contacts, using a rapid thermal annealing process at a temperature greater than 350° C. and less than 615° C.
- 10. The method as recited in claim 9, wherein the temperature is about 485° C. to 550° C.
- 11. The method as recited in claim 9, wherein the temperature is approximately 485° C.
- 12. The method as recited in claim 9, wherein excess silicon consumption is substantially reduced.
- 13. The method as recited in claim 9, wherein excess silicon consumption is reduced to approximately zero.
- 14. The method as recited in claim 9, wherein the metal layer comprises a metal selected from the group consisting of Ti, Co, W, Ni and Pt.
- 15. The method as recited in claim 9, wherein the metal layer is Ti.
- 16. A system for preventing excess silicon consumption in a semiconductor wafer, comprising:deposition of a metal layer atop a native oxide layer that resides upon a CoSi2 layer, wherein the metal layer comprises a metal selected from the group consisting of Ti, Co, W, Ni and Pt; and reduction of the native oxide layer to form low resistance contacts using a rapid thermal annealing process at a temperature of about 485° C. to 550° C.
- 17. The system as recited in claim 16, wherein excess silicon consumption is substantially reduced.
- 18. The system as recited in claim 16, wherein excess silicon consumption is reduced to approximately zero.
- 19. The system as recited in claim 16, wherein the metal layer is Ti.
PRIORITY CLAIM
This patent application claims priority of U.S. Provisional Application No. 60/344,665, filed on Dec. 28, 2001.
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Provisional Applications (1)
|
Number |
Date |
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|
60/344665 |
Dec 2001 |
US |