Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipments. Semiconductor devices are fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of different materials over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon. Many integrated circuits are manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are packaged separately, in multi-chip modules, or in other types of packaging, for example.
In the semiconductor processing field, various process chambers can be utilized in association with a wafer handling system or device to perform a variety of semiconductor processes. These processes may include annealing, cleaning, chemical vapor deposition, oxidation, and nitridation. The processes may be applied under vacuum, under gas pressure and with the application of heat.
However, the wafer usually has to be placed in a specific orientation before entering the process chambers, and has to have its temperature reduced after the processes. There are still many challenges related to reducing the entire processing time.
For a more complete understanding of the illustrative embodiments and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings.
The making and using of various embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the various embodiments can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the performance of a first process before a second process in the description that follows may include embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes may be performed between the first and second processes. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Furthermore, the formation of a first feature over or on a second feature in the description may include embodiments in which the first and second features are formed in direct or indirect contact.
Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It is understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
Embodiments of mechanisms for transferring a semiconductor substrate are provided.
A first rail 11 and two holes 12, 13 are formed on the stage 10, as shown in
Referring to
After the movable pillars P move downward, the semiconductor substrate S can be disposed on the first portion 21, the carrier 20 moves back along the first rail 11. Therefore, the semiconductor substrate S can be transferred from the storage chamber C2 to the transfer module 100 in the station C1.
It should be noted that, when the semiconductor substrate S is transferred from the storage chamber C2 to the transfer module 100 in the station C1, the center detector 40 can emit light to detect the center of the semiconductor substrate S. Subsequently, as shown in
Referring to
As shown in
After the process is finished in the first process chamber C3, the semiconductor substrate S has a high temperature in some embodiments. For the purpose of reducing the temperature of the semiconductor substrate S, the transfer module 100 transfers the semiconductor substrate S from the first process chamber C3 to the transfer module 100 in the station C1 by using an operation similar to the operation of transferring it from the storage chamber C2 to the transfer module 100 in the station C1.
As shown in
When the operation of cooling the semiconductor substrate S is finished, the stage 10 rotates and the semiconductor substrate S is transferred from the transfer module 100 to the storage chamber C2 in some embodiments. In some other embodiments, when the operation of cooling the semiconductor substrate S is finished, the stage 10 rotates and the semiconductor substrate S is transferred from the transfer module 100 to the second process chamber C4.
In some embodiments, after the semiconductor substrate S is transferred from the first process chamber C3 to the transfer module 100 in the station C1, the stage 10 rotates and the semiconductor substrate S is transferred from the transfer module 100 to the second process chamber C4. The semiconductor substrate S can be processed in the second process chamber C4. The operation of cooling the semiconductor substrate S is executed after the process is finished in the second process chamber C4. In some embodiments, when the stage 10 rotates from the first process chamber C3 to the target chamber (such as the storage chamber C2 or the second process chamber C4), the cooling members 60 cool the semiconductor substrate S during the transportation.
In some embodiments, the first process chamber C3 or the second process chamber C4 is a CVD (chemical vapor deposition) chamber, PVD (physical vapor deposition) chamber, CMP (chemical mechanical polishing) chamber, photolithography chamber, etching chamber, or other pre-process chamber or post-process chamber.
In some embodiments, as shown in
Referring to
Afterwards, a center and a notch of the semiconductor substrate S can be detected by the transfer module 100 (operation S2). As shown in
The following operation is to transfer the semiconductor substrate S from the transfer module 100 to a first process chamber C3 (operation S3). As shown in
After the operation S4, the semiconductor substrate S is transferred from the first process chamber C3 to the transfer module 100 (operation S5), and the temperature of the semiconductor substrate S is reduced by the transfer module 100 (operation S6). The operation S5 includes raising a movable pillar along a second direction in the first process to hold the semiconductor substrate S in accordance with some embodiments. In some embodiments, the operation S5 also includes moving a carrier 20 of the transfer module 100 along a first direction into the storage chamber C2 and under the semiconductor substrate S. In some embodiments, the operation S5 further includes lowering the movable pillar in the storage chamber C2, and moving back the carrier 20 along the first direction. As shown in
In some embodiments, the method further includes rotating the stage 10 and transferring the semiconductor substrate S from the transfer module 100 to a second process chamber C4 after the operation S5 or S6. In some embodiments, the method further includes detecting the center and notch of the semiconductor substrate S after the operation S5. In some embodiments, the method further includes transferring the semiconductor substrate S from the transfer module 100 to the storage chamber C2 after the operation S5.
Embodiments of systems and methods for transferring a semiconductor substrate are provided. A center detector, a notch detector, and a cooling member are included in a transfer module. A center or notch of the semiconductor substrate can be detected, and the semiconductor substrate can be cooled by the cooling member when the semiconductor substrate is transferred from a chamber to another chamber. As a result, the time required for processing can be reduced.
According to some embodiments, a method for processing a semiconductor substrate is provided. The method includes loading a semiconductor substrate from a chamber to a transfer module. The method also includes detecting a center and a notch of the semiconductor substrate by the transfer module. The method further includes transferring the semiconductor substrate from the transfer module to a process chamber.
According to some embodiments, a transfer module is provided. The transfer module includes a stage and a carrier. The carrier is connected to the stage and movable with respect to the stage along a first direction. The transfer module also includes a rotating member, which is connected to the stage. The transfer module further includes a center detector and a notch detector. The center detector and the notch detector are connected to the stage and configured to detect a center and a notch of the semiconductor substrate.
According to some embodiments, a system for transferring a semiconductor substrate is provided. The system includes a storage chamber and a first process chamber. The system also includes a station, which is connected to the storage chamber and the first process chamber. The system further includes a transfer module positioned in the station, including a stage, a carrier, a rotating member, a center detector, and a notch detector. The carrier is connected to the stage and movable with respect to the stage along a first direction. The rotating member, the center detector, and the notch detector are connected to the stage, a center and a notch of the semiconductor substrate is detected by the center detector and the notch detector.
Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Number | Name | Date | Kind |
---|---|---|---|
5678320 | Thompson | Oct 1997 | A |
5888102 | Strickland | Mar 1999 | A |
6374143 | Berrang | Apr 2002 | B1 |
6502054 | Mooring | Dec 2002 | B1 |
6510365 | Nishinakayama | Jan 2003 | B1 |
6612801 | Koguchi | Sep 2003 | B1 |
7758338 | Hsiao | Jul 2010 | B2 |
20010003964 | Kitano | Jun 2001 | A1 |
20040151574 | Lu | Aug 2004 | A1 |
20060102285 | Bluck | May 2006 | A1 |
20060104795 | Mimken | May 2006 | A1 |
20060250594 | Iwashita | Nov 2006 | A1 |
20070194005 | Hirakawa | Aug 2007 | A1 |
20070269293 | Yu | Nov 2007 | A1 |
20070274711 | Kaneyama | Nov 2007 | A1 |
20080236488 | Takeshita | Oct 2008 | A1 |
20080280453 | Koelmel | Nov 2008 | A1 |
20090081852 | Tanaka | Mar 2009 | A1 |
20090213347 | Sugihara | Aug 2009 | A1 |
20100051597 | Morita | Mar 2010 | A1 |
20100243437 | Gessert | Sep 2010 | A1 |
20110050882 | Lee | Mar 2011 | A1 |
20110256663 | Hollis | Oct 2011 | A1 |
20120247671 | Sugawara | Oct 2012 | A1 |
20120289058 | Hirano | Nov 2012 | A1 |
Number | Date | Country | |
---|---|---|---|
20150200120 A1 | Jul 2015 | US |