Duty cycle refers to the percentage of time that a periodic digital signal exhibits a high state during a full signal cycle or period. For example, a signal that exhibits a logic high state for 50% of the signal period has a 50% duty cycle. Similarly, for instance, a signal that exhibits a logic high state for 40% of a signal period has a 40% duty cycle.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in some various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between some various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.
Duty cycle refers to the percentage of time that a periodic digital signal exhibits a high state during a full signal cycle or period. It can be challenging to monitor a relatively fast periodic signal (e.g., a multi-GHz signal) and determine its duty cycle via direct measurements. These challenges may result from bandwidth limitations of test equipment and associated accessories, such as cables.
Conventional solutions to determining the duty cycle of a periodic signal are often based in analog technology. In some of the conventional solutions, the periodic signal is converted into a current using an analog circuit, and then the current is converted into a voltage using a low-bandwidth filter or other analog circuitry. The voltage of the signal is measured, and the duty cycle for the periodic signal can be determined based on the measured voltage. A problem with the conventional methods is that the analog circuits used to generate the currents can introduce distortions and inaccuracies into the measurements. These distortions and inaccuracies are especially problematic when the periodic signal is relatively fast (e.g., in the GHz range). The conventional solutions also often require an analog-to-digital converter (ADC) to convert the analog voltages to digital values, which can introduce additional error and inaccuracy into the duty cycle determination. Further, the conventional solutions are also inconvenient because they often require an analog voltage meter to perform the voltage measurements, and such analog voltage meters require additional space and cost.
The approaches of the instant disclosure enable the determination of duty cycles of periodic signals in a manner that is more accurate than the conventional solutions. For example, as explained below, the approaches of the instant disclosure account for unknown variables in the duty cycle determination that can otherwise cause inaccuracies in the calculation. In some embodiments, duty cycles are determined using a delay locked loop (DLL) that delays the periodic signal based on digital control words received from digital circuitry. In addition to being more accurate than the conventional solutions, the approaches of the instant disclosure are also more convenient, space-efficient, and cost-effective because they do not require the use of an analog voltage meter and other components that consume circuit space and add additional cost. These advantages and others of the instant disclosure are described in detail below.
In some embodiments, the digital circuit 110 generates the three distinct digital control words OTWFULL 112a, OTWHIGH 112b, and OTWLOW 112c that cause the delay circuit 104 to delay the periodic input signal 102 by three different amounts of time. The first digital control word OTWFULL 112a generated by the digital circuit 110 causes the delay circuit 104 to delay the periodic input signal 102 by a first amount of time that corresponds to a full period of the periodic input signal 102. The second digital control word OTWHIGH 112b generated by the digital circuit 110 causes the delay circuit 104 to delay the periodic input signal 102 by a second amount of time that corresponds to a portion of the period that the periodic input signal 102 has a logic-level high value. The third digital control word OTWLOW 112c generated by the digital circuit 110 causes the delay circuit 104 to delay the periodic input signal 102 by a third amount of time that corresponds to a portion of the period that the periodic input signal 102 has a logic-level low value.
A phase detector 108 generates signals that are used by the digital circuit 110 in generating the first digital control word OTWFULL 112a, the second digital control word OTWHIGH 112b, and the third digital control word OTWLOW 112c. Specifically, as seen in
The output of the phase detector 108 thus provides a feedback loop to the digital circuit 110 that enables the digital circuit 110 to modify the first digital control word OTWFULL 112a, the second digital control word OTWHIGH 112b, and the third digital control word OTWLOW 112c until the periodic input signal 102 has been delayed the correct amount of time. For instance, in generating the first digital control word OTWFULL 112a, the digital circuit 110 can modify the control word based on feedback from the phase detector 108 until a control word that results in the delay circuit 104 delaying the periodic digital signal 102 by the first amount of time is determined. Likewise, in generating the second digital control word OTWHIGH 112b, the digital circuit 110 can modify the control word based on feedback from the phase detector 108 until a control word that results in the delay circuit 104 delaying the periodic digital signal 102 by the second amount of time is determined. Similarly, in generating the third digital control word OTWLOW 112c, the digital circuit 110 can modify the control word based on feedback from the phase detector 108 until a control word that results in the delay circuit 104 delaying the periodic digital signal 102 by the third amount of time is determined.
In some embodiments, to generate the first digital control word OTWFULL 112a that causes the periodic input signal 102 to be delayed the first amount of time, a divider circuit is utilized.
In some embodiments, to generate the second digital control word OTWHIGH 112b that causes the periodic input signal 102 to be delayed the second amount of time, an inverter circuit is utilized.
In some embodiments, to generate the third digital control word OTWLOW 112c that causes the periodic input signal 102 to be delayed the third amount of time, multiple inverter circuits are utilized.
With reference again to
where OTWFULL is the first digital control word 112a, OTWHIGH is the second digital control word 112b, and OTWLOW is the third digital control word 112c.
In some embodiments, the delay circuit 104 is configured to delay the periodic input signal 102 in accordance with a step size ΔT representing a minimum incremental amount of delay that can be applied by the delay circuit 104. The step size ΔT of a delay circuit (e.g., a DLL-based delay circuit, as described herein) is generally an unknown value that cannot be controlled in the fabrication process. However, in embodiments of the present disclosure, the controller 114 is configured to determine the step size ΔT of the delay circuit 104 based on the duty cycle 116 and the digital control words OTWFULL 112a, OTWHIGH 112b, and OTWLOW 112c. Specifically, in some embodiments, the controller determines the step size ΔT by solving Equation 2:
where FDUT represents a frequency corresponding to the duty cycle (e.g., the duty cycle divided by the pulse width of the periodic input signal 102), OTWFULL represents the first digital tuning word 112a, OTWHIGH represents the second digital tuning word 112b, and OTWLOW represents the third digital tuning word 112c. The step size ΔT determined by solving Equation 2 may provide useful process information (e.g., the step size ΔT may serve as a process indicator indicative of one or more processes used in forming the component for which a duty cycle is being measured).
Equations 1 and 2, used by the controller 114 in calculating the duty cycle 116 and step size ΔT, respectively, can be determined as follows. As explained above, the first digital control word OTWFULL 112a causes the delay circuit 104 to delay the periodic input signal 102 the first amount of time corresponding to the full period of the periodic input signal 102. The relationship between the first amount of time and the first digital control word OTWFULL 112a can be represented by Equation 3:
Full=intrdly+(ΔT)(OTWFULL), (Equation 3)
where Full is the first amount of time, intrdly is an intrinsic delay of the delay circuit 104, OTWFULL is the first digital control word 112a, and ΔT is the step size described above. In embodiments where the delay circuit 104 uses a delay train or other types of delay elements (e.g., delay elements containing logic gates, etc.), the intrdly term represents the intrinsic delay of such delay elements. The intrinsic delay intrdly and the step size ΔT are both non-controllable, unknown parameters in silicon. In order to accurately calculate the duty cycle 116, embodiments of the present disclosure remove the intrdly and ΔT terms via mathematical manipulation, as described below.
The second digital control word OTWHIGH 112b causes the delay circuit 104 to delay the periodic input signal 102 the second amount of time corresponding to the portion of the period that the periodic input signal 102 has a logic-level high value, as explained above. The relationship between the second amount of time and the second digital control word OTWHIGH can be represented by Equation 4:
Hi=intrdly+(ΔT)(OTWHIGH), (Equation 4)
where Hi is the second amount of time, intrdly is the intrinsic delay of the delay circuit 104, OTWHIGH is the second digital control word 112b, and ΔT is the step size described above.
The third digital control word OTWLOW 112c causes the delay circuit 104 to delay the periodic input signal 102 the third amount of time corresponding to the portion of the period that the periodic input signal 102 has a logic-level low value. The relationship between the third amount of time and the third digital control word OTWLOW can be represented by Equation 5:
Lo=intrdly+(ΔT)(OTWLOW) (Equation 5)
where Lo is the third amount of time, intrdly is the intrinsic delay of the delay circuit 104, OTWLOW is the third digital control word 112c, and ΔT is the step size as described above.
The intrdly term can be removed by manipulating Equations 3-5 using subtraction operations:
Hi′=Full−Lo=(ΔT)(OTWFULL−OTWLOW), (Equation 6)
Lo′=Full−Hi=(ΔT)(OTWFULL−OTWHIGH), (Equation 7)
Full′=Hi′+Lo′=(ΔT)((2*OTWFULL)−OTWHIGH−OTWLOW), (Equation 8)
As seen above, Equation 8 represents the first amount of time (i.e., an amount of time equal to a full period of the periodic input signal 102) but does not depend on the intrinsic delay term intrdly. Likewise, Equations 6 and 7 represent the second and third amounts of time, respectively, but do not depend on the intrinsic delay term intrdly. Accordingly, Equations 6-8 show that the intrinsic delay term intrdly has been removed by mathematical manipulation. Further, with the intrinsic delay term intrdly removed, Equations 6-8 are free of process, voltage, and temperature (PVT) artifact fluctuations.
Equation 1, used in calculating the duty cycle 116, can be derived by dividing Equation 6 by Equation 8:
As seen above, by dividing the equations for Hi′ by Full′, the step size term ΔT is removed via the division operation. This is evident from Equation 1, above, which enables the calculation of the duty cycle 116 using only the digital control words OTWFULL 112a, OTWHIGH 112b, and OTWLOW 112c, and does not depend on the step size term ΔT. After the duty cycle 116 is determined, the step size term ΔT can be calculated via Equation 2 to obtain useful process information, as explained above.
As is further explained below with reference to
Embodiments described below with reference to
In some embodiments, the digital control words generated by the digital circuit 3240 include the three distinct digital control words OTWFULL, OTWHIGH, and OTWLOW described above with reference to
The circuit of
As shown in the table above, when Sw=1 and Xor=0, the first digital control word OTWFULL used in delaying the periodic input signal 3002 the first amount of time is generated. When Sw=0 and Xor=0, the second digital control word OTWHIGH used in delaying the periodic input signal 3002 the second amount of time is generated. When Sw=0 and Xor=1, the third digital control word OTWLOW used in delaying the periodic input signal 3002 the third amount of time is generated. Accordingly, by progressing through the different combinations of Sw and Xor, the circuit of
The phase detector 3131 generates signals that are used by the digital circuit 3240 in generating the first, second, and third digital control words OTWFULL, OTWHIGH, and OTWLOW. Specifically, as seen in
To generate the first digital control word OTWFULL that causes the periodic input signal 3002 to be delayed the first amount of time, a divider circuit 3111 and XOR gate 3113 are utilized, among other components. The divider circuit 3111 divides the periodic input signal 3002 by two (2) to generate a slower, divided version of the periodic input signal. The divided version of the periodic input signal and the undivided periodic input signal 3002 are received at inputs of a multiplexer 3112, which selects one of the two received signals and propagates the selected signal.
The XOR gate 3113 (i) functions as an inverter when the Xor signal is equal to a first value (e.g., 1′b1), and (ii) does not invert a received input signal when the Xor signal is equal to a second value (e.g., 1′b0). Accordingly, when the multiplexer 3112 propagates the divided version of the periodic input signal and the XOR gate 3113 inverts that divided signal, the output of the XOR gate 3113 is a divided, inverted version of the periodic input signal, similar to the waveform 1301 described above with reference to
To generate the second digital control word OTWHIGH that causes the periodic input signal 3002 to be delayed the second amount of time, the XOR gate 3113 is utilized, among other components. As explained above, the XOR gate 3113 functions as an inverter when the Xor signal is equal to the first value. Accordingly, when the multiplexer 3112 propagates the periodic input signal 3002 and the XOR gate 3113 inverts that signal, the output of the XOR gate 3113 is an inverted version of the periodic input signal 3002, similar to the waveform 1101 described above with reference to
To generate the third digital control word OTWLOW that causes the periodic input signal 3002 to be delayed the third amount of time, the XOR gate 3113 is again utilized as an inverter, among other components. Specifically, in some embodiments, the XOR gate 3113 is used to propagate (i) a first waveform representative of an inverted version of the periodic input signal 3002 (e.g., waveform 1202 shown in
In the circuit of
Along with the features described above, the circuit of
In
The selection module 3110 of the analog block 3100 includes divider 3111, multiplexer 3112, XOR gate 3113, and two D flip flops 3114, 3115. In the analog block 3100, the periodic input signal 3002 is received by the divider 3111 and a first input pin of the multiplexer 3112. An output of the divider 3111 is electrically connected to a second input pin of the multiplexer 3112, and a control pin of the multiplexer 3112 for determining the multiplexer's selection is connected to an output of the D flip flop 3114. Further, the output of the multiplexer 3112 is connected to a first input of the XOR gate 3113, and an output of the D flip flop 3115 is connected to a second input of the XOR gate 3113.
In
The 2-bit counter 3210 generates three distinct outputs (e.g., 2′b00, 2′b01 and 2′b10), which are used to control the selection module 3110 for generating three patterns. The combination of the selection module 3110 and the 2-bit counter 3210 may be understood as making up a pattern generator module 4000, as labeled in
The locking signal LD is received by D flip flops 3232, 3233, which sample the LD signal twice. In some embodiments, the first sampling turns the locking signal LD into a strobe clock fSTROBE, and the second sampling turns the locking signal LD into a triggering event to trigger the reset block 3250 and the 2-bit counter 3210. The strobe clock fSTROBE drives the D flip flops 3232, 3233 to store the digital control word generated by the digital circuit 3240 and divide-by-3 block 3231. In some embodiments, another strobe clock fSTROBE_DIV3 generated by the divide-by-3 block 3231 is used by the controller 3230 to latch the three digital control words OTWFULL, OTWHIGH AND OTWLOW.
As explained above, the second sampling of the locking signal LD turns the signal LD into a triggering event to trigger the reset block 3250 and the 2-bit counter 3210. The triggering event has one clock latency compared to fSTROBE, and as a result, the reset block 3250 sends a reset signal to the digital circuit 3240 after finishing the storage of the digital control words from the digital circuit 3240. The triggering event also drives the 2-bit counter 3210 for changing the output state. In some embodiments, the three outputs of the 2-bit counter 3210 represent high period measurement in 2′b00, low period measurement in 2′b01, and full period measurement in 2′b10.
In the embodiment of
In some embodiments, the 2-bit counter 3210 generates three states: 2b′00, 2′b01 and 2′b10. The MSB (most significant bit) of 2-bit output is denoted “Sw,” and the LSB (least significant bit) is denoted “Xor.” According to some embodiments, the signal Xor controls the XOR-gate 3113 to either invert the periodic input signal 3002 or not (e.g., “1” means to invert the periodic input signal 3002, and “0” means to propagate the periodic input signal 3002 without inversion). According to some embodiments, the signal Sw controls the multiplexer 3112 to choose either the periodic input signal 3002 or the version of the periodic input signal 3002 that has been divided by two (2), as generated by divider 3111.
In some embodiments, the locking signal LD from the digital circuit 3240 is resampled by the system clock fSYS at a falling edge to generate the strobe clock fSTROBE used in capturing the digital control words OTWFULL, OTWHIGH, and OTWLOW. The reset block 3250 is triggered by the locking signal LD via a second sampling that is required to reset the digital circuit 3240 for a new period measurement. One additional cycle delay, however, can ensure that the digital control word data is stored before the reset of digital circuit 3240. In some embodiments, the first sampling of OTWFULL, OTWHIGH, and OTWLOW via fSTROBE is captured by a low-speed clock (where fSTROBE_DIV3 is fSTROBE divided by 3) for the calculation of the final period of Hi′ and Full′ free of PVT artifact fluctuations.
Example sequences of timing diagrams are illustrated in
Reset block 3250 sends a signal to the digital circuit 3240 to drop down the locking signal LD 6004 and restart period tracking, and the 2-bit counter 3210 changes state to 2′b10 from 2′b01. In some embodiments, the state of “Sw” 6010 and “Xor” 6009 becomes 2′b10, and the periodic input signal 3002 is provided to the divider 3111. The digital circuit 3240 implements the same procedure as discussed above to complete period tracking and generate “H” in the locking signal LD. The fSTROBE 6005 drives D flip flops 3232, 3233 to store OTWFULL, and the rising edge of fSTROBE_DIV3 6007 drives the D flip flops 3237, 3238, and 3239 to latch the three different digital control words OTW (e.g., OTWFULL, OTWHIGH, OTWLOW, as described herein). These control words are used in calculating the duty cycle and step size ΔT. According to some embodiments, the 2-bit counter 3210 receives trigger event to change the state from 2′b10 to 2b′00 for the calculation.
As described above, the circuit of
The D-type flip-flop performs reliably as described above when the data input signal 820 is a logic-level high/low for a first minimum amount of time before (and a second minimum amount of time after) each triggering edge of the clock input signal 810. These first and second minimum amounts of time are referred to as a set-up time and a hold time of the D-type flip-flop, respectively.
The second circuit 1020 is configured to receive the periodic input signal 102 and to generate a clock input signal 1040 and a data input signal 1050 at outputs of the circuit 1000 based on the periodic input signal 102 received thereby. The D-type flip-flop 1030 receives the clock input signal 1040 at the clock input (CK) thereof and the data input signal 1050 at the data input (D) thereof to generate a data output signal 1060 at the data output (Q) thereof.
In further detail,
The first delay circuit 1120 is configured to receive the first input signal 1150 and a fixed digital control word 1120′ so as to delay the first input signal 1150 by a fixed amount of time based on the fixed digital control word 1120′, generating a delayed version of the first input signal 1150. The delayed version of the first input signal 1150 serves as the clock input signal 1040.
The second divider circuit 1130 is configured to receive the first input signal 1150 and to divide the first input signal 1150 by a second predetermined number (Y) so as to generate a second input signal 1160. In this exemplary embodiment, the second predetermined number (Y), e.g., 2, is less than the first predetermined number (X).
The second delay circuit 1140 is configured to receive the second input signal 1160 and a variable digital control word 1140′ so as to delay the second input signal 1160 by different amounts of time based on the variable digital control word 1140′, generating different delayed versions of the second input signal 1160. Each delayed version of the second input signal 1160 serves as the data input signal 1050.
In operation, when it is desired to determine a parameter, e.g., metastability window, of the D-type flip-flop 1030, the fixed digital control word 1120′ is adjusted at a fixed value to generate the delayed version 1040 of the first input signal 1150. Next, the variable digital control word 1140′ is adjusted at different values to generate the delayed versions 1050 of the second input signal 1160.
Next, the values of the variable digital control word 1140′ at which the D-type flip-flop 1030 enters and leaves the metastable state are obtained based on the data output signal 1060 of the D-type flip-flop 1030. For example,
Next, the step size (ΔT) generated by the first circuit 1010 is obtained at the output of the circuit 1000. Thereafter, the metastability window of the D-type flip-flop 1030 is determined by solving Equation 10:
(V1−V2+V3)×ΔT (Equation 10)
where V1 is the value of the variable digital control word 1140′ at which the D-type flip-flop 1030 leaves the metastable state, V2 is the value of the variable digital control word 1140′ at which the D-type flip-flop 1030 enters the metastable state, V3 is the value by which the variable digital control word 1140′ is incremented, and ΔT is the step size. Thus, in the example of
At 1440, the second divider circuit 1120 receives the first input signal 1150 and divides the first input signal 1150 received thereby by a second predetermined number (Y) to generate a second input signal 1160. At 1450, the second delay circuit 1140 receives the second input signal 1160 and a variable digital control word 1140′ to delay the second input signal 1160 by different amounts of time based on the variable digital control word 1140′, generating different delayed versions 1050 of the second input signal 1160 at an output thereof.
The D-type flip-flop 1030 generates a data output signal 1060 at the data output (Q) thereof based on the clock input signal 1040 at the clock input (CK) thereof and the data input signal 1050 at the data input (D) thereof. The metastability window of the D-type flip-flop 1030 may be determined as described above with reference to
In an alternative embodiment, the circuit 1000 is dispensed with the first circuit 1010 and the step size (ΔT) is obtained from a circuit external to the circuit 1000.
The second circuit 1520 is configured to receive the periodic input signal 102 and to generate a clock input signal 1540 at an output of the circuit 1500 based on the periodic input signal 102 received thereby. The D-type flip-flop 1530 receives the clock input signal 1540 at the clock input (CK) thereof and a data input signal 1550 at the data input (D) thereof to generate a data output signal 1560 at the data output (Q) thereof.
In further detail,
The first delay circuit 1620 is configured to receive the input signal 1650 and a fixed digital control word 1620′ so as to delay the input signal 1650 by a fixed amount of time based on the fixed digital control word 1620′, generating a delayed version 1660 of the input signal 1650.
The second delay circuit 1630 is configured to receive the input signal 1650 and a variable digital control word 1630′ so as to delay the input signal 1650 by different amounts of time based on the variable digital control word 1630′, generating different delayed versions 1670 of the input signal 1650.
The pulse width modulator (PWM) 1640 is configured to receive the delayed version 1660 of the input signal 1650 and the different delayed versions 1670 of the input signal 1650 so as to generate a plurality of PWM signals, each of which has a distinct duty cycle. Each PWM signal serves as a clock input signal 1540 at the clock input (CK) of the D-type flip-flop 1530.
In this exemplary embodiment, the PWM 1640 includes one or more logic gates, one or more latch circuits, or a combination thereof. For example, the PWM 1640 includes an AND gate and an inverter. The AND gate has a first input connected to the first delay circuit 1620 and an output connected to the clock input (CK) of the D-type flip-flop 1530. The inverter is connected between the second delay circuit 1630 and a second input of the AND gate.
In operation, when it is desired to determine a parameter, e.g., metastability window, of the D-type flip-flop 1530, the fixed digital control word 1620′ is adjusted at a fixed value to generate the delayed version 1660 of the input signal 1650. Next, the variable digital control word 1630′ is adjusted at different values to generate the delayed versions 1670 of the input signal 1650, whereby the PWM 1640 generates the PWM signals 1540.
Next, the values of the variable digital control word 1630′ at which the D-type flip-flop 1530 enters and leaves the metastable state are obtained based on the data output signal 1560 of the D-type flip-flop 1530. For example,
Next, the step size (ΔT) generated by the first circuit 1510 is obtained at the output of the circuit 1500. Thereafter, the metastability window of the D-type flip-flop 1530 is determined by solving equation 10 described above. Thus, in the example of
At 1940, the second delay circuit 1630 receives the input signal 1650 and a variable digital control word 1630′ to delay the input signal 1650 by different amounts of time based on the variable digital control word 1630′, generating different delayed versions 1670 of the input signal 1650.
At 1950, the PWM 1640 receives the delayed version 1660 of the input signal 1650 and the different delayed versions 1670 of the input signal 1650 to generate a plurality of PWM signals 1540, each of which has a distinct duty cycle.
The D-type flip-flop 1530 generates a data output signal 1560 at the data output (Q) thereof based on the clock input signal 1540 at the clock input (CK) thereof and the data input signal 1550 at the data input (D) thereof. The metastability window of the D-type flip-flop 1530 may be determined as described above with reference to
In an alternative embodiment, the circuit 1500 is dispensed with the first circuit 1510 and the step size (ΔT) is obtained from a circuit external to the circuit 1500.
In some embodiments, the DUT 1530 is a memory circuit. In such some embodiments, the circuit 1500 may be used to determine a parameter associated with a read/write operation of the memory circuit.
The present disclosure is directed to circuits, methods, and devices for determining a duty cycle of a periodic input signal. In an example method for determining a duty cycle of a periodic input signal, the periodic input signal is received at a delay circuit configured to delay the periodic input signal based on a digital control word. A first digital control word is generated, where the first digital control word is used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal. A second digital control word is generated, where the second digital control word is used to delay the periodic input signal a second amount of time corresponding to a portion of the period that the periodic input signal has a logic-level high value. A third digital control word is generated, where the third digital control word is used to delay the periodic input signal a third amount of time corresponding to a portion of the period that the periodic input signal has a logic-level low value. The duty cycle of the periodic input signal is determined based on the first, second, and third digital control words.
An example circuit for determining a duty cycle of a periodic input signal includes a delay element configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal. The digital circuit is also configured to generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the period that the periodic input signal has a logic-level high value. The digital circuit is further configured to generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the period that the periodic input signal has a logic-level low value. The example circuit also includes a controller configured to determine the duty cycle of the periodic input signal based on the first, second, and third digital control words.
An example circuit for determining a duty cycle of a periodic input signal includes a delay locked loop with a delay train and a phase detector. The delay locked loop being configured to receive the periodic input signal. The circuit also includes a digital circuit configured to receive an output of the phase detector indicating an alignment between the periodic input signal and a delayed version of the periodic input signal. The digital circuit is also configured to generate digital control words for controlling an amount of delay applied by the delay train. The digital control words include a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the period that the periodic input signal has a logic-level high value, and a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the period that the periodic input signal has a logic-level low value. The circuit also includes a controller configured to determine the duty cycle of the periodic input signal based on the first, second, and third digital control words.
The present disclosure is further directed to circuits, methods, and devices for facilitating measurement of a parameter of a DUT. An example circuit configured to facilitate measurement of a parameter of a DUT includes a first divider circuit, a first delay circuit, a second divider circuit, and a second delay circuit. The first divider circuit is configured to divide a periodic input signal by a first predetermined number so as to generate a first input signal. The first delay circuit is configured to generate a delayed version of the first input signal. The second divider circuit is configured to divide the first input signal by a second predetermined number so as to generate a second input signal. The second delay circuit is configured to generate different delayed versions of the second input signal. The parameter of the DUT is determined based on the delayed version of the first input signal and the different delayed versions of the second input signal.
An example circuit configured to facilitate measurement of a parameter of DUT includes a divider circuit, a first delay circuit, and a second delay circuit. The divider circuit is configured to divide a periodic input signal by a predetermined number so as to generate an input signal. The first delay circuit is configured to generate a delayed version of the input signal. The second delay circuit is configured to generate different delayed versions of the input signal. The delayed version of the input signal and the different delayed versions of the input signal are associated with the parameter of the DUT.
A method for facilitating measurement of a parameter of a device under test (DUT) includes the steps of: receiving a periodic input signal; dividing the periodic input signal by a first predetermined number to generate a first input signal; dividing the first input signal by a second predetermined number to generate a second input signal; and delaying the second input signal to generate different delayed versions of the second input signal. The different delayed versions of the second input signal are associated with the parameter of the DUT.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application is a continuation-in-part of U.S. patent application Ser. No. 17/124,580, entitled “Systems and Methods for Duty Cycle Measurement,” filed Dec. 17, 2020, which claims priority from U.S. Provisional Application No. 62/982,176, filed Feb. 27, 2020, entitled “All Digital Solution for Duty-Cycle Measurement and Process Indicator.” This application further claims priority from U.S. Provisional Application No. 6/407,232, filed Sep. 16, 2022. All of these are incorporated herein by reference in their entireties.
Number | Date | Country | |
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62982176 | Feb 2020 | US | |
63407232 | Sep 2022 | US |
Number | Date | Country | |
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Parent | 17124580 | Dec 2020 | US |
Child | 18150845 | US |