Modern microprocessors operate much faster than associated memories where program data is kept. In particular, main memories operate much slower than do modern microprocessors. Because of this, program data may not be able to be read fast enough to keep a microprocessor busy. Moreover, the performance gap creates a bottleneck that is the source of latency. Cache memory is used to help ameliorate the performance gap that exists between processors and main memory. Cache memory is memory that is smaller in storage capacity than main memory, but is memory that can be accessed much more quickly than can main memory.
As such, cache memory is used by the central processing unit of a computer to reduce the time that it takes to access data and instructions associated with the execution of an application. Cache memory is small, high speed memory, usually static RAM, which stores copies of data and instructions accessed from the most recently used main memory locations. As long as data and instructions are accessed from cached memory locations, the latency associated with data and instruction accesses is that of cache memory accesses as opposed to being that of main memory accesses, which are much slower. Cache memory improves latency by decreasing the time that it takes to move information to and from the processor.
Cache flushing is the intentional removal of information from a cache. Individual modified or dirty cache lines can be evicted from a cache and written into main memory in an operation called a write-back. The write-back updates the version of the cache line that is stored in main memory. A writeback may result from actions in either hardware or software. If the write-back was initiated by software, as a result of the execution of a cache flush instruction, after the processor finishes the write-backs, it then generates a special bus cycle called a flush acknowledge cycle.
In conventional processors, when a flush of data from a cache is requested, the processor is stalled until the flush of data to main memory or the next level of cache is completed. As such, latency that is attributable to the period during which the processor waits for the write backs to complete is incurred. Accordingly, some conventional processors exhibit an unsatisfactory latency that is attributable to the waiting period that is associated with writebacks to main memory (or other locations).
Conventional processors exhibit an unsatisfactory latency that is attributable to the waiting period that is associated with data write-backs. A method for non-blocking implementation of cache flush instructions is disclosed that addresses these shortcomings. However, the claimed embodiments are not limited to implementations that address any or all of the aforementioned shortcomings. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the processor executing the cache flush instruction is prematurely/expediently notified that the cache flush operation is completed. Subsequent to such notification, access is provided to data then present in the write-back data holding buffer to determine if data then present in the writeback data holding buffer is flagged. The aforementioned methodology does not require a waiting period during which the processor waits (e.g., is stalled) for write-backs to complete. Accordingly, the aforementioned methodology avoids unsatisfactory latency that is attributable to the waiting period that is associated with data flushes in conventional processors.
The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:
It should be noted that like reference numbers refer to like elements in the figures.
Although the present invention has been described in connection with one embodiment, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the scope of the invention as defined by the appended claims.
In the following detailed description, numerous specific details such as specific method orders, structures, elements, and connections have been set forth. It is to be understood however that these and other specific details need not be utilized to practice embodiments of the present invention. In other circumstances, well-known structures, elements, or connections have been omitted, or have not been described in particular detail in order to avoid unnecessarily obscuring this description.
References within the specification to “one embodiment” or “an embodiment” are intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearance of the phrase “in one embodiment” in various places within the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments.
Some portions of the detailed descriptions, which follow, are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, computer executed step, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals of a computer readable storage medium and are capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as “receiving” or “accessing” or “flagging” or “notifying” or the like, refer to the action and processes of a computer system, or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories and other computer readable media into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
Referring to
WDHB 109 receives data that is flushed from L2 cache 107 based on a software based request to flush the data to main memory/next level cache/private memory of device. WDHB 109 is a temporary data holding buffer that temporarily holds data that is in the process of being flushed from L2 cache 107 to main memory/next level cache/private memory of a device 111. In one embodiment, as shown in
In one embodiment, as illustrated in
Referring again to
Main Memory/Next Level Cache/Private Memory of Device 111 stores data that is flushed from L2 cache 107 to main memory/next level cache/private memory of device 111 via WDHB 109. Having been placed into WDH B 109 to avoid blocking the ingress of data into L2 cache 107, data is moved to main memory/next level cache/private memory of device 111 when the interconnect fabric authorizes the forwarding of the data from WDHB 109. The data that is flushed to main memory/next level cache/private memory of device from L2 cache 107 updates the data that is stored in the involved address of main memory/next level cache/private memory of device 111. Also shown in
Referring to
At B, data is flushed from L2 cache 107 and forwarded to WDHB 109. In one embodiment, WDHB 109 has an 8 entry data holding capacity. In other embodiments, WDHB 109 can have other data holding capacities.
At C, system 101 accesses the data that is received by WDHB 109 and flags the data with a processor identifier and a serialization flag. In one embodiment, the processor identifier and the serialization flag refer to a specific processor and a specific cache flush.
At D, responsive to the flagging of the data, L2 cache 107 is notified that the cache flush has been completed (that the data has been written back to main memory/next level cache/private memory of device 111). In one embodiment, L2 cache 107 is notified that that the cache flush has been completed, in response to the flagging of the data and before the data is actually written-back to main memory/next level cache/private memory of device 111.
At E, the data that is flushed from L2 cache 107 is written-back to main memory/next level cache/private memory of device 111. At F, access to the contents of the write-back data holding buffer is provided to a serialization instruction in the software program that initiated the cache flush request. The serialization instruction ensures that the write-back of data is completed before subsequent instructions in the software program can be executed. The serialization operation uses the flags to identify data held in WDHB 109 that is associated with a specific processor core and data flush request, and blocks the execution of subsequent instructions, until the write-back of the identified data is completed.
Referring to
Data flagger 203 flags the data that is flushed to the write-back data holding buffer with a processor identifier and a serialization flag. In one embodiment, the flagging enables data associated with a specific processor core and a specific flush to be identified from among other data associated with various other processor cores and flushes that are extant on a chip.
Cache notifier 205, responsive to the flagging, notifies L2 cache that a flush of the flagged data has been completed (e.g., that the data has been written back to main memory/next level cache/private memory of device). In one embodiment, the notification is provided to L2 cache prior to the completion of the flush of the flagged data to main memory/next level cache/private memory of device.
Access provider 207, after a cache flush completion notification is provided to the cache, provides access to the data that is then present in the write-back holding buffer, such that it can be determined if the data then present in the write-back data holding buffer is flagged. In one embodiment, access is provided to a serialization instruction, which determines if any of the data then present in the write-back data holding buffer is flagged.
It should be appreciated that the aforementioned components of system 101 can be implemented in hardware or software or in a combination of both. In one embodiment, components and operations of system 101 can be encompassed by components and operations of one or more computer components or operations (e.g., cache controller 102 in
Referring to
At 303, data is accessed that is received by a write-back data holding buffer as a part of the cache flushing operation.
At 305, the flushed data is flagged with a processor identifier and a serialization flag. In one embodiment, as described herein, the flagging enables data associated with a specific processor core and a specific flush to be distinguished from among other data associated with various other processor cores and flushes that can be extant on a chip.
At 307, the L2 cache is notified that a write-back of the data to main memory/next level cache/private memory of device has been completed (that the flush of the data to main memory/next level cache/private memory of device is completed) prior to the actual completion of the write-back of the data to main memory/next level cache/private memory of device. In one embodiment, the cache is notified that a write-back of the data to main memory/next level cache/private memory of device has been completed in response to the flagging of the data.
At 309, subsequent to notifying the L2 cache that a write-back of the flagged data to main memory/next level cache/private memory of device has been completed, access is provided to data then present in the write-back holding buffer to determine if the data then present in the write-back data holding buffer has been flagged.
With regard to exemplary embodiments thereof, systems and methods for efficient cache flushing are disclosed. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the cache is notified that the cache flush is completed. Subsequent to the notifying, access is provided to data then present in the write-back data holding buffer to determine if data then present in the write-back data holding buffer is flagged.
Although many of the components and processes are described above in the singular for convenience, it will be appreciated by one of skill in the art that multiple components and repeated processes can also be used to practice the techniques of the present invention. Further, while the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that changes in the form and details of the disclosed embodiments may be made without departing from the spirit or scope of the invention. For example, embodiments of the present invention may be employed with a variety of components and should not be restricted to the ones mentioned above. It is therefore intended that the invention be interpreted to include all variations and equivalents that fall within the true spirit and scope of the present invention.
This application is a continuation of Ser. No. 15/003,486, filed Jan. 21, 2016 (now U.S. Pat. No. 9,842,056, issued Dec. 12, 2017), which is a continuation of U.S. application Ser. No. 13/649,532, filed Oct. 11, 2012 (now U.S. Pat. No. 9,678,882, issued Jun. 13, 2017), which is hereby incorporated by reference.
Number | Name | Date | Kind |
---|---|---|---|
4075704 | O'Leary | Feb 1978 | A |
4245344 | Richter | Jan 1981 | A |
4356550 | Katzman et al. | Oct 1982 | A |
4414624 | Summer, Jr. et al. | Nov 1983 | A |
4524415 | Mills, Jr. et al. | Jun 1985 | A |
4527237 | Frieder et al. | Jul 1985 | A |
4577273 | Hopper et al. | Mar 1986 | A |
4597061 | Cline et al. | Jun 1986 | A |
4600986 | Scheuneman et al. | Jul 1986 | A |
4633434 | Scheuneman | Dec 1986 | A |
4682281 | Woffinden et al. | Jul 1987 | A |
4816991 | Watanabe et al. | Mar 1989 | A |
4920477 | Colwell et al. | Apr 1990 | A |
5294897 | Notani et al. | Mar 1994 | A |
5317705 | Gannon et al. | May 1994 | A |
5317754 | Blandy et al. | May 1994 | A |
5548742 | Wang et al. | Aug 1996 | A |
5559986 | Alpert et al. | Sep 1996 | A |
5574878 | Onodera et al. | Nov 1996 | A |
5634068 | Nishtala et al. | May 1997 | A |
5752260 | Liu | May 1998 | A |
5754818 | Mohamed | May 1998 | A |
5758166 | Ajanovic | May 1998 | A |
5787243 | Stiffler | Jul 1998 | A |
5787494 | Delano et al. | Jul 1998 | A |
5793941 | Pencis et al. | Aug 1998 | A |
5802602 | Rahman et al. | Sep 1998 | A |
5806085 | Berliner | Sep 1998 | A |
5809524 | Singh | Sep 1998 | A |
5813031 | Chou et al. | Sep 1998 | A |
5835951 | McMahan | Nov 1998 | A |
5852738 | Bealkowski et al. | Dec 1998 | A |
5860146 | Vishin et al. | Jan 1999 | A |
5864657 | Stiffler | Jan 1999 | A |
5872985 | Kimura | Feb 1999 | A |
5881277 | Bondi et al. | Mar 1999 | A |
5903750 | Yeh et al. | May 1999 | A |
5905509 | Jones et al. | May 1999 | A |
5918251 | Yamada et al. | Jun 1999 | A |
5956753 | Glew et al. | Sep 1999 | A |
5974506 | Sicola et al. | Oct 1999 | A |
6016533 | Tran | Jan 2000 | A |
6073230 | Pickett et al. | Jun 2000 | A |
6075938 | Bugnion et al. | Jun 2000 | A |
6088780 | Yamada et al. | Jul 2000 | A |
6092172 | Nishimoto et al. | Jul 2000 | A |
6101577 | Tran | Aug 2000 | A |
6115809 | Mattson, Jr. et al. | Sep 2000 | A |
6134634 | Marshall, Jr. et al. | Oct 2000 | A |
6138226 | Yoshioka et al. | Oct 2000 | A |
6157998 | Rupley, II et al. | Dec 2000 | A |
6167490 | Levy et al. | Dec 2000 | A |
6205545 | Shah et al. | Mar 2001 | B1 |
6212613 | Belair | Apr 2001 | B1 |
6226732 | Pei et al. | May 2001 | B1 |
6247097 | Sinharoy | Jun 2001 | B1 |
6253316 | Tran et al. | Jun 2001 | B1 |
6256727 | McDonald | Jul 2001 | B1 |
6256728 | Witt et al. | Jul 2001 | B1 |
6260131 | Kikuta et al. | Jul 2001 | B1 |
6260138 | Harris | Jul 2001 | B1 |
6272662 | Jadav et al. | Aug 2001 | B1 |
6275917 | Okada | Aug 2001 | B1 |
6321298 | Hubis | Nov 2001 | B1 |
6332189 | Baweja et al. | Dec 2001 | B1 |
6341324 | Caulk, Jr. et al. | Jan 2002 | B1 |
6437789 | Tidwell et al. | Aug 2002 | B1 |
6442700 | Cooper | Aug 2002 | B1 |
6449671 | Patkar et al. | Sep 2002 | B1 |
6457120 | Sinharoy | Sep 2002 | B1 |
6557083 | Sperber et al. | Apr 2003 | B1 |
6594755 | Nuechterlein et al. | Jul 2003 | B1 |
6604187 | McGrath et al. | Aug 2003 | B1 |
6609189 | Kuszmaul et al. | Aug 2003 | B1 |
6658549 | Wilson et al. | Dec 2003 | B2 |
6681395 | Nishi | Jan 2004 | B1 |
6907600 | Neiger et al. | Jun 2005 | B2 |
6912644 | O'Connor et al. | Jun 2005 | B1 |
7007108 | Emerson et al. | Feb 2006 | B2 |
7111145 | Chen et al. | Sep 2006 | B1 |
7143273 | Miller et al. | Nov 2006 | B2 |
7149872 | Rozas et al. | Dec 2006 | B2 |
7213106 | Koster et al. | May 2007 | B1 |
7278030 | Chen et al. | Oct 2007 | B1 |
7380096 | Rozas et al. | May 2008 | B1 |
7406581 | Southwell et al. | Jul 2008 | B2 |
7546420 | Shar et al. | Jun 2009 | B1 |
7680988 | Nickolls et al. | Mar 2010 | B1 |
7783868 | Ukai | Aug 2010 | B2 |
7856530 | Mu | Dec 2010 | B1 |
7913058 | Rozas et al. | Mar 2011 | B2 |
8145844 | Bruce | Mar 2012 | B2 |
8239656 | Rozas et al. | Aug 2012 | B2 |
8301847 | Dantzig et al. | Oct 2012 | B2 |
8522253 | Rozas et al. | Aug 2013 | B1 |
8868838 | Glasco et al. | Oct 2014 | B1 |
8930674 | Avudaiyappan et al. | Jan 2015 | B2 |
9047178 | Talagala et al. | Jun 2015 | B2 |
20010049782 | Hsu et al. | Dec 2001 | A1 |
20020069326 | Richardson et al. | Jun 2002 | A1 |
20020082824 | Neiger et al. | Jun 2002 | A1 |
20020099913 | Steely et al. | Jul 2002 | A1 |
20030028737 | Kaiya et al. | Feb 2003 | A1 |
20030065887 | Maiyuran et al. | Apr 2003 | A1 |
20030088752 | Harman | May 2003 | A1 |
20040034762 | Kacevas | Feb 2004 | A1 |
20040044850 | George et al. | Mar 2004 | A1 |
20040064668 | Kjos et al. | Apr 2004 | A1 |
20040093483 | Nguyen et al. | May 2004 | A1 |
20040117441 | Liu et al. | Jun 2004 | A1 |
20040117593 | Uhlig et al. | Jun 2004 | A1 |
20040117594 | Vanderspek | Jun 2004 | A1 |
20040143727 | McDonald | Jul 2004 | A1 |
20040193857 | Miller et al. | Sep 2004 | A1 |
20040205296 | Bearden | Oct 2004 | A1 |
20040215886 | Cargnoni et al. | Oct 2004 | A1 |
20040225872 | Bonanno et al. | Nov 2004 | A1 |
20050005085 | Miyanaga | Jan 2005 | A1 |
20050027961 | Zhang | Feb 2005 | A1 |
20050027972 | Harrington | Feb 2005 | A1 |
20050044320 | Olukotun | Feb 2005 | A1 |
20050060457 | Olukotun | Mar 2005 | A1 |
20050108480 | Correale, Jr. et al. | May 2005 | A1 |
20050154867 | Dewitt et al. | Jul 2005 | A1 |
20060004964 | Conti et al. | Jan 2006 | A1 |
20060015689 | Okawa | Jan 2006 | A1 |
20060026381 | Doi et al. | Feb 2006 | A1 |
20060190707 | McIlvaine et al. | Aug 2006 | A1 |
20060236074 | Williamson et al. | Oct 2006 | A1 |
20060277365 | Pong | Dec 2006 | A1 |
20080077813 | Keller et al. | Mar 2008 | A1 |
20080091880 | Vishin | Apr 2008 | A1 |
20080126771 | Chen et al. | May 2008 | A1 |
20080195844 | Shen et al. | Aug 2008 | A1 |
20080215865 | Hino et al. | Sep 2008 | A1 |
20080235500 | Davis et al. | Sep 2008 | A1 |
20080270758 | Ozer et al. | Oct 2008 | A1 |
20080270774 | Singh et al. | Oct 2008 | A1 |
20080282037 | Kusachi et al. | Nov 2008 | A1 |
20090138659 | Lauterbach | May 2009 | A1 |
20090157980 | Bruce | Jun 2009 | A1 |
20090158017 | Mutlu et al. | Jun 2009 | A1 |
20090164733 | Kim et al. | Jun 2009 | A1 |
20090172344 | Grochowski et al. | Jul 2009 | A1 |
20090287912 | Sendag | Nov 2009 | A1 |
20100138607 | Hughes et al. | Jun 2010 | A1 |
20100169578 | Nychka et al. | Jul 2010 | A1 |
20100169611 | Chou et al. | Jul 2010 | A1 |
20100211746 | Tsukishiro | Aug 2010 | A1 |
20110010521 | Wang et al. | Jan 2011 | A1 |
20110082980 | Gschwind et al. | Apr 2011 | A1 |
20110082983 | Koktan | Apr 2011 | A1 |
20110153955 | Herrenschmidt | Jun 2011 | A1 |
20120005462 | Hall et al. | Jan 2012 | A1 |
20120042126 | Krick et al. | Feb 2012 | A1 |
20120239857 | Jibbe | Sep 2012 | A1 |
20130019047 | Podvalny et al. | Jan 2013 | A1 |
20130046934 | Nychka et al. | Feb 2013 | A1 |
20130086417 | Sivaramakrishnan et al. | Apr 2013 | A1 |
20130097369 | Talagala et al. | Apr 2013 | A1 |
20130212321 | Talagala et al. | Aug 2013 | A1 |
20130238874 | Avudaiyappan | Sep 2013 | A1 |
20130304991 | Boettcher et al. | Nov 2013 | A1 |
20130311759 | Abdallah et al. | Nov 2013 | A1 |
20130332660 | Talagala | Dec 2013 | A1 |
20130346699 | Walker | Dec 2013 | A1 |
20140032844 | Avudaiyappan et al. | Jan 2014 | A1 |
20140032845 | Avudaiyappan et al. | Jan 2014 | A1 |
20140032856 | Avudaiyappan et al. | Jan 2014 | A1 |
20140075168 | Abdallah | Mar 2014 | A1 |
20140108730 | Avudaiyappan et al. | Apr 2014 | A1 |
20140156947 | Avudaiyappan | Jun 2014 | A1 |
20140281242 | Abdallah et al. | Sep 2014 | A1 |
20140365736 | Simionescu | Dec 2014 | A1 |
20160041908 | Avudaiyappan et al. | Feb 2016 | A1 |
20160041913 | Avudaiyappan et al. | Feb 2016 | A1 |
20160041930 | Avudaiyappan | Feb 2016 | A1 |
20160048469 | Waugh | Feb 2016 | A1 |
Number | Date | Country |
---|---|---|
1305150 | Jul 2001 | CN |
0596636 | May 1994 | EP |
0706133 | Apr 1996 | EP |
2343270 | May 2000 | GB |
200707284 | Mar 1995 | TW |
539996 | Jul 2003 | TW |
200401187 | Jan 2004 | TW |
591530 | Jun 2004 | TW |
I233545 | Jun 2005 | TW |
I281121 | May 2007 | TW |
0125921 | Apr 2001 | WO |
Entry |
---|
Barham, et al., “Xen and the Art of Virtualization,” Proceedings of the ACM Symposium on Operating Systems Principles, XP002298786, Oct. 2003, pp. 164-177. |
Cooperman, “Cache Basics,” Winter 2003, downloaded from http://www.ccs.neu.edu/course/com3200/parent/NOTES/cache-basics.html on Sep. 24, 2015, 3 pages. (no publication month available). |
Garmany, J., “The Power of Indexing: Oracle Tips by Burleson Consulting,” Burleson Enterprises, Inc., archived on Mar. 9, 2009, retrieved Sep. 17, 2015 via Internet: web.archive.org/web/20090309201136/http://dba-oracle.com/t_indexing_power.htm, 7 pages. |
Jacobson, et al., “Path-based Next Trace Prediction,” MICRO 30—Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 1-3, 1997, IEEE Computer Society, Washington, D.C., 1997, pp. 14-23. |
Nanda, et al., “The Misprediction Recovery Cache,” International Journal of Parallel Programming—Special issue: MICRO-29, 29th annual IEEE/ACM international symposium on microarchitecture, Plenum Press, New York, NY, Aug. 1998, vol. 26 (4), pp. 383-415. |
Non-Final Office Action from U.S. Appl. No. 13/649,532, dated Apr. 7, 2015, 16 pages. |
Non-Final Office Action from U.S. Appl. No. 15/003,486, dated Apr. 21, 2017, 8 pages. |
Notice of Allowance from U.S. Appl. No. 13/649,532, dated Feb. 10, 2017, 13 pages. |
Notice of Allowance from U.S. Appl. No. 13/649,532, dated Feb. 29, 2016, 15 pages. |
Notice of Allowance from U.S. Appl. No. 13/649,532, dated May 18, 2016, 9 pages. |
Notice of Allowance from U.S. Appl. No. 13/649,532, dated Oct. 22, 2015, 13 pages. |
Notice of Allowance from U.S. Appl. No. 13/649,532, dated Sep. 21, 2016, 7 pages. |
Notice of Allowance from U.S. Appl. No. 15/003,486, dated Aug. 21, 2017, 33 pages. |
Rotenberg, et al., “Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching,” MICRO 29—Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, IEEE Computer Society, Apr. 11, 1996, 48 pages. |
Wallace, et al., “Multiple Branch and Block Prediction,” Third International symposium on High-Performance Computer Architecture, IEEE, Feb. 1997, pp. 94-103. |
Ye, et al., “A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, The Institute of Electronics, Information and Communication Engineers, Dec. 1, 2011, vol. E94-A (12), pp. 2639-2648. |
Yeh, et al., “Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache,” ICS 93, Proceedings of the 7th International Conference on Supercomputing, ACM, New York, NY, Jul. 19-23, 1993, pp. 57-76. |
Number | Date | Country | |
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20180060243 A1 | Mar 2018 | US |
Number | Date | Country | |
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Parent | 15003486 | Jan 2016 | US |
Child | 15806178 | US | |
Parent | 13649532 | Oct 2012 | US |
Child | 15003486 | US |