Patent Application
20100332177
(A) Field of the Invention
The present invention is related to a test access control apparatus and method for a stacked chip device.
(B) Description of the Related Art
Three-dimensional (3D) integration or wafer-to-wafer or chip-to-chip bonding technology has been considered the most promising solution to extend the life of Moore's law in semiconductor manufacturing technology. However, the stacked dies employed in such technologies will face the severe problem of exponential decay in quality if the currently employed post-bond testing technique is not changed.
Through-silicon via (TSV) is the latest in a progression of technologies for stacking silicon devices in 3D arrangements. Placing and wiring devices in 3D promises higher clock rates, lower power dissipation, and higher integration density. 3D TSV technology will be adopted in many applications because it solves issues related to electrical performance, memory latency, power, and noise on and off the chip. For some applications, a high-bandwidth memory interface to the logic has been the main driver for the development of TSV technology. However, the available TSV for 3D-IC testing is highly related to its overall test cost.
Expectations for the technology are running high, but the integration of the TSV test with the current memory test and logic test forms a barrier to using the technology. Therefore, there is a need for an architecture and a method that can efficiently perform the above-mentioned integrated testing.
The present invention provides a test access control apparatus and method for stacked chip devices that can perform System On Chip (SOC) test and TSV verification in pre-bond and post-bond testing stages. Therefore, the yield of the stacked chip devices can be better assured.
In accordance with an embodiment of the present invention, a test access control apparatus for testing a stacked chip device includes a test access mechanism (TAM) buses and an extended IEEE 1149.1 Test Access Port (TAP) Controller coupled to the TAM buses. The TAM buses can support related controls of a memory built-in-self-test (BIST) circuit for memory known-good-die (KGD) test, scan chains for logic known-good-die test, and TSV chains for conducting a TSV test that verifies any defect appeared in vertical interconnects of the stacked chip device. The TAP Controller is configured to control the process for various KGD tests before chips can be stacked and also includes vertical interconnect verification after chips are stacked. Several explanatory connections and configurations of test access control apparatus in 3D-IC are also presented.
In accordance with an embodiment of the present invention, a test access control method includes steps of performing known-good-die (KGD) test before chip stacking; bonding chips layer by layer with TSVs or vertical interconnects; and performing optional KGD test after chips are stacked.
The present invention will be explained with the appended drawings to clearly disclose the technical characteristics of the present invention.
The TAP Controller 12 include a MTAP 31 which is a finite state machine, an Instruction Register (IR) 32, an IR decoder 33, a bypass register (BYR) 34, a Core Identity Register (CIR) 35, a TAM Bus Register (TBR) 36, a single-cascade register (SCR) 37, a bypass flag register (BFR) 38, a MBIST start register (MSR) 39. The MTAP 31 receives a TCK signal, a TRST signal, and a TMS signal. TCK represents the test clock and TRST is the test reset signal. TMS controls the generation of control signals of various test protocols. The inputs of the BYR 34, the CIR 35, the TBR 36, the SCR 37, the BFR 38, and the MSR 39 receive Dn_TDI or TDI signal, and the outputs thereof are connected to a multiplexer 40. Data for test configuration are transmitted through TDI or Dn_TDI. The IR 32 receives TDI and stores the data for test configuration. The input of IR decoder 33 receives the data stored in IR 32. The output of the IR decoder 33 is connected to a WSP (Wrapper Serial Port) interpreter 50 and the multiplexer 40. The output of the WSP interpreter 50 is connected to a cascade_WIR_chain 44. The output of the WSP interpreter 50 is coupled to a cascade_WIR_Chain 44. Multiplexers 41, 42 and 43 output Up_TDI, Dn_TDO and TDO signals. The TSV chains 23 include upper TSV chains 71 and lower TSV chains 72 for testing vertical interconnects in the upper chip layer and the lower chip layer.
The memory BIST circuit 21, the TSV chains 23 and the scan chains 22 in parallel receive a Dn_TAMin or TAMin signal for test patterns application, and their outputs are connected to a multiplexer 45 which further receives a TBR signal. The Dn_TAMin signal represents the inputs for test pattern from a lower chip layer of a stacked chip device and is transmitted to a bypass unit named TAM Bypass unit (TBY) 48 that is configured to control whether the KGD test in current layer is bypassed. A multiplexer 46 receives the output signals from the TBY 48 and the multiplexer 45 and BFR signal, and the output of the multiplexer 46 is connected to Up_TAMin which transmits the test pattern for an upper chip layer of the stacked chip device. Moreover, a multiplexer 47 is connected to the output of the multiplexer 46 and the SCR signal, and outputs of the multiplexer 47 are connected to Dn_TAMout or TAMout.
In brief, this invention proposes a test access control apparatus for 3D-IC. The test access port controller may use an extended JTAG/IEEE 1149.1, and for applying logic testing a test access control apparatus features IEEE 1500 Wrapper Control, hierarchical test control, at-speed test (for transition faults), functional and scan test, heterogeneous test protocols, etc. In order to save the control signal pins/TSVs, the test access port controller is further extended to support memory BIST (MBIST) in the stacked chips by adding MSR 39 in the test access port controller 12 and defining a special TAM switching. The 3D interconnect verification can be easily applied through the operations of SCR 37 and BFR 38.
The details of locating a KGD are shown in
We also propose the way to operate test access control apparatuses in different layers of 3D-IC in
Based on such proposed test scheme and TACS-3D, the yield issues of the 3D-IC can be easily mitigated by flexibly executing an SOC test before and after dies are mounted. In addition, shorter overall test time is expected due to uniform test interface and reduced test-control requirements.
By special arrangement of SOC test integration, logic or memory testing with simple test configuration and small area overhead can be flexibly executed. After KGDs are obtained, the stacked chip device can be formed by layer-by-layer mounting. Every time a new KGD is mounted on the original stacked chip, the TSV test may be performed for 3D interconnect verification between the two chip layers. If necessary, the proposed test scheme also supports an extra KGD test in every layer of the stack with neither extra test circuits nor modified test application. Therefore, the yield of the stacked chips can be better assured.
The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.
