Patent Application
20250095763
This application is based upon and claims the benefit of Japanese Patent Application No. 2023-150343, filed on Sep. 15, 2023; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a test apparatus and a test method.
A test apparatus that tests a semiconductor storage device including a memory cell may test read characteristics of the memory cell by performing write processing on the memory cell with an increasing write voltage. The test apparatus is desired to appropriately test the memory cell.
In general, according to one embodiment, there is provided a test apparatus including an interface unit and a controller. The interface unit acquires a read characteristic indicating a relationship between a read voltage of a memory cell and a logarithm of a cell current. The memory cell is subject to write processing in which a write operation and a verification operation are repeated with increasing write voltage. The controller obtains a threshold voltage of the memory cell by performing first processing on the read characteristic. The first processing is processing of, when a subthreshold region in the read characteristic is defined as a first region, focusing on a second region being a region of a read voltage larger than a maximum read voltage of the first region. The controller calculates a first slope in a first threshold characteristic indicating a relationship between a write voltage and the threshold voltage in the write processing, based on the threshold voltage obtained in the first processing. The controller subtracts the first slope from a slope in a predetermined threshold characteristic to obtain a first slope degradation component.
Exemplary embodiments of a test apparatus will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.
The test apparatus according to the embodiment is a test apparatus for testing a semiconductor storage device including a memory cell, and performs write processing on the memory cell with an increasing write voltage to test a read characteristic of the memory cell, with improved configurations for appropriately testing the memory cell.
A test apparatus 300 can be configured as illustrated in
The test apparatus 300 can be connected to a semiconductor storage device 1 via a communication medium 400. The communication medium 400 may include a wired communication channel such as a coaxial cable or a wireless communication channel. When connected to the semiconductor storage device 1, the test apparatus 300 can supply a test pattern to the semiconductor storage device 1 via the communication medium 400 to test the semiconductor storage device 1.
The test apparatus 300 includes an interface (I/F) unit 301, an input unit 305, a storage unit 303, a display unit 304, and a controller 302.
The interface unit 301 includes an external connection terminal 301a. The external connection terminal 301a can be connected to the semiconductor storage device 1 via the communication medium 400. The interface unit 301 performs an interface operation between the semiconductor storage device 1 and the controller 302 under the control of the controller 302.
The input unit 305 can receive an instruction from the user. For example, the input unit 305 may receive a test execution instruction related to a test of a memory cell. Having received an instruction from the user, the input unit 305 supplies the instruction to the controller 302. The input unit 305 may include a keyboard, a mouse, a touch panel, and the like.
The storage unit 303 stores predetermined information. The predetermined information includes information related to a test of the memory cell. The storage unit 303 may store test data 303a. The storage unit 303 may be a non-volatile storage medium such as a hard disk.
The display unit 304 includes a display screen 304a, and can display predetermined information on a display screen 304a. For example, the display unit 304 may display information related to a test of a memory cell (for example, test conditions, test results, and the like) on the display screen 304a.
The controller 302 integrally controls each unit of the test apparatus 300. The controller 302 may perform predetermined control in accordance with an instruction from the user, or may autonomously perform predetermined control in accordance with establishment of a predetermined condition.
For example, the controller 302 generates a write command in response to an instruction from the user via the input unit 305 or autonomously in accordance with establishment of a predetermined condition, and reads the test data 303a from the storage unit 303. The controller 302 supplies the write command and the test data 303a to the interface unit 301. The write command includes an address of a memory cell to be tested. The interface unit 301 converts the write command and the test data 303a into a format compatible with the communication medium 400 and supplies the converted command and data to the semiconductor storage device 1 via the communication medium 400.
The semiconductor storage device 1 includes multiple memory cells. Having received the write command and the test data, the semiconductor storage device 1 can perform test data write processing onto the memory cell addressed by the write command. The write processing may be performed by an Incremental Step Pulse Programming (ISPP) method. In the write processing, a write operation and a verification operation are repeated with an increasing write voltage. When the verification operation is successful to complete the write processing of the test data to the memory cell, the semiconductor storage device 1 transmits a write completion notification to the interface unit 301 via the communication medium 400.
Having received the write completion notification, the interface unit 301 supplies the write completion notification to the controller 302.
Thereafter, the controller 302 generates a read command in response to an instruction from the user via the input unit 305 or autonomously in accordance with establishment of a predetermined condition. The read command includes an address of a memory cell to be tested. The controller 302 may generate a read command including the address of the memory cell that has undergone write processing. The controller 302 supplies the read command to the interface unit 301.
Having received the read command, the semiconductor storage device 1 can perform read processing on the memory cell addressed by the read command. The read processing detects the cell current while sweeping the read voltage. Having completed the read processing on the memory cell, the semiconductor storage device 1 generates read characteristic information 303b. The read characteristic information 303b indicates a read characteristic. The read characteristic indicates a relationship between the read voltage and the logarithm (common logarithm) of the cell current. The semiconductor storage device 1 transmits the read characteristic information 303b to the interface unit 301 via the communication medium 400.
The interface unit 301 receives the read characteristic information 303b. Having acquired the read characteristic information 303b, the interface unit 301 supplies the read characteristic information 303b to the controller 302. The controller 302 stores the read characteristic information 303b in the storage unit 303.
The controller 302 performs processing PC1 on the read characteristic indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. The processing PC1 is processing of obtaining the threshold voltage focusing on an overdrive region in the read characteristic. The processing PC1 includes processing of obtaining a voltage corresponding to a tangent near a boundary between the subthreshold region and the overdrive region in the read characteristic as the threshold voltage. The processing PC1 may include a process by a GM-MAX method (an extrapolation method using maximum transconductance).
In the present specification, the subthreshold region refers to a WL voltage region that linearly changes (that is, a region with a waveform of a straight line having a substantially constant inclination) in a chart in which a voltage of the word line WL (WL voltage: Vwl) is used as a horizontal axis and a common logarithm of the current flowing through the memory cell (cell current: Icell), that is, log10 (Icell) is plotted on a vertical axis. The overdrive region refers to a region having a WL voltage higher than the maximum WL voltage of the subthreshold region. Hereinafter, “logarithm” refers to a common logarithm.
The controller 302 generates threshold characteristic information 303c based on the threshold voltage obtained in the processing PC1. The threshold characteristic information 303c indicates a threshold characteristic TP1. The threshold characteristic TP1 indicates a relationship between the write voltage and the threshold voltage in the write processing. The controller 302 may obtain the threshold characteristic TP1 by performing plotting on a plane having the threshold voltage obtained in the processing PC1 and the write voltage during the write processing as coordinate axes so as to generate the threshold characteristic information 303c.
Here, an average rate of change of the threshold voltage with respect to the write voltage is referred to as a slope. A phenomenon in which the average rate of change of the threshold voltage with respect to the write voltage decays from a predetermined rate of change will be referred to as slope degradation. The predetermined rate of change may be a theoretically obtainable ideal rate of change, and is 1, for example.
The controller 302 calculates a slope SL1 in the threshold characteristic TP1. The slope SL1 indicates an average rate of change of the threshold voltage with respect to the write voltage in the threshold characteristic TP1. The controller 302 generates slope degradation component information 303d in accordance with the slope SL1. The slope degradation component information 303d indicates a slope degradation component ΔDS1. The controller 302 may obtain a threshold characteristic TP0 based on an ideal condition such as an ideal rate of change and may calculate a slope SL0 in a threshold characteristic TP0. The controller 302 may subtract the slope SL1 from the slope SL0 to obtain the slope degradation component ΔDS1. The controller 302 stores the slope degradation component information 303d in the storage unit 303.
The controller 302 performs processing PC2 on the read characteristic indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. The processing PC2 is processing of obtaining the threshold voltage focusing on the subthreshold region in the read characteristic. The processing PC2 includes processing of obtaining a voltage corresponding to an approximate straight line of the subthreshold region in the read characteristic, as the threshold voltage.
The controller 302 generates threshold characteristic information 303e based on the threshold voltage obtained by the processing PC2. The threshold characteristic information 303e indicates a threshold characteristic TP2. The threshold characteristic TP2 indicates a relationship between the write voltage and the threshold voltage in the write processing. The controller 302 may obtain the threshold characteristic TP2 by plotting the threshold voltage obtained in the processing PC2 and the write voltage during the write processing so as to generate the threshold characteristic information 303e.
The controller 302 calculates a slope SL2 in the threshold characteristic TP2. The slope SL2 indicates the inclination of the change in the threshold voltage with respect to the write voltage. The controller 302 generates slope degradation component information 303f in accordance with the slope SL2. The slope degradation component information 303f indicates a slope degradation component ΔDS2. The controller 302 may subtract the slope SL2 from the slope SL1 to obtain the slope degradation component ΔDS2. The controller 302 stores the slope degradation component information 303f in the storage unit 303.
The controller 302 reads the slope degradation component information 303d and the slope degradation component information 303f individually from the storage unit 303. The controller 302 notifies the user of the slope degradation component ΔDS1 corresponding to the slope degradation component information 303d and the slope degradation component ΔDS2 corresponding to the slope degradation component information 303f. The controller 302 may display the slope degradation component ΔDS1 and the slope degradation component ΔDS2 on the display screen 304a of the display unit 304. The controller 302 may display the slope degradation component information 303d and the slope degradation component information 303f on the display screen 304a of the display unit 304 in a mode of being able to recognize the magnitude relationship between the slope degradation component ΔDS1 and the slope degradation component ΔDS2. This makes it possible for the test apparatus 300 to notify the user of the slope degradation component ΔDS1 and the slope degradation component ΔDS2. By comparing the slope degradation component ΔDS1 and the slope degradation component ΔDS2 when there is a failure in the memory cell, the cause of the failure can be predicted to some extent.
The slope degradation component ΔDS1 indicates degradation due to a decrease in carrier capture efficiency of the memory cell. The decrease in carrier capture efficiency is a phenomenon in which charges are less likely to be accumulated in a charge accumulation film together with thinning of a block insulating film of the memory cell in response to the demand for miniaturization. The decrease in the carrier capture efficiency is likely to increase the write voltage necessary for successful verification in the write processing of the memory cell, leading to a possibility of earlier degradation of the memory cell.
The slope degradation component ΔDS2 indicates degradation due to a fringe effect of the memory cell. The fringe effect is a phenomenon in which the shortened distance between memory cells in response to a demand for miniaturization causes the cell current to flow at a read voltage lower than an appropriate read voltage. Occurrence of the fringe effect tends to decrease the read voltage in the read processing of the memory cell, making it difficult to achieve a proper sense amplifier operation.
For example, in a case where the slope degradation component ΔDS1 is larger than the slope degradation component ΔDS2 when there is a failure in the memory cell, a main cause of the failure can be predicted to be a decrease in carrier capture efficiency of the memory cell. This makes it possible to prompt the user to take measures against a decrease in carrier capture efficiency of the memory cell.
In another case where the slope degradation component ΔDS2 is larger than the slope degradation component ΔDS1 when there is a failure in the memory cell, the main cause of the failure can be predicted to be the fringe effect of the memory cell. This makes it possible to prompt the user to take measures against the fringe effect of the memory cell.
Next, the semiconductor storage device 1 to be tested will be described. As illustrated in
As illustrated in
In the example of
The select gate SGD is divided in the Y direction by a division film SHE, for example. The example of
An example of the substrate SUB is a silicon substrate. The select gate SGS, the word line WL, and the select gate SGD are metal layers containing tungsten (W), for example. The insulating layer 7 and the interlayer insulating film 81 are insulators containing silicon oxide, for example.
The semiconductor storage device 1 further includes multiple columnar bodies 4. The columnar body 4 penetrates the select gate SGS, the word line WL, and the select gate SGD and extends in the Z direction which is a stacking direction of these components. The semiconductor storage device 1 further includes multiple bit lines BL provided above the select gate SGD.
Each of the columnar bodies 4 is electrically connected to the bit line BL via a contact plug 31. For example, one of the columnar bodies 4 sharing the select gate SGD0 and one of the columnar bodies 4 sharing the select gate SGD1 are electrically connected to one bit line BL.
In
In the semiconductor storage device 1, the select gate SGD, the word line WL, and the select gate SGS are each formed with a conductive layer. On the +Z side of the source line SL, there is provided a stacked body SST in which conductive layers and the insulating layers 7 are alternately stacked. The stacked body SST is penetrated by the columnar bodies 4 to form an array of three-dimensional memory cells (memory cell array).
That is, the semiconductor storage device 1 has a configuration in which portions where the word line WL and the columnar body 4 intersect function as memory cells, and includes a memory cell array 2 having multiple memory cells three-dimensionally arranged. In addition, a portion where the select gate SGS intersects with the columnar body 4 functions as a source-side select gate, while a portion where the select gates SGD0 and SGD1 intersect with the columnar body 4 functions as a drain-side select gate. With an increased number of stacked word lines WL in the stacked body SST, the semiconductor storage device 1 can increase the storage capacity without using a finer patterning technology.
As illustrated in
The WL drive circuit 110 is a circuit that controls a voltage applied to the word line WL, and the SGS drive circuit 120 is a circuit that controls a voltage applied to the select gate SGS. The SGD drive circuit 130 is a circuit that controls a voltage applied to the select gate SGD, and the SL drive circuit 140 is a circuit that controls a voltage applied to the source line SL. The sense amplifier circuit 150 is a circuit that controls a voltage applied to the bit line BL and is a circuit that determines data read according to a signal from a selected memory cell.
The peripheral circuit 100 controls the operation of the semiconductor storage device 1 based on an instruction input from the outside (for example, a memory controller of a memory system to which the semiconductor storage device 1 is applied) via the interface 200.
Next, a circuit configuration of the memory cell array 2 will be described with reference to
The memory cell array 2 includes multiple blocks BLK each of which is a set of multiple memory cell transistors MT. Hereinafter, the memory cell transistor MT is simply referred to as a memory cell MT.
Each block BLK includes multiple string units SU0, SU1, SU2, and SU3 each of which is a set of memory cells MT associated with the word line WL and the bit line BL. Each of the string units SU0 to SU3 includes multiple memory strings MST having the memory cells MT connected in series. Note that the number of memory strings MST in the string units SU0 to SU3 may be any number.
The multiple string units SU0, SU1, SU2, and SU3 correspond to the multiple select gates SGD0, SGD1, SGD2, and SGD3, respectively, share the select gate SGS, and function as multiple units of drive in the block BLK. Each string unit SU can be driven by its corresponding select gate SGD and select gate SGS. In addition, each of the string units SU includes multiple memory strings MST.
Each memory string MST includes, for example, ten memory cells MT (MT0 to MT9) and selection transistors DGT and SGT. The memory cell MT includes a control gate and a charge accumulation film, and performs nonvolatile retention and storage of data. The ten memory cells MT are connected in series between the source of the selection transistor DGT and the drain of the selection transistor SGT. The number of memory cell MT in the memory string MST is not limited to ten.
Gates of the selection transistors DGT in the string units SU0 to SU3 are connected to select gates SGD0 to SGD3, respectively. On the other hand, the gate of the selection transistor SGT in each string unit SU is commonly connected to the select gate SGS, for example.
The drains of the selection transistors DGT of the individual memory strings MST in the individual string units SU are connected to different bit lines BL0 to BLk (k is any integer of two or more). In addition, the bit lines BL0 to BLk commonly connect one memory string MST in each string unit SU among the multiple blocks BLK. Furthermore, the source of each selection transistor SGT is commonly connected to the source line SL.
That is, the string unit SU is a set of memory strings MST connected to different bit lines BL0 to BLk and connected to the identical select gate SGD. Each block BLK is a set of multiple string units SU0 to SU3 sharing the word line WL. The memory cell array 2 is a set of multiple blocks BLK sharing the bit lines BL0 to BLk.
The bit lines BL0 to BLk (denoted as BL when each bit line is not distinguished from each other) are connected to the memory string MST. When the select gate DGT is turned on, a channel region of each memory cell MT in the memory string MST can be electrically connected to the bit line BL. Each bit line BL is connected to a corresponding sense amplifier SA among the multiple sense amplifiers SAO to SAp in the sense amplifier circuit 150.
Word lines WL0 to WL9 (denoted as WL when each word line is not distinguished from each other) commonly connect the control gates of the memory cells MT among the individual memory strings MST in the individual string units SU in the physical block BLK. That is, the control gates of the memory cell MT in a same row in each string unit SU in the physical block BLK are connected to an identical word line WL. That is, the string unit SU of the physical block BLK includes multiple memory cell groups MCG corresponding to multiple word lines WL, and each memory cell group MCG includes (k+1) memory cells MT connected to the identical word line WL.
When each memory cell MT is configured to be able to retain a 1-bit value (when operating in a single-level cell (SLC) mode), (p+1) memory cells MT (that is, the memory group MCG) connected to the identical word line WL are handled as one physical page, and data write processing and data read processing are performed for each physical page.
For example, in a single-level cell (SLC) mode in which each memory cell MT stores a 1-bit value, data equivalent to one physical page is retained in each word line WL. Regarding the threshold distribution of the memory cells MT in the memory cell array 2, as illustrated in
Each memory cell MT may be configured to be able to retain multiple bit values. When each memory cell MT can store a value of n (n≥2) bits, the storage capacity per word line WL is equal to the size of n physical pages. That is, each memory cell group MCG is handled as n physical pages.
In a multi-level cell (MLC) mode in which each memory cell MT stores a 2-bit value, data of two physical pages is retained in each word line WL. Regarding the threshold distribution of the memory cells MT in the memory cell array 2, as illustrated in
In a triple-level cell (TLC) mode in which each memory cell MT stores a 3-bit value, data of three physical pages is retained in each word line WL. Regarding the threshold distribution of the memory cells MT in the memory cell array 2, as illustrated in
In a quad-level cell (QLC) mode in which each memory cell MT stores a 4-bit value, data of four physical pages is retained in each word line WL. Regarding the threshold distribution of the memory cells MT in the memory cell array 2, as illustrated in
In a penta-level cell (PLC) mode in which each memory cell MT stores a 5-bit value, data of five physical pages is retained in each word line WL. Regarding the threshold distribution of the memory cells MT in the memory cell array 2, as illustrated in
Next, a cross-sectional configuration of the memory cell array 2 will be described with reference to
In the semiconductor storage device 1, a conductive layer 3 is disposed on the +Z side of the substrate SUB via the interlayer insulating film 81. The conductive layer 3 can be formed with a material containing a semiconductor (for example, silicon) containing impurities as a main component or a material containing an electrical conductor (for example, a metal such as tungsten) as a main component. The conductive layer 3 extends in a plate shape in X-Y directions and functions as the source line SL (refer to
The stacked body SST has a structure including a stack of multiple stacked bodies SST1 and SST2.
Each columnar body 4 has a tier 4a, a joint portion 4b, a tier 4c, and a cap layer 4d sequentially stacked on the +Z side of the conductive layer 3. The stacked body SST includes the stacked body SST1, a joint layer JL, and the stacked body SST2 sequentially stacked on the +Z side of the conductive layer 3.
Each of the stacked bodies SST1 and SST2 has a configuration in which the conductive layers 6 functioning as word lines WL and the like are stacked via the insulating layers 7. The tier 4a extends in the Z direction and penetrates the stacked body SST1. The joint portion 4b has a Z position corresponding to the joint layer JL. The joint layer JL can be formed with a material containing an oxide (for example, silicon oxide) as a main component. The tier 4c extends in the Z direction and penetrates the stacked body SST2. The +Z-side end portion of the tier 4a is coupled to the tier 4c via the joint portion 4b. The cap layer 4d extends in a plate shape in the X-Y directions and covers the +Z-side end of the tier 4c. The cap layer 4d can be formed with, for example, a material containing a semiconductor containing impurities (for example, polysilicon) as a main component. The conductive layer 9 is disposed on the +Z side of the stacked body SST2 via interlayer insulating films 82 and 83. The conductive layer 9 can be formed with a material containing an electrical conductor (for example, a metal such as tungsten) as a main component. The conductive layer 9 extends as a line in the Y direction and functions as the bit line BL (refer to
As illustrated in
The core member 41 has a substantially columnar pillar shape disposed in the vicinity of the central axis CA of the columnar body 40 and extending along the central axis CA of the columnar body 40. The core member 41 can be formed with a material containing an insulator (for example, a semiconductor oxide such as silicon oxide) as a main component.
The semiconductor film 42 is disposed so as to surround the core member 41 from the outside, and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40. The semiconductor film 42 further covers the −Z-side end of the core member 41 and is connected to a conductive film 3. The semiconductor film 42 can be formed with a material containing a semiconductor (for example, polysilicon) substantially containing no impurities as a main component.
The insulating film 43a is disposed so as to surround the semiconductor film 42 from the outside and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40. The insulating film 43a can be formed with a material containing an oxide (for example, silicon oxide or silicon oxynitride) as a main component.
The charge accumulation film 43b includes a substantially cylindrical shape that is disposed so as to surround the insulating film 43a from the outside and extends along the central axis CA of the columnar body 40. The charge accumulation film 43b can be formed with a material containing a nitride (for example, silicon nitride) as a main component.
The insulating film 43c is disposed so as to surround the charge accumulation film 43b from the outside, and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40. The insulating film 43c can be formed with a material containing an oxide (for example, a silicon oxide, a metal oxide, or a stack of these) as a main component. This configuration can form an ONO three-layer structure in which the charge accumulation film 43b is sandwiched between the pair of insulating films 43a and 43c.
The insulating film 8 covers the insulating film 43c from the outside in the X-Y directions, extends to cover the +Z-side surface of the conductive layer 6, the surface on the columnar body 40 side, and the −Z-side surface of the conductive layer 6, and forms a substantially hollow disc shape having an axis in the Z direction. The insulating film 8 can be formed with an insulator such as aluminum oxide. Hereinafter, illustration and description of the insulating film 8 may be omitted for simplification.
The semiconductor film 42 of the columnar body 40 is connected, on the −Z side, to the conductive film 3 as the source line SL, while being connected, on the +Z side, to the conductive layer functioning as the bit line BL via the contact plug 31. That is, the semiconductor film 42 of the columnar body 40 includes a channel region (active region) in the memory string MST.
In each of the stacked bodies SST1 and SST2 illustrated in
In the stacked body SST1, at least the conductive layer 6 closest to the −Z side among the multiple conductive layers 6 disposed apart from each other in the Z direction functions as the select gate SGS, and the other conductive layers 6 function as word lines WL0 to WL4.
The selection transistor SGT is formed at a position where the conductive layer 6 of the select gate SGS intersects the semiconductor film 42 and the charge accumulation film 43b. The memory cell MT0 is formed at a position where the conductive layer 6 of the word line WL0 intersects the semiconductor film 42 and the charge accumulation film 43b. The memory cell MT1 is formed at a position where the conductive layer 6 of the word line WL1 intersects the semiconductor film 42 and the charge accumulation film 43b. The memory cell MT2 is formed at a position where the conductive layer 6 of the word line WL2 intersects the semiconductor film 42 and the charge accumulation film 43b. The memory cell MT3 is formed at a position where the conductive layer 6 of the word line WL3 intersects the semiconductor film 42 and the charge accumulation film 43b. The memory cell MT4 is formed at a position where the conductive layer 6 of the word line WL4 intersects the semiconductor film 42 and the charge accumulation film 43b. Incidentally, the tier 4a may partially omit the charge accumulation film 43b and the insulating film 43c at a position intersecting the conductive layer 6 of the select gate SGS.
In the stacked body SST2 stacked on the stacked body SST1 via the joint layer JL, at least the conductive layer 6 closest to the +Z side among the multiple conductive layers 6 disposed apart from each other in the Z direction functions as the select gate SGD, and the other conductive layers 6 function as the word lines WL5 to WL9.
The memory cell MT5 is formed at a position where the conductive layer 6 of the word line WL5 intersects the semiconductor film 42 and the charge accumulation film 43b. The memory cell MT6 is formed at a position where the conductive layer 6 of the word line WL6 intersects the semiconductor film 42 and the charge accumulation film 43b. The memory cell MT7 is formed at a position where the conductive layer 6 of the word line WL7 intersects the semiconductor film 42 and the charge accumulation film 43b. The memory cell MT8 is formed at a position where the conductive layer 6 of the word line WL8 intersects the semiconductor film 42 and the charge accumulation film 43b. A memory cell MT9 is formed at a position where the conductive layer 6 of the word line WL9 intersects the semiconductor film 42 and the charge accumulation film 43b. The selection transistor DGT is formed at a position where the conductive layer 6 of the select gate SGD intersects the semiconductor film 42 and the charge accumulation film 43b. Incidentally, the tier 4c may partially omit the charge accumulation film 43b and the insulating film 43c at a position intersecting the conductive layer 6 of the select gate SGD.
In the processing of writing information to the memory cell MT, a write voltage is applied to the conductive layer 6 of the selected word line WL, a transfer voltage is applied to the conductive layer 6 of the unselected word line WL, and a reference voltage is applied to the semiconductor film 42. The write voltage has an electric potential (for example, 20 V) for injecting charges (electrons) of the semiconductor film 42 into the charge accumulation film 43b. The transfer voltage has an electric potential (for example, 10 V) between the write voltage and the reference voltage. The reference voltage has an electric potential to be a reference (for example, 0 V). With this configuration, charges are accumulated in the charge accumulation film 43b of the selected memory cell MT at a position where the conductive layer 6 of the selected word line WL and the semiconductor film 42 intersect each other, and information is written in the selected memory cell MT.
In the process of erasing information from the memory cell MT, a reference voltage is applied to the conductive layer 6 of each word line WL, an erase voltage is applied to the semiconductor film 42, and an intermediate voltage between the two voltages is applied to the select gates SGS and SGD. The erase voltage has an electric potential (for example, 20 V) for injecting opposite charges (holes) of the semiconductor film 42 into the charge accumulation film 43b. The reference voltage has an electric potential to be a reference (for example, 0 V). The intermediate voltage has an electric potential (for example, 5 V) between the erase processing and the reference voltage. By such control, electron-hole pairs are generated by Gate Induced Drain Leakage (GIDL) near the drains of the selection transistors SGT and DGT, and opposite charges (holes) are injected from the semiconductor film 42 into the charge accumulation film 43b. This operation erases the charge accumulated in the charge accumulation film 43b so as to be able to erase the information in the memory cell MT.
Next, the configuration and operation of the controller 302 in the test apparatus 300 will be described.
As illustrated in
The controller 302 functionally includes a write processing unit 3021, a read processing unit 3022, an acquisition unit 3023, a threshold calculation unit 3024, a slope calculation unit 3025, a degradation component calculation unit 3026, a threshold calculation unit 3027, a slope calculation unit 3028, a degradation component calculation unit 3029, and a notification unit 3030 illustrated in
In the controller 302, each unit illustrated in
The write processing unit 3021 generates a write command in response to an instruction from the user via the input unit 305 or autonomously in accordance with establishment of a predetermined condition, and reads the test data 303a from the storage unit 303. The write processing unit 3021 supplies the write command and the test data 303a to the interface unit 301. The write command includes an address of a memory cell to be tested. The interface unit 301 supplies the write command and the test data 303a to the semiconductor storage device 1 via the communication medium 400.
Having received the write command and the test data, the semiconductor storage device 1 can perform test data write processing onto the memory cell addressed by the write command. In the write processing, as illustrated in
Having received the write completion notification, the interface unit 301 supplies the write completion notification to the controller 302.
Thereafter, the read processing unit 3022 illustrated in
Having received the read command, the semiconductor storage device 1 can perform the read processing on the memory cell addressed by the read command. The read processing detects the cell current for each memory cell while sweeping the read voltage, as illustrated in
Having completed the read processing on the memory cell, the semiconductor storage device 1 generates read characteristic information. The read characteristic information indicates a read characteristic. The read characteristic indicates a relationship between the read voltage and the logarithm of the cell current. The semiconductor storage device 1 generates read characteristic information indicating read characteristics Pf1 to Pf3, as illustrated in
Each of the read characteristics Pf1 to Pf3 has a subthreshold region and an overdrive region. The read characteristic Pf is characterized in that, in the subthreshold region, the logarithm of the cell current linearly increases steeply together with an increase in the read voltage. The read characteristic Pf is characterized in that, in the overdrive region, the logarithm of the cell current increases nonlinearly and gradually together with an increase in the read voltage. In each of the read characteristics Pf1 to Pf3, the inclination of the tangent for cell current characteristic that is not logarithmically-converted tends to be maximized near the boundary between the subthreshold region and the overdrive region.
The semiconductor storage device 1 transmits the read characteristic information to the interface unit 301 via the communication medium 400.
The interface unit 301 receives the read characteristic information. Having acquired the read characteristic information 303b, the interface unit 301 supplies the read characteristic information 303b to the acquisition unit 3023 illustrated in
The threshold calculation unit 3024 performs the processing PC1 on the read characteristic indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. The processing PC1 is processing of obtaining the threshold voltage focusing on an overdrive region in the read characteristic. The processing PC1 includes processing of obtaining a voltage corresponding to a tangent near a boundary between the subthreshold region and the overdrive region in the read characteristic as the threshold voltage. The processing PC1 may include processing using a GM-MAX method.
For example, regarding the graph of the read characteristic Pf1 for cell current that is not logarithmically-converted illustrated in
Regarding the graph of the read characteristic Pf2, the threshold calculation unit 3024 calculates the inclination of the tangent for cell current characteristic that is not logarithmically-converted corresponding to the read voltage value while changing the read voltage value, and obtains a coordinate point CP2 including a read voltage value at which the inclination of the tangent is maximized. The threshold calculation unit 3024 obtains an intersection CX2 between a tangent TL2 of the coordinate point CP2 with respect to the graph of the read characteristic Pf2 and the horizontal axis (cell current=0). The threshold calculation unit 3024 sets the read voltage value at the intersection CX2 as a threshold voltage Vth2.
Regarding the graph of the read characteristic Pf3, the threshold calculation unit 3024 calculates the inclination of the tangent for cell current characteristic that is not logarithmically-converted corresponding to the read voltage value while changing the read voltage value, and obtains a coordinate point CP3 including a read voltage value at which the inclination of the tangent is maximized. The threshold calculation unit 3024 obtains an intersection CX3 between a tangent TL3 of the coordinate point CP3 with respect to the graph of the read characteristic Pf3 and the horizontal axis (cell current=0). The threshold calculation unit 3024 sets the read voltage value at the intersection CX3 as a threshold voltage Vth3.
As illustrated in
The threshold calculation unit 3024 illustrated in
The slope calculation unit 3025 generates the threshold characteristic information 303c based on the threshold voltage obtained in the processing PC1. The threshold characteristic information 303c indicates a threshold characteristic TP1. The threshold characteristic TP1 indicates a relationship between the write voltage and the threshold voltage in the write processing. As indicated by a dotted line of
The slope calculation unit 3025 calculates the slope SL1 in the threshold characteristic TP1. The slope SL1 indicates the inclination of the change in the threshold voltage with respect to the write voltage. The slope SL1 corresponds to the inclination of the straight line representing the threshold characteristic TP1 illustrated in
The degradation component calculation unit 3026 illustrated in
The threshold calculation unit 3027 performs the processing PC2 on the read characteristic indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. The processing PC2 is processing of obtaining the threshold voltage focusing on the subthreshold region in the read characteristic. The processing PC2 includes processing of obtaining a voltage corresponding to an approximate straight line of the subthreshold region in the read characteristic, as the threshold voltage.
For example, regarding the graph of the read characteristic Pf1 illustrated in
Regarding the graph of the read characteristic Pf2, the threshold calculation unit 3027 obtains an intersection CX12 between the subthreshold region of the read characteristic Pf2 and the horizontal line HL1 representing threshold current level (cell current=threshold current level). The threshold calculation unit 3027 sets the read voltage value at the intersection CX12 as a threshold voltage Vth12.
Regarding the graph of the read characteristic Pf3, the threshold calculation unit 3027 obtains an intersection CX13 between the subthreshold region of the read characteristic Pf3 and the horizontal line HL1 representing threshold current level (cell current=threshold current level). The threshold calculation unit 3027 sets the read voltage value at the intersection CX13 as a threshold voltage Vth13.
As illustrated in
The threshold calculation unit 3027 illustrated in
The slope calculation unit 3028 generates threshold characteristic information 303e based on the threshold voltage obtained in the processing PC2. The threshold characteristic information 303e indicates a threshold characteristic TP2. The threshold characteristic TP2 indicates a relationship between the write voltage and the threshold voltage in the write processing. As indicated by a solid line of
The slope calculation unit 3028 calculates the slope SL2 in the threshold characteristic TP2. The slope SL2 indicates the inclination of the change in the threshold voltage with respect to the write voltage. The slope SL2 corresponds to the inclination of the straight line of the threshold characteristic TP2 illustrated in
The degradation component calculation unit 3029 illustrated in
The notification unit 3030 reads the slope degradation component information 303d and the slope degradation component information 303f individually from the storage unit 303. The notification unit 3030 may display the slope degradation component ΔDS1 and the slope degradation component ΔDS2 on the display screen 304a of the display unit 304. The notification unit 3030 may display the slope degradation component information 303d and the slope degradation component information 303f on the display screen 304a of the display unit 304 in a mode of being able to recognize the magnitude relationship between the slope degradation component ΔDS1 and the slope degradation component ΔDS2. This makes it possible for the test apparatus 300 to notify the user of the slope degradation component ΔDS1 and the slope degradation component ΔDS2. By comparing the slope degradation component ΔDS1 and the slope degradation component ΔDS2 when there is a failure in the memory cell, the cause of the failure can be predicted to some extent.
For example, in a case where the slope degradation component ΔDS1 is larger than the slope degradation component ΔDS2 when there is a failure in the memory cell, a main cause of the failure can be predicted to be a decrease in carrier capture efficiency of the memory cell. This makes it possible to prompt the user to take measures against a decrease in carrier capture efficiency of the memory cell.
In another case where the slope degradation component ΔDS2 is larger than the slope degradation component ΔDS1 when there is a failure in the memory cell, the main cause of the failure can be predicted to be the fringe effect of the memory cell. This makes it possible to prompt the user to take measures against the fringe effect of the memory cell.
Next, slope degradation components will be described with reference to
However, an occurrence of slope degradation due to a problem at the time of writing would lead to an assumable case where the slope of the threshold characteristic TP1 or TP2 illustrated in
At this time, an increase in the write voltage Vpgm should also increase the electric field of the insulating film 43a and the tunnel current a result, but it is experimentally found that the crucial value ΔVth has not increased. This leads to an estimation that the electron capture efficiency has decreased to the extent of canceling the increase in the tunnel current. In other words, the write operation accompanied by slope degradation due to a problem at the time of writing has a tendency of transition in which the tunnel current increases (for example, X times), and the capturing efficiency decreases (for example, 1/X times). In this case, as illustrated in
Meanwhile, slope degradation may occur due to a problem at the time of reading. For example, in a case of reading data of a memory cell having a high threshold voltage Vth, an electric field of the word line WL to which a high read voltage is applied propagates to the semiconductor film 42 between the word lines WL, and an occurrence of a sneak (leakage) electric field to the channel back surface causes degradation of a subthreshold coefficient of the read characteristic as illustrated in
Next, operations of the test apparatus 300 will be described with reference to
In the test apparatus 300, the controller 302 controls the semiconductor storage device 1 to execute write processing (S1). The controller 302 generates a test write command and supplies the write command and the test data to the semiconductor storage device 1 via the interface unit 301 and a communication channel 400. With this configuration, write processing is performed in the semiconductor storage device 1. In the write processing, the write operation and the verification operation are repeated with an increasing write voltage. The write processing can be performed by the ISPP method.
The controller 302 controls the semiconductor storage device 1 to execute read processing, and acquires read characteristics from the semiconductor storage device 1 (S2). The controller 302 generates a read command and supplies the generated read command to the semiconductor storage device 1 via the interface unit 301 and the communication channel 400. With this configuration, read processing is performed in the semiconductor storage device 1. The read processing detects the cell current while sweeping the read voltage. As a response to the read command, the controller 302 acquires the read characteristics from the semiconductor storage device 1 via the communication channel 400 and the interface unit 301.
When S2 is completed, the processing of S3 to S5 and the processing of S6 to S7 are performed in parallel.
The controller 302 performs the processing PC1 on the read characteristics to calculate the threshold voltage of the memory cell (S3). The processing PC1 is processing of obtaining the threshold voltage focusing on an overdrive region in the read characteristic. The processing PC1 includes processing of obtaining a voltage corresponding to a tangent near a boundary between the subthreshold region and the overdrive region in the read characteristic as the threshold voltage. The processing PC1 may include processing using a GM-MAX method.
The controller 302 calculates the slope SL1 based on the threshold voltage calculated in S3 (S4). The controller 302 obtains the threshold characteristic TP1 based on the threshold voltage obtained in the processing PC1. The threshold characteristic TP1 indicates a relationship between the write voltage and the threshold voltage in the write processing. The controller 302 may obtain the threshold characteristic TP1 by performing plotting on a plane having the threshold voltage obtained in the processing PC1 and the write voltage during the write processing as coordinate axes. The controller 302 calculates the slope SL1 in the threshold characteristic TP1.
The controller 302 calculates the slope degradation component ΔDS1 based on the slope SL1 calculated in S4 (S5). The controller 302 may obtain a threshold characteristic TP0 based on an ideal condition and may calculate a slope SL0 in a threshold characteristic TP0. The controller 302 may subtract the slope SL1 from the slope SL0 to obtain the slope degradation component ΔDS1.
On the other hand, the controller 302 performs the processing PC2 on the read characteristics to calculate the threshold voltage of the memory cell (S6). The processing PC2 is processing of obtaining the threshold voltage focusing on the subthreshold region in the read characteristic. The processing PC2 includes processing of obtaining a voltage corresponding to an approximate straight line of the subthreshold region in the read characteristic, as the threshold voltage.
The controller 302 calculates the slope SL2 based on the threshold voltage calculated in S6 (S7). The controller 302 obtains the threshold characteristic TP2 based on the threshold voltage obtained by the processing PC2. The threshold characteristic TP2 indicates a relationship between the write voltage and the threshold voltage in the write processing. The controller 302 may obtain the threshold characteristic TP2 by performing plotting on a plane having the threshold voltage obtained in the processing PC2 and the write voltage during the write processing as coordinate axes. The controller 302 calculates a slope SL2 in the threshold characteristic TP2.
When both S5 and S7 are completed, the controller 302 calculates the slope degradation component ΔDS1 based on the slope SL1 calculated in S4 and the slope SL2 calculated in S7 (S8). The controller 302 may subtract the slope SL2 from the slope SL1 to obtain the slope degradation component ΔDS2.
The controller 302 notifies the user of the slope degradation component ΔDS1 and the slope degradation component ΔDS2 (S9). The controller 302 may display the slope degradation component ΔDS1 and the slope degradation component ΔDS2 on the display screen 304a of the display unit 304. The controller 302 may display the slope degradation component information 303d and the slope degradation component information 303f on the display screen 304a of the display unit 304 in a mode of being able to recognize the magnitude relationship between the slope degradation component ΔDS1 and the slope degradation component ΔDS2. This makes it possible for the test apparatus 300 to notify the user of the slope degradation component ΔDS1 and the slope degradation component ΔDS2. By comparing the slope degradation component ΔDS1 and the slope degradation component ΔDS2 when there is a failure in the memory cell, the cause of the failure can be predicted to some extent.
For example, in a case where the slope degradation component ΔDS1 is larger than the slope degradation component ΔDS2 when there is a failure in the memory cell, a main cause of the failure can be predicted to be a decrease in carrier capture efficiency of the memory cell. This makes it possible to prompt the user to take measures against a decrease in carrier capture efficiency of the memory cell.
In another case where the slope degradation component ΔDS2 is larger than the slope degradation component ΔDS1 when there is a failure in the memory cell, the main cause of the failure can be predicted to be the fringe effect of the memory cell. This makes it possible to prompt the user to take measures against the fringe effect of the memory cell.
As described above, in the embodiment, in testing the semiconductor storage device 1, the controller 302 of the test apparatus 300 performs the processing PC1 focusing on the overdrive region on the read characteristic of the memory cell that has undergone write processing, and obtains the threshold voltage. With this operation, the threshold voltage can be obtained by removing the influence of the fringe effect (influence of the degradation of the inclination in the subthreshold region). Based on the threshold voltage obtained in the processing PC1, the controller 302 calculates the slope SL1 in the threshold characteristic TP1 indicating the relationship between the write voltage and the threshold voltage, and subtracts the slope SL1 from the slope SL0 in the ideal threshold characteristic TP0 to obtain the slope degradation component ΔDS1. This makes it possible to separate a component indicating degradation due to a decrease in carrier capture efficiency of the memory cell to be obtained as the slope degradation component ΔDS1.
In addition, in the embodiment, in testing the semiconductor storage device 1, the controller 302 of the test apparatus 300 performs the processing PC2 focusing on the subthreshold region on the read characteristic of the memory cell that has undergone write processing, and obtains the threshold voltage. With this operation, the threshold voltage can be obtained in the mode of including the influence of the fringe effect (influence of the degradation of the inclination in the subthreshold region). Based on the threshold voltage obtained in the processing PC2, the controller 302 calculates the slope SL2 in the threshold characteristic TP2 indicating the relationship between the write voltage and the threshold voltage in the write processing, and subtracts the slope SL2 from the slope SL1 to obtain the slope degradation component ΔDS2. This makes it possible to separate a component indicating degradation due to the fringe effect of the memory cell to be obtained as the slope degradation component ΔDS2.
As a first modification of the embodiment, the controller 302 of the test apparatus 300 may calculate, in S3 of
The processing PC11 is similar to the processing PC1 in that the threshold voltage is obtained focusing on the overdrive region in the read characteristic, but is different from the processing PC1 in that the threshold voltage is obtained by parallel-translating the duplication of the waveform of the read characteristic on the low level side in the read voltage direction.
For example, regarding the graph of the read characteristic Pf1 on cell current that is logarithmically-converted as illustrated in
In obtaining the threshold voltage for the graph of the read characteristic Pf2, the controller 302 non-logarithmically-converts the cell current in each of the read characteristic Pf1 and the read characteristic Pf2, and obtains a read characteristic Pf1′ and a read characteristic Pf2′.
The controller 302 parallel-translates the duplication of the waveform of the read characteristic Pf1′ in the read voltage direction as indicated by a dotted outlined arrow. The controller 302 fits the duplicated waveform of the read characteristic Pf1′ to the waveform of the read characteristic Pf2′. The controller 302 logarithmically-converts the cell current in the fitted read characteristic Pf1′ again to obtain a read characteristic Pf22. With this operation, the controller 302 obtains a waveform of the fitted read characteristic Pf22 as indicated by a dotted line. The fitted read characteristic Pf22 has its overdrive region substantially overlapping the overdrive region of the read characteristic Pf2. The controller 302 obtains a threshold voltage corresponding to the read characteristic Pf2 using the waveform of the read characteristic Pf22. That is, the controller 302 obtains an intersection CX22 between the subthreshold region of the read characteristic Pf22 and the horizontal line HL1 representing threshold current level (cell current=threshold current level). The controller 302 sets the read voltage value at the intersection CX22 as a threshold voltage Vth22.
When applying a method of obtaining the read characteristic Pf1 and the read characteristic Pf2 on cell current that is logarithmically-converted based on the read characteristic Pf1′ and the read characteristic Pf2′ on the cell current that is not logarithmically-converted, the read characteristic Pf1′ and the read characteristic Pf2′ can be stored in the storage unit 303 in advance, and the stored read characteristic Pf1′ and read characteristic Pf2′ can be used in the processing PC11 so as to correspond to the read characteristic Pf1 and the read characteristic Pf2, respectively.
In obtaining the threshold voltage for the graph of the read characteristic Pf3, the controller 302 non-logarithmically-converts the cell current in each of the read characteristic Pf1 and the read characteristic Pf3, and obtains the read characteristic Pf1′ and a read characteristic Pf3′.
The controller 302 parallel-translates the duplication of the waveform of the read characteristic Pf1′ in the read voltage direction as indicated by a one-dot chain line outlined arrow. The controller 302 fits the duplicated waveform of the read characteristic Pf1′ to the waveform of the read characteristic Pf3′. The controller 302 logarithmically-converts the cell current in the fitted read characteristic Pf1′ again to obtain a read characteristic Pf23. With this operation, the controller 302 obtains a waveform of the fitted read characteristic Pf23 as indicated by a one-dot chain line. The fitted read characteristic Pf23 has its overdrive region substantially overlapping the overdrive region of the read characteristic Pf3. The controller 302 obtains a threshold voltage corresponding to the read characteristic Pf3 using the waveform of the read characteristic Pf23. That is, the controller 302 obtains an intersection CX23 between the subthreshold region of the read characteristic Pf23 and the horizontal line HL1 representing threshold current level (cell current=threshold current level). The controller 302 sets the read voltage value at the intersection CX23 as a threshold voltage Vth23.
When applying a method of obtaining the read characteristic Pf1 and the read characteristic Pf3 on cell current that is logarithmically-converted based on the read characteristic Pf1′ and the read characteristic Pf3′ on cell current that is not logarithmically-converted, the read characteristic Pf1′ and the read characteristic Pf3′ can be stored in the storage unit 303 in advance, and the stored read characteristic Pf1′ and read characteristic Pf3′ can be used in the processing PC11 so as to correspond to the read characteristic Pf1 and the read characteristic Pf3, respectively.
As illustrated in
In addition, the concept of the embodiment can be applied to a test of a memory cell subjected to the erase processing in addition to a test of a memory cell subjected to the write processing.
As a second modification of the embodiment, the controller 302 may functionally further include an erase processing unit 3031 illustrated in
Having received the erase command, the semiconductor storage device 1 can perform the erase processing on the memory cell addressed by the erase command. The erase processing may be performed by an Incremental Step Pulse Erasing (ISPE) method. In the erase processing, as illustrated in
Having received the erase completion notification, the interface unit 301 supplies the erase completion notification to the controller 302.
Thereafter, the read processing unit 3022 illustrated in
Having received the read command, the semiconductor storage device 1 can perform the read processing on the memory cell addressed by the read command. The read processing detects the cell current for each memory cell while sweeping the read voltage, as illustrated in
Having completed the read processing on the memory cell, the semiconductor storage device 1 generates read characteristic information. The read characteristic information indicates a read characteristic. The read characteristic indicates a relationship between the read voltage and the logarithm of the cell current. The semiconductor storage device 1 generates read characteristic information indicating the read characteristic Pf0, as illustrated in
The read characteristic Pf0 has a subthreshold region and an overdrive region. In the subthreshold region, the read characteristic Pf0 is characterized in that the logarithm of the cell current linearly increases steeply together with an increase in the read voltage. In the overdrive region, the read characteristic Pf0 is characterized in that the logarithm of the cell current increases nonlinearly and gradually together with an increase in the read voltage. In the read characteristic Pf0, the inclination of the tangent for cell current characteristic that is not logarithmically-converted tends to be maximized near the boundary between the subthreshold region and the overdrive region.
The semiconductor storage device 1 transmits the read characteristic information to the interface unit 301 via the communication medium 400.
The interface unit 301 receives the read characteristic information. Having acquired the read characteristic information 303b, the interface unit 301 supplies the read characteristic information 303b to the acquisition unit 3023 illustrated in
The threshold calculation unit 3024 performs the processing PC1 on the read characteristic indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. The processing PC1 is processing of obtaining the threshold voltage focusing on an overdrive region in the read characteristic. The processing PC1 includes processing of obtaining a voltage corresponding to a tangent near a boundary between the subthreshold region and the overdrive region in the read characteristic as the threshold voltage. The processing PC1 may include processing using a GM-MAX method.
For example, regarding the graph of the read characteristic Pf0 on cell current that is not logarithmically-converted illustrated in
As illustrated in
The threshold calculation unit 3024 illustrated in
The slope calculation unit 3025 generates the threshold characteristic information 303c based on the threshold voltage obtained in the processing PC1. The threshold characteristic information 303c indicates a threshold characteristic TP11. The threshold characteristic TP11 indicates a relationship between the erase voltage and the threshold voltage in the erase processing. As indicated by a dotted line of
The slope calculation unit 3025 calculates the slope SL11 in the threshold characteristic TP11. The slope SL11 indicates an inclination of change of the threshold voltage with respect to the erase voltage. The slope SL11 corresponds to the inclination of the straight line of the threshold characteristic TP11 illustrated in
The degradation component calculation unit 3026 illustrated in
The threshold calculation unit 3027 performs the processing PC2 on the read characteristic indicated by the read characteristic information 303b to obtain the threshold voltage of the memory cell. The processing PC2 is processing of obtaining the threshold voltage focusing on the subthreshold region in the read characteristic. The processing PC2 includes processing of obtaining a voltage corresponding to an approximate straight line of the subthreshold region in the read characteristic, as the threshold voltage.
For example, regarding the graph of the read characteristic Pf0 on cell current that is logarithmically-converted illustrated in
As illustrated in
The threshold calculation unit 3027 illustrated in
The slope calculation unit 3028 generates threshold characteristic information 303e based on the threshold voltage obtained in the processing PC12. The threshold characteristic information 303e indicates a threshold characteristic TP12. The threshold characteristic TP12 indicates a relationship between the erase voltage and the threshold voltage in the erase processing. As indicated by a solid line of
The slope calculation unit 3028 calculates the slope SL12 in the threshold characteristic TP12. The slope SL12 indicates an inclination of change of the threshold voltage with respect to the erase voltage. The slope SL12 corresponds to the inclination of the straight line of the threshold characteristic TP12 illustrated in
The degradation component calculation unit 3029 illustrated in
The notification unit 3030 reads the slope degradation component information 303d and the slope degradation component information 303f individually from the storage unit 303. The notification unit 3030 may display the slope degradation component ΔDS11 and the slope degradation component ΔDS12 on the display screen 304a of the display unit 304. The notification unit 3030 may display the slope degradation component information 303d and the slope degradation component information 303f on the display screen 304a of the display unit 304 in a mode of being able to recognize the magnitude relationship between the slope degradation component ΔDS11 and the slope degradation component ΔDS12. This makes it possible for the test apparatus 300 to notify the user of the slope degradation component ΔDS11 and the slope degradation component ΔDS12. By comparing the slope degradation component ΔDS11 and the slope degradation component ΔDS12 when there is a failure in the memory cell, the cause of the failure can be predicted to some extent.
For example, in a case where the slope degradation component ΔDS11 is larger than the slope degradation component ΔDS12 when there is a failure in the memory cell, a main cause of the failure can be predicted to be a decrease in carrier capture efficiency of the memory cell. This makes it possible to prompt the user to take measures against a decrease in carrier capture efficiency of the memory cell.
In another case where the slope degradation component ΔDS12 is larger than the slope degradation component ΔDS11 when there is a failure in the memory cell, the main cause of the failure can be predicted to be the fringe effect of the memory cell. This makes it possible to prompt the user to take measures against the fringe effect of the memory cell.
In this manner, in testing the semiconductor storage device 1, the controller 302 of the test apparatus 300 performs the processing PC1 focusing on the overdrive region on the read characteristic of the memory cell that has undergone erase processing, and obtains the threshold voltage. With this operation, the threshold voltage can be obtained by removing the influence of the fringe effect (influence of the degradation of the inclination in the subthreshold region). Based on the threshold voltage obtained in the processing PC1, the controller 302 calculates the slope SL11 in the threshold characteristic TP11 indicating the relationship between the erase voltage and the threshold voltage, and subtracts the slope SL11 from the slope SL10 in a predetermined threshold characteristic TP10 to obtain the slope degradation component ΔDS11. This makes it possible to separate a component indicating degradation due to a decrease in carrier capture efficiency of the memory cell to be obtained as the slope degradation component ΔDS11.
In addition, in testing the semiconductor storage device 1, the controller 302 of the test apparatus 300 performs the processing PC2 focusing on the subthreshold region on the read characteristic of the memory cell that has undergone erase processing, and obtains the threshold voltage. With this operation, the threshold voltage can be obtained in the mode of including the influence of the fringe effect (influence of the degradation of the inclination in the subthreshold region). Based on the threshold voltage obtained in the processing PC2, the controller 302 calculates the slope SL12 in the threshold characteristic TP12 indicating the relationship between the erase voltage and the threshold voltage in the erase processing, and subtracts the slope SL12 from the slope SL11 to obtain the slope degradation component ΔDS12. This makes it possible to separate a component indicating degradation due to the fringe effect of the memory cell to be obtained as the slope degradation component ΔDS12.
Moreover, in testing the memory cell that has undergone erase processing, the controller 302 of the test apparatus 300 may calculate the threshold voltage of the memory cell by applying processing PC11 as illustrated in
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-150343 | Sep 2023 | JP | national |
