This Application claims the benefit of and priority to Chinese Application No. 201711276164.7, filed on Dec. 6, 2017, which is hereby incorporated by reference in its entirety.
The present invention relates to a test apparatus.
As a high-speed data transmission method for data transmission between semiconductor devices, a source synchronous method is known. With this method, in addition to a data signal, a clock signal is transmitted via a pair of transmission lines in synchronization with the data signal. For example, the HDMI (trademark) (High-Definition Multimedia Interface) employs the source synchronous method.
The PLL circuit 102 generates a serial clock CKS by frequency multiplying the reference clock CKREF by N. With the TMDS (Transition Minimized Differential Signaling) employed in HDMI, N is set to 10. The serializer 104 performs parallel/serial conversion of parallel data DP to be transmitted into serial data DS using the serial clock CKS. The driver 106 drives a data line 302 according to the serial data DS. In this drawing, a single data line 302 is shown. In a case of employing a differential operation, a pair of data lines 302 are employed.
The TMDS employs a clock forward method. In this method, a serial signal is transmitted with a frequency that is an integer multiple of the clock signal. The frequency divider 108 frequency divides the serial clock CKS by N. The driver 110 drives a clock line 304 according to a base clock after the frequency division. With this arrangement, a data signal TData and a clock signal TClock are transmitted to the receiver RX.
The receiver RX includes a CRU (Clock Recovery Unit) 202 and a deserializer 204. The CRU 202 frequency multiplies the clock signal TClock by N so as to generate a sampling clock CKS having edges at appropriate timings. The deserializer 204 acquires the data signal TData with the sampling clock CKS as a trigger.
The clock signal TClock and the data signal TData output from the transceiver TX involve jitter. A strobe signal STRB generated by the CRU 202 follows the jitter of the clock signal TClock. Accordingly, the deserializer 204 is capable of correctly receiving the data signal having such jitter.
[Patent Document 1]
US Patent Application Publication No. 2005/0222789
[Patent Document 2]
US Patent Application Publication No. 2002/0188888
Let us consider a case in which the transmitter TX shown in
With the test apparatus including no CRU 202, a PLL circuit frequency multiplies an internal reference clock employed in the test apparatus so as to generate a strobe signal. The signal under test TData is acquired using the strobe signal thus generated, and is compared with an expected value.
That is to say, the test apparatus performs a substantially asynchronous operation with respect to the DUT. As described above, the signal under test TData includes jitter or drift. In a case in which the phase shift between the received data and the expected value exceeds 1 UI (Unit Interval), this leads to a problem in that a DUT that should be assessed as a non-defective product is assessed as a defective product.
Description has been made regarding the source synchronous method. A similar problem can occur in a case of testing a transmitter TX employing a clock embedded method.
The present invention has been made in order to solve such a problem. Accordingly, it is an exemplary purpose of an embodiment of the present invention to provide a test apparatus that is capable of testing a device under test while reducing effects of jitter or drift.
An embodiment of the present invention relates to a test apparatus. The test apparatus comprises: a time measurement unit structured to measure a time interval between edges to be monitored in a signal under test including serial data output from a device under test; and a comparison judgment unit structured to calculate the number of bits included between the edges to be monitored, based on the time interval thus measured, and to compare the number of bits with an expected value thereof.
It is to be noted that any arbitrary combination or rearrangement of the above-described structural components and so forth is effective as and encompassed by the present embodiments. Moreover, this summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.
Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which:
The invention will now be described based on preferred embodiments which do not intend to limit the scope of the present invention but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention.
In the present specification, the state represented by the phrase “the member A is coupled to the member B” includes a state in which the member A is indirectly coupled to the member B via another member that does not affect the electric connection between them, or that does not damage the functions of the connection between them, in addition to a state in which they are physically and directly coupled. Similarly, the state represented by the phrase “the member C is provided between the member A and the member B” includes a state in which the member A is indirectly coupled to the member C, or the member B is indirectly coupled to the member C via another member that does not affect the electric connection between them, or that does not damage the functions of the connection between them, in addition to a state in which they are directly coupled.
The test apparatus 300 includes a time measurement unit (TMU) 310 and a comparison judgment unit 320.
The time measurement unit 310 measures the time intervals ΔT1, ΔT2, . . . , between edge to be monitored, for the signal under test output from the DUT 400 in the form of a serial signal (which will be referred to as the “DUT_Output signal”). As the edges to be monitored, all the edges in the DUT_Output signal may be employed. Also, positive edges (rising edges, leading edges) may be employed. Also, negative edges (falling edges, trailing edges) may be employed.
The comparison judgment unit 320 calculates the number of bits X of the serial data included between the edges to be monitored, based on the time intervals ΔT thus measured, and compares the number of bits X with an expected value XEXP thereof. Furthermore, the comparison judgment unit 320 generates a Pass/Fail signal that corresponds to a comparison result. Specifically, when the number of bits X of the serial data thus calculated matches the expected value XEXP, judgment is made that the product is non-defective (Pass). Otherwise, judgment is made that the product is defective (Fail).
The comparison judgment unit 320 may be mounted in the form of a DSP (Digital Signal Processor).
When the number of bits of the serial data included between the edges to be monitored is detected as a non-integer value, rounding is performed. With such an arrangement, nearest rounding is preferably employed. Also, an arrangement may be made in which, when the tenths digit of such a non-integer value is greater than 5, it is rounded up, and otherwise, it is rounded down. Also, ordinary rounding-off may be employed. Also, an arrangement may be made in which, when the tenths digit of such a non-integer value is equal to or greater than 6, it is rounded up, and otherwise, it is rounded down.
For example, the time measurement unit 310 generates a time stamp T[i] for every edge to be monitored. Here, i represents the edge number.
The comparison judgment unit 320 calculates the edge time interval ΔTi=T[i+1]−T[i]. Furthermore, the comparison judgment unit 320 divides the edge time interval ΔTi by an ideal unit interval UIIDEAL and rounds off the calculation result. The rounded result is employed as the number of bits Xi.
Xi=Integer((T[i+1]−T[i])/UIIDEAL)
Here, Integer( ) represents a function that returns an integer obtained by nearest rounding its argument.
The above is the basic configuration of the test apparatus 300. Next, description will be made regarding the operation thereof.
As shown in
Next, description will be made regarding a mechanism for reducing the effects of jitter or drift (which will collectively be referred to simply as “jitter” hereafter without distinguishing them).
In a case in which there is no effect of jitter, the number of bits included between each pair of edges is an integer value. In contrast, if the DUT_Output signal is affected by jitter, the number of bits included between each pair of edges, i.e., (ΔTi/UIIDEAL) is a non-integer number. With the present embodiment, the number of bits (ΔTi/UIIDEAL) calculated as a non-integer value is rounded, and the rounded value is compared with the expected value thereof. This allows the effects of jitter to be removed.
With this test method, in theory, this arrangement is capable of removing the effects of jitter that is smaller than UIIDEAL/2 per bit. This arrangement is capable reducing the effects of drift, which is accumulated jitter, without any limitation. In the example shown in
The above is the basic configuration and the operation of the test apparatus 300.
In a case in which a clock recovery circuit or a clock data recovery circuit is mounted on the test apparatus 300 as shown in
In contrast, with the test apparatus or the test method according to the present embodiment, this arrangement is capable of testing various kinds of DUTs including various kinds of transmitters regardless of the kind of interface and regardless of the data transmission method such as the source synchronous method, clock forward method, embedded clock method, etc.
In many cases, the test apparatus is provided with a circuit block having a time stamping function as a standard component or otherwise an optional component. In this case, by using the time stamping function, and by preparing a software program for providing a general-purpose DUT with a function of the comparison judgment unit 320, this provides a test according to the embodiment with low costs.
It should be noted that, instead of configuring the comparison judgment unit 320 as a DSP controlled in a software manner, the comparison judgment unit 320 may be mounted in the form of an FPGA (Field Programmable Gate Array) or an ASIC (Application Specified IC).
The present invention encompasses various kinds of apparatuses and methods that can be regarded as a block configuration or a circuit configuration shown in
The data decimation unit 311 receives the signal under test DUT_Output and extracts the edges to be monitored. The remaining edges are discarded. The data decimation unit 311 includes a polarity selector 312, a pre-scaler 314, and an inter-discarder 316. The polarity selector 312 selects at least one edge polarity from among positive and negative with respect to the DUT_Output signal.
The edges thus selected by the polarity selector 312 are further thinned out by the pre-scaler 314 and the inter-discarder 316.
Specifically, the pre-scaler 314 receives the output signal of the polarity selector 312, and selects an edge for every K edges. Specifically, the pre-scaler 314 selects the (p+1×K)-th edge, the (p+2×K)-th edge, . . . , and the (p+j×K)-th edge (j represents an integer 1, 2, . . . ). Here, p is a parameter designed to satisfy the relation 1 p K. In a case in which K=1, the pre-scaler 314 passes all the edges.
The inter-discarder 316 receives the edges selected by the pre-scaler 314, and selects an edge for every L edges. Specifically, the inter-discarder 316 selects the (q+1×L)-th edge, the (q+2×L)-th edge, . . . , and the (q+j×L)-th edge (j represents an integer 1, 2, . . . ). Here, q is a parameter designed to satisfy the relation 1≤q≤L. In a case in which L=1, the inter-discarder 316 passes all the edges.
By employing a combination of the pre-scaler 314 and the inter-discarder 316, this arrangement is capable of selecting an edge for every N (=K×L) edges. By changing the parameter p from 1 up to K, and by changing the parameter q from 1 up to L, this arrangement is capable of measuring all the edge intervals.
The time stamper 318 assigns a time stamp T[i] to each edge of the output signal of the inter-discarder 316.
Next, description will be made regarding several examples of the operation of the test apparatus 300A.
As shown in
With the first example operation, a DUT that has passed both the test with respect to the positive edges and the test with respect to the negative edges is judged to be non-defective. Such a test in which the test with respect to the positive edge and the test with respect to the negative edge are performed for the same pattern generated by the DUT is equivalent to a test as shown in
The first example operation can be regarded as an operation in which an edge to be monitored is selected for every N=2 edges. As a generalization of this, an edge to be monitored may be selected for every N edges.
First, the first edge, the (1+N)-th edge, the (1+2×N)-th edge, . . . , and the (1+j×N)-th edge are selected as the edges to be monitored. Subsequently, the time stamps T[1], T[2], . . . , and T[j] are assigned to the edges thus selected. Furthermore, the time intervals thereof ΔT1, ΔT2, . . . , ΔTj, are acquired. In this example, the expected values are 37, 33, 33, . . . .
As the second test, the same test is performed for the second edge, the (2+N)-th edge, the (2+2×N)-th edge, . . . , and the (2+j×N)-th edge to be monitored. This test is repeated N times. As the last test, the same test is performed for the (N+N)-th edge, the (N+2×N)-th edge, . . . , and the (N+j×N)-th edge to be monitored. It should be noted that the order of the tests is not restricted in particular.
As a generalization, an edge to be monitored is selected for every N edges, and the test is executed for the i-th edge, the (i+N)-th edge, (i+2×N)-th edge, . . . , with i incremented from 1 to N. Here, i will be referred to as the “phase number”. When the DUT has passed all the tests for i=1 to N, the DUT is judged to be non-defective.
In a case in which the signal under test has a very high bit rate, and in a case in which the test is to be performed with all the edges as the monitoring targets, the time measurement unit 310 is required to be designed to have high time resolution. Furthermore, the comparison judgment unit 320 is required to have high processing performance. This involves increased costs of hardware components. In order to solve such a problem, by selecting a relatively large number N, this arrangement is able to reduce the required performance levels for the time measurement unit 310 and the comparison judgment unit 320.
The setting value L=3 is set for the inter-discarder 316. In a case in which q=1, the edge numbers 1, 10, 19, 28, . . . , are selected. The time stamps T[i] are generated for the edges thus selected. Furthermore, the number of bits Xi included in each time interval ΔTi is calculated. In this example, the expected values are 37, 33, 33, 32, . . . .
A similar test is performed for all the combinations of p and q. Here, p and q can each be regarded as a phase number. More specifically, in a case in which p=1 and q=2, a time stamp is assigned to each of the edges with the edge numbers 4, 13, 22, 31, . . . . In a case in which p=1 and q=3, a time stamp is assigned to each of the edges with the edge numbers 7, 16, 25, 34, . . . .
In a case in which p=2, the pre-scaler 314 selects the edges with the edge numbers 2, 5, 8, 11, . . . , (2+K×j). In a case in which q=1, the inter-discarder 316 selects the edges with the edge numbers 2, 11, 20, 29, . . . . In a case in which q=2, the inter-discarder 316 selects the edges with the edge numbers 5, 14, 23, 32, . . . . In a case in which p=2 and q=3, the edge numbers of the selected edges are 8, 17, 26, 35, . . . .
In a case in which p=3, the pre-scaler 314 selects the edges with the edge numbers 3, 6, 9, 12, . . . , (3+K×j). In a case in which q=1, the inter-discarder 316 selects the edges with the edge numbers 3, 12, 21, 30, . . . . In a case in which q=2, the inter-discarder 316 selects the edges with the edge numbers 6, 15, 24, 33, . . . . In a case in which p=3 and q=3, the edge numbers of the selected edges are 9, 18, 27, 36, . . . .
The same test is performed with respect to the inverted edge polarity, i.e., negative edges.
In a case of employing a combination of a pre-scaler and an inter-discarder as described in the third example operation, by optimizing the combination of the number of edge intervals K and the number of edges included in each pattern period, this arrangement allows the measurement to be repeatedly performed for the same pattern with a fixed phase number p, as with the fourth example operation. Similarly, by optimizing the number of edge intervals L and the number of edges included in each pattern period, this arrangement allows the measurement to be repeatedly performed for the same pattern with a fixed phase number q.
Description has been made above regarding the present invention with reference to the embodiments. The above-described embodiments have been described for exemplary purposes only, and is by no means intended to be interpreted restrictively. Rather, it can be readily conceived by those skilled in this art that various modifications may be made by making various combinations of the aforementioned components or processes, which are also encompassed in the technical scope of the present invention. Description will be made below regarding such modifications.
At least one component may be omitted from among the polarity selector 312, the pre-scaler 314, and the inter-discarder 316 included in the data decimation unit 311. It is needless to say that, in a case in which a high-speed time stamper or a high-speed DSP (comparison judgment unit 320) can be employed, the data decimation unit 311 may be omitted.
Description has been made regarding an arrangement in which PRBS4 is employed as the signal under test. However, the present invention is not restricted to such an arrangement. Also, PRBS7 or the like may be employed.
Description has been made in the embodiment regarding an arrangement in which the number of bits of serial data included between each pair of edges is acquired in the form of an integer value, and the integer value thus acquired is compared with an expected value thereof. However, the present invention is not restricted to such an arrangement. For example, the number of bits Xi′ of serial data included between each pair of edges may be acquired in the form of a non-integer value (floating-point data, for example) as represented by Xi′=(T[i+1]−T[i])/UIIDEAL.
Subsequently, judgment may be made regarding whether or not the number of bits Xi′ thus calculated is included in an expected range.
For example, in a case in which the expected value of the number of bits Xi is an integer value XEXPi, the expected range may be set to a range between (XEXPi−0.5) and (XEXPi+0.5). In this case, when the relation (XEXPi−0.5)<Xi′<(XEXPi+0.5) holds true, judgment may be made that the measurement result is “pass”. Otherwise, judgment may be made that the measurement result is “fail”.
While the preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the appended claims.
Number | Date | Country | Kind |
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201711276164.7 | Dec 2017 | CN | national |
Number | Name | Date | Kind |
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5919270 | Arkin | Jul 1999 | A |
20020188888 | Rivoir | Dec 2002 | A1 |
20050222789 | West | Oct 2005 | A1 |
20070247181 | Ishida | Oct 2007 | A1 |
20080040060 | Hou | Feb 2008 | A1 |
Number | Date | Country | |
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20190170823 A1 | Jun 2019 | US |