Patent Application
20070019480
The present invention relates generally to memory devices and in particular the present invention relates to test circuitry and testing methods for memory devices.
Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.
A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge on the floating gate.
NOR and NAND flash memory devices are two common types of flash memory devices, so called for the logical form the basic memory cell configuration in which each is arranged. Typically, for NOR flash memory devices, the control gate of each memory cell of a row of the array is connected to a word line, and the drain region of each memory cell of a column of the array is connected to a bit line. The memory array for NOR flash memory devices is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their control gates. The row of selected memory cells then place their data values on the column bit lines by flowing a differing current, depending upon their programmed states, from a connected source line to the connected column bit lines.
The array of memory cells for NAND flash memory devices is also arranged such that the control gate of each memory cell of a row of the array is connected to a word line. However, each memory cell is not directly connected to a column bit line by its drain region. Instead, the memory cells of the array are arranged together in strings (often termed NAND strings), e.g., of 32 each, with the memory cells connected together in series, source to drain, between a source line and a column bit line. The memory array for NAND flash memory devices is then accessed by a row decoder activating a row of memory cells by selecting the word line connected to a control gate of a memory cell. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series connected string, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.
Defects can occur during the manufacture of a flash memory array having rows and columns of memory cells, such as shorts between a word line and a bit line. Shorts typically occur because of the large number of rows and columns of memory cells that have to be placed in close proximity to each other on an integrated circuit wafer. In these increasingly tighter geometries, alignment errors and other processing imperfections can lead to shorts between adjacent structures. Such defects can reduce the yield of the flash memory device.
After a memory die has been manufactured, it is tested for shorts between word lines and bit lines. In general, this testing helps with repair and/or identification of defects that can render the device inoperable. Due to shrinking cell geometries and increased word line to bit line voltage potentials during erase cycles, the density of shorts between word lines and bit lines has increased, and conventional test methods are becoming excessively time consuming.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to conventional test methods for testing for shorts between word lines and bit lines.
The above-mentioned problems with conventional test methods for detecting shorts between word lines and bit lines and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
For one embodiment, the invention provides a method of testing a memory device that includes comparing a signal indicative of a current drawn by one or more select lines to a reference signal generated within the memory device, and indicating whether the signal indicative of the current drawn by the one or more select lines exceeds the reference signal.
For another embodiment, the invention provides a memory device having a memory array having a plurality of select lines. Testing circuitry is coupled to the select lines. The testing circuitry includes a comparator. The comparator compares a signal indicative of a current drawn by one or more of the select lines to a reference signal generated within the memory device. The comparator indicates whether the signal indicative of the current drawn by the one or more select lines exceeds the reference signal.
Further embodiments of the invention include methods and apparatus of varying scope.
In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.
For one embodiment, memory device 102 includes an array of memory cells 104, an address decoder 106, row access circuitry 108, column access circuitry 110, control circuitry 112, Input/Output (I/O) circuitry 114, and an address buffer 116.
Memory device 102 may be coupled with an external microprocessor 120, or memory controller, for memory accessing as part of an electronic system 100. The memory device 102 receives control signals from the processor 120 over a control link 122. The memory cells are used to store data that are accessed via a data (DQ) link 124. Address signals are received via an address link 126 that are decoded at address decoder 106 to access the memory array 104. Address buffer circuit 116 latches the address signals. The memory cells are accessed in response to the control signals and the address signals. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of
The memory array 104 includes memory cells arranged in row and column fashion. For one embodiment, each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells may be grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation.
For one embodiment, control circuitry 112 includes test circuitry 150 for testing for word line to bit line shorts in memory array 104. This involves comparing a reference current generated within the memory device to a current indicative of a current flowing through one or more word lines of memory array 104 when a test voltage, e.g., about five volts, is applied to the one or more word lines and one or more corresponding bit lines are grounded. Alternatively, the reference current may be generated externally of the memory device and supplied to an input pad of the memory device. When the word line indicator current exceeds the reference current, test circuitry 150 outputs a first logic value, such as logic high, indicative a short between a word line and a bit line. Otherwise, test circuitry 150 outputs a second logic value, such as logic low, indicative that there are no shorts detected between the word lines and the bit lines. For another embodiment, the output of test circuitry 150 is sent to an input/output pad (not shown in
The detail of memory block 200 is provided to better understand the various embodiments of the invention. However, the invention is not limited to the specific floating-gate memory cell and layout described with reference to
As shown in
Floating gate transistors 206 are located at each intersection of a word line 202 and a local bit line 204. The floating gate transistors 206 represent the non-volatile memory cells for storage of data. Typical construction of such floating gate transistors 206 include a source 208 and a drain 210, a floating gate 212, and a control gate 214.
Floating gate transistors 206 having their control gates 214 coupled to a word line 202 typically share a common source 208 depicted as array source 216. As shown in
It should be noted that although
A resistor 220 coupled between a select line 202 and a bit line 204 is intended to exemplify a resistive short between that select line 202 and that bit line 204. Select lines 202 are coupled to a comparator 250 and bit lines 204 are coupled to ground to test for shorts between select lines 202 and bit lines 204. During a test, a test voltage, e.g., five volts, is applied to all of the select lines 202 to be tested, while bit lines 204 corresponding to the select lines 202 to be tested and array sources 216 are grounded. This causes a word line indicator current Iwl that is indicative of, e.g., proportional to, current flowing through one or more of the select lines 202 to be compared to a reference current Iref, generated within the memory device, at comparator 250. When the word line indicator current Iwl exceeds the reference current Iref, comparator 250 outputs a signal having a logic value, such as logic high, indicative a short to a select line. Otherwise, comparator 250 outputs a logic value, such as logic low, indicating that there are no shorts to the select lines. Although shorts are often located between a select line and an intersecting bit line, as conceptually depicted by resistor 220, other shorts to select lines 202 may be detected. Shorts, such as a short between a substrate on which a NAND array is formed through a gate dielectric layer of a select line coupled to a select gate of a NAND memory array may also be detected as described above. Hereinafter the term “shorts” will refer to any short to a select line 202 leading to a current loss in response to application of the test voltage.
In Table 1, for one embodiment, “Hi-Z” corresponds to a non-driven voltage.
When the test mode is enabled, p-channel field-effect transistors (pFETs) 302 and 304 are enabled by a first enable signal enable I_going LOW, and pFETs 306 and 308 are enabled by a second enable signal enable II going LOW. An external supply voltage Vext, e.g., about 5 to 6 volts, is applied to node 310, and an output voltage signal Vout supplies a voltage Vselect at output node 314 to the select lines that is generally somewhat less than the external supply voltage Vext due to a slight voltage drop across pFETs 302, 312, and 306. When there is no short, the steady-state current thru pFET 312 is substantially zero as the select lines would form an open circuit. However, if there is a short, a leakage path results that causes a first gate bias voltage VbiasI at node 311 to drop to a level indicative of the level of current flow thru pFET 312. It will be recognized that pFETs 302, 312 and 306 form a reference leg of a current mirror while pFETs 304, 316 and 308 form a mirror leg of the current mirror. As a result, the current flow thru pFET 312 is mirrored through pFET 316. This current is selectively passed to n-channel field-effect transistor (nFET) 320 thru nFET 319. With its drain coupled to its gate, the mirrored current applied to the drain of nFET 320 will produce a second gate bias voltage VbiasII that is indicative of the level of current flow through nFET 320. The second gate bias voltage VbiasII is, in turn, applied to the gate of nFET 322. By biasing the drain of nFET 322 and coupling its source to a ground potential node, a current, Iwl, will be generated that is indicative of a level of current flow through the leakage path. It should be noted that when the second enable signal enable II is HIGH, nFET 350 connects second gate bias voltage VbiasII to ground, thus turning off nFET 320 and nFET 322.
Note that for one embodiment, the reference leg and the mirror leg of the current mirror are sized substantially the same, i.e., pFETs 302 and 304 are substantially the same size, pFETs 312 and 316 are substantially the same size, and pFETs 306 and 308 are substantially the same size to facilitate mirroring of the current through the leakage path. For a further embodiment, the nFETs 320 and 322 are substantially the same size to facilitate establishing Iwl at a level that is directly proportional to the current through the leakage path. For another embodiment, pFETs 302, 312, and 306 are respectively proportional in size to pFETs 304, 316, and 308.
The drain of nFET 322 is biased to, e.g., about 0.7 volts, thru a comparator (or sense amp circuit) 330, for one embodiment, causing the select line indicator current Iwl to flow through nFET 322. The select line indicator current Iwl thru nFET 322 is compared inside comparator 330 to the reference current Iref, generated within comparator 330 in response to a reference voltage VREF. For another embodiment, the reference current Iref may be generated externally and supplied to an input pad of the memory device. A variety of methods for sensing current differences are known and the invention is not limited to a specific method.
Inside comparator 330, VREF is placed, for example, on a gate of an nFET with a grounded source and a drain biased to the biasing voltage on the drain of nFET 322, e.g., about 0.7 volts. When the select line indicator current Iwl is greater than the reference current Iref, comparator 330 indicates a short by setting an indicator signal Indicator, such as a digital output signal, having a logic value, such as a logic HIGH, indicative of a short on the selected select line or memory block(s). Otherwise, comparator 330 indicates that the selected select line or memory block(s) is okay or “good” by setting the indicator signal Indicator to another logic value, such as a logic LOW. For one embodiment, the indicator signal Indicator is sent to an input/output pad 340 of the memory device.
The reference current Iref may be a predetermined value chosen to be indicative of an acceptable level of current leakage given the number of select lines under test, accepting that some level of current leakage is generally inevitable even if no short is present. Higher values of Iref are generally deemed to be acceptable if multiple select lines are being tested than if a single select line is being tested. However, the value of Iref for the testing of multiple select lines would generally not be equal to the product of Iref for testing of a single select line times the number of select lines under test. The value of the reference current Iref should generally be chosen such that it is approximately equal to or greater than the expected current leakage if no short is present in the select lines under test, but less than an expected current leakage if at least one short is present. For other embodiments, the reference current Iref is adjustable.
For one embodiment, the value of the reference voltage VREF can be determined by selecting a voltage that produces reference current Iref that is substantially equal to a select line indicator current Iwl for a known “good” select line or memory block(s) that does not have a short. For another embodiment, the reference voltage VREF may be supplied externally to an input pad of the memory device or generated internally within the memory device.
For some embodiments, the select line indicator current Iwl is passed through a resistor (not shown), and the resulting voltage drop across the resistor is compared to the reference voltage VREF. If the reference voltage VREF is greater than or equal to the resulting voltage drop across the resistor, the select line is shorted, i.e., either to a bit line or an oxide layer of the select line coupled a select gate of a NAND memory array is shorted to a substrate. It will be appreciated by those skilled in the art that there are other ways of determining if a signal indicative of the current drawn through the select line(s) is greater than a desired level, whether comparing it to a reference current or voltage level.
For one embodiment, a memory device compares a signal indicative of a current drawn by one or more select lines to a reference signal generated within the memory device, and indicates whether the signal indicative of the current drawn by the one or more select lines exceeds the reference signal. This is considerably less time consuming than conventional testing and can reduce test times by as much as a factor of about 8 to a factor of about 240.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.
