Claims
- 1. An apparatus for testing an embedded memory in an integrated circuit, comprising:
input logic comprising one or more memory-input paths coupled to respective memory inputs of the embedded memory; a memory built-in self-test (MBIST) controller; and at least one scan cell coupled between the input logic and the MBIST controller, and being selectively operable in a memory-test mode and a system mode, wherein the at least one scan cell inputs memory-test data from the MBIST controller and outputs the memory-test data through the input logic along at least one of the memory-input paths while operating in the memory-test mode.
- 2. The apparatus of claim 1, further comprising compensatory input logic coupled between the MBIST controller and the at least one scan cell, the compensatory input logic being configured to perform a function on the memory-test data.
- 3. The apparatus of claim 2, wherein the function performed by the compensatory input logic is the inverse of a function performed by the input logic.
- 4. The apparatus of claim 2, wherein the compensatory input logic comprises one or more fan-outs that control memory inputs having two or more controlling paths.
- 5. The apparatus of claim 1, wherein the at least one scan cell is part of one or more respective scan chains, wherein the at least one scan cell is further operable in a scan mode, and wherein the at least one scan cell shifts scan-chain data through the one or more respective scan chains while operating in the scan mode.
- 6. The apparatus of claim 1, further comprising at least one modified system register coupled between the input logic and the MBIST controller, and being selectively operable in the memory-test mode and the system mode.
- 7. The apparatus of claim 1, wherein the at least one scan cell is at least one input scan cell, the apparatus further comprising:
output logic comprising one or more memory-output paths coupled to respective memory outputs of the embedded memory; and at least one output scan cell configured to input memory-test responses from the memory-output paths and output the memory-test responses to the MBIST controller.
- 8. The apparatus of claim 7, further comprising compensatory output logic coupled between the at least one output scan cell and the MBIST controller, the compensatory output logic being configured to perform a function on the memory-test responses.
- 9. The apparatus of claim 8, wherein the function performed by the compensatory output logic is the inverse of a function performed by the output logic.
- 10. A computer-readable medium storing computer-executable instructions for causing a computer system to design the apparatus of claim 1.
- 11. A computer-readable medium storing a design database that comprises design information for the apparatus of claim 1.
- 12. A scan cell used for testing an embedded memory in an integrated circuit, comprising:
a clocked element that inputs data from a data-input path and outputs data along a data-output path; a primary multiplexer having a primary output coupled to the data-input path and two or more primary inputs coupled to at least a system-data path and a secondary-multiplexer path, respectively, the primary multiplexer being operable to selectively output at least system data or test data on the data-input path; and a secondary multiplexer having a secondary output coupled to the secondary-multiplexer path and secondary inputs coupled to at least a scan-chain-data path and a memory-test-data path, the secondary multiplexer being operable to selectively output at least scan-chain data or secondary-multiplexer data on the secondary-multiplexer path.
- 13. The scan cell of claim 12, wherein the clocked element is a flip-flop.
- 14. The scan cell of claim 12, wherein the clocked element comprises a part of a scan chain in the integrated circuit.
- 15. The scan cell of claim 12, wherein the primary multiplexer and the secondary multiplexer are two-input multiplexers.
- 16. The scan cell of claim 12, further comprising a two-input OR gate having a first input coupled to a memory-test enable signal, a second input coupled to a scan-chain enable signal, and an output coupled to a data-select input of the primary multiplexer.
- 17. The scan cell of claim 12, wherein the memory-test data is a constant value.
- 18. The scan cell of claim 12, wherein the data-output path is coupled to an input of an embedded memory, and the memory-test-data path is coupled to an output of a memory built-in self-test (MBIST) controller.
- 19. The scan cell of claim 18, wherein the data-output path comprises input logic, and wherein the memory-test-data path comprises compensatory input logic.
- 20. The scan cell of claim 19, wherein the compensatory input logic performs an inverse function of the input logic.
- 21. A computer-readable medium storing computer-executable instructions for causing a computer system to design the scan cell of claim 12.
- 22. A computer-readable medium storing a design database that comprises design information for the scan cell of claim 12.
- 23. A method for testing an embedded memory in an integrated circuit, comprising:
switching one or more sequential elements of the integrated circuit into a memory-test mode; loading memory-test data into the one or more sequential elements from a memory-test controller located on the integrated circuit; and outputting the memory-test data from the one or more sequential elements and into the embedded memory, wherein the one or more sequential elements are coupled to the embedded memory via one or more system paths.
- 24. The method of claim 23, wherein the act of loading the memory-test data includes performing a function on the memory-test data, the function compensating for a function performed along the one or more system paths.
- 25. The method of claim 23, wherein at least one of the sequential elements comprises a modified scan cell of a scan chain.
- 26. The method of claim 23, wherein at least one of the sequential elements is in a shadow register.
- 27. The method of claim 23, wherein at least one of the sequential elements comprises a modified system register.
- 28. The method of claim 23, wherein the one or more system paths comprise input logic.
- 29. The method of claim 23, wherein the one or more sequential elements are one or more input sequential elements, and wherein the system paths are one or more system-input paths, the method further comprising:
outputting memory-test responses from the embedded memory into one or more output sequential elements, wherein the one or more output sequential elements are coupled to the embedded memory via one or more observation paths.
- 30. The method of claim 29, further comprising:
outputting the memory-test responses from the one or more output sequential elements; and receiving the memory-test responses in the memory-test controller.
- 31. The method of claim 30, wherein the act of outputting the memory-test responses comprises performing a function on the memory-test responses, the function compensating for a function performed along the one or more observation paths.
- 32. The method of claim 23, further comprising:
switching the one or more sequential elements of the integrated circuit into a scan-chain mode; and loading test patterns for testing the integrated circuit into the one or more sequential elements from an external tester while operating in the scan-chain mode.
- 33. An integrated circuit comprising hardware configured to perform the method of claim 23.
- 34. A computer-readable medium storing computer-executable instructions for causing a computer system to design hardware configured to perform the method of claim 23.
- 35. A computer-readable medium storing a design database that comprises design information for hardware configured to perform the method of claim 23.
- 36. A method for testing an embedded memory in an integrated circuit, comprising:
means for switching one or more sequential elements of the integrated circuit into a memory-test mode; means for loading memory-test data into the one or more sequential elements from a memory-test controller located on the integrated circuit; and means for outputting the memory-test data from the one or more sequential elements and into the embedded memory, wherein the one or more sequential elements are coupled to the embedded memory via one or more system paths.
- 37. A method of designing a memory built-in self-test (MBIST) architecture for testing an embedded memory in an integrated circuit, the method comprising:
searching for controlling paths that can be used to control respective input pins of the embedded memory via single respective controlling points; identifying and classifying any input pins that cannot be controlled by single respective controlling points as being unconstrained input pins or constrained/dependent input pins; sensitizing independent paths for the unconstrained input pins; and justifying applicable values for the constrained/dependent input pins.
- 38. The method of claim 37, further comprising the act of disregarding input pins of the embedded memory that are tied to a specific value or that are directly connected to other pins.
- 39. The method of claim 37, further comprising the act of justifying all test patterns used to test the embedded memory on the input pins of the embedded memory if the applicable values for the constrained/dependent input pins cannot be justified.
- 40. The method of claim 37, wherein the act of searching for controlling paths further comprises the act of searching for observation paths that can be used to observe output pins of the embedded memory at single respective observation points.
- 41. The method of claim 40, wherein the act of identifying and classifying the input pins further comprises the act of identifying and classifying output pins that cannot be observed by single respective observation points as being constrained by another output pin or as being dependent on another pin.
- 42. The method of claim 41, further comprising the act of finding observation paths for output pins that are constrained by another output pin by controlling the other output pin during at least one extra test.
- 43. The method of claim 41, further comprising the act of finding observation paths for output pins that are constrained by another output pin by coupling the constrained output pins directly to an MBIST controller.
- 44. The method of claim 37, wherein at least some of the respective controlling points comprise scan cells from one or more scan chains in the integrated circuit, and wherein the scan cells are modified to input memory-test data from an MBIST controller located on the integrated circuit.
- 45. A computer-readable medium storing computer-executable instructions for causing a computer system to perform the method of claim 37.
- 46. A computer-readable medium storing a design database that includes design information for hardware designed according to the method of claim 37.
- 47. A method for designing a memory built-in self-test (MBIST) architecture for testing an embedded memory in an integrated circuit, the method comprising:
finding one or more control paths from memory inputs of the embedded memory to one or more respective control points, at least one of the control points comprising a modified scan cell or a modified system register; and synthesizing hardware that couples at least one of the control points to an associated output of a memory-test controller located on the integrated circuit.
- 48. The method of claim 47, wherein the act of finding the control paths comprises:
sensitizing individual control paths to the memory inputs; and justifying applicable values to memory inputs that cannot be sensitized.
- 49. The method of claim 48, wherein the memory inputs that cannot be sensitized comprise unconstrained inputs or constrained/dependent inputs, and wherein the memory inputs to which the applicable values are justified comprise the constrained/dependent inputs.
- 50. The method of claim 47, wherein the act of synthesizing comprises reducing the size of the hardware by identifying two or more of the control points that can be coupled to a single respective output of the memory-test controller.
- 51. The method of claim 47, wherein the act of synthesizing comprises searching for connections between the control points and the hardware using functions having as few variables as possible.
- 52. The method of claim 47, wherein the act of synthesizing comprises inserting a fan-out from a single respective output of the memory-test controller to control two or more of the control points.
- 53. The method of claim 52, further comprising delaying placement of the fan-out in order to reduce area overhead of the hardware.
- 54. A computer-readable medium storing computer-executable instructions for causing a computer system to perform the method of claim 47.
- 55. A computer-readable medium storing a design database that includes design information for an MBIST system designed according to the method of claim 47.
Parent Case Info
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application claims the benefit of U.S. Provisional Application No. 60/447,583, filed Feb. 13, 2003, and claims the benefit of U.S. Provisional Application No. 60/512,278, filed Oct. 17, 2003, both of which are hereby incorporated by reference.
Provisional Applications (2)
|
Number |
Date |
Country |
|
60447583 |
Feb 2003 |
US |
|
60512278 |
Oct 2003 |
US |