The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Integrated circuit (IC) devices integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvement in 2D IC formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are used.
In light of these challenges, the present disclosure, across various embodiments, introduces a three-dimensional (3D) IC structure. This structure comprises lower transistors at a substrate level and higher transistors at an elevated level, resulting in a notable increase in device density within a specified area. More specifically, several embodiments of the current disclosure utilize a laser-liquid-phase-epitaxy technique to create an epitaxial layer above the lower transistors. This epitaxial layer functions as a seed layer, enabling the growth of semiconductor layers for the fabrication of the higher transistors on the elevated level. Thus, the 3D IC structure can be fabricated without using a wafer bonding technique.
The bottom epitaxial stack BE is illustrated as including three first semiconductor layers 102L and two second semiconductor layers 102L for illustrative purposes. In some embodiments, the bottom epitaxial stack BE may include any number of the first semiconductor layers 101L and the second semiconductor layers 102L. Each of the layers of the bottom epitaxial stack BE may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.
The first semiconductor layers 101L and the second semiconductor layers 102L may be materials having a high-etch selectivity to one another. As such, the first semiconductor layers 101L of a first semiconductor material may be removed without significantly removing the second semiconductor layers 102L of a second semiconductor material, thereby allowing the second semiconductor layers 102L to serve as channel regions of bottom GAA-FETs. In various embodiments, the first semiconductor layers 101L and the second semiconductor layers 102L are made of different materials selected from the group consisting of Si, Ge, Sn, Si1-xGex, Ge1-ySny, Si1-x-yGexSny, III-V compound, and combinations thereof. Because of the material difference, in subsequent processing, the first semiconductor layers 101L can be selectively etched without substantially etching the second semiconductor layers 102L.
Referring now to
The fin structure FN1 may be patterned by any suitable method. For example, a hard mask 103 (e.g., formed of SiO2) is first formed over the bottom epitaxial stack BE by using suitable deposition and patterning techniques, followed by patterning the bottom epitaxial stack BE into the fin structure FN1 by one or more etching processes using the hard mask 103 as an etch mask. While each of the fin structure FN1 is illustrated as having a consistent width throughout, in other embodiments, the fin structures FN1 may have tapered sidewalls such that a width of the fin structure FN1 continuously increases in a direction towards the substrate 100. In such embodiments, each of the nanostructures 101, 102 may have a different width and be trapezoidal in shape.
In
A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures 101, 102. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process is performed until a topmost one of the first nanostructures 101 such that a top surface of the topmost one of the first nanostructures 101 and the insulation material are level after the planarization process is complete. In this way, the hard mask 103 can be removed by the planarization process.
The insulation material is then recessed to form the STI regions 104. The insulation material is recessed such that an upper portion of the fin structure FN1 protrudes from between neighboring STI regions 104. Further, the top surfaces of the STI regions 104 may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions 104 may be formed flat, convex, and/or concave by an appropriate etch. The STI regions 104 may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fin structure FN1. For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used.
The process described above with respect to
In
The mask layer 106 may be patterned using acceptable photolithography and etching techniques. The pattern of the mask layer 106 then may be transferred to the dummy gate layer and to the dummy dielectric layer to form the dummy gate structure 105. The dummy gate structure 105 covers respective the channel region of the fin structure FN1. The dummy gate structure 105 may also have a lengthwise direction substantially perpendicular to the lengthwise direction of the fin structures FN1.
In
Next, exposed portions of the fin structure FN1 that laterally extend beyond the hard mask layer 106 and the gate spacers 107 are etched to form source/drain recesses R1 at opposite sides of the dummy gate structure 105, by using the hard mask layer 106 and the gate spacers 107 as an etch mask. Thereafter, portions of sidewalls of the layers in the fin structure FN1 formed of the first semiconductor materials (e.g., the first nanostructures 101) exposed by the source/drain recesses R1 are etched to form sidewall recesses between corresponding second nanostructures 102, followed by forming inner spacers 107s in the sidewall recesses. The resulting structure is illustrated in
The inner spacers 107s may be formed by, for example, depositing an inner spacer material layer in the sidewall recesses by using a conformal deposition process, such as CVD, ALD, or the like, followed by anisotropically etching the inner spacer layer to remove excessive inner spacer materials outside the sidewall recesses, while leaving the remaining inner spacer materials in the sidewall recesses to serve as the inner spacers 107s. The inner spacers 107s may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. Although outer sidewalls of the inner spacers 107s are illustrated as being flush with sidewalls of the second nanostructures 102, the outer sidewalls of the inner spacers 107s may extend beyond or be recessed from sidewalls of the second nanostructures 102.
In
In some embodiments, the epitaxial source/drain regions 108 may include any acceptable material appropriate for n-type GAA-FETs. For example, if the second nanostructures 102 are silicon, the epitaxial source/drain regions 108 may include materials exerting a tensile strain on the second nanostructures 102, such as silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. In some embodiments, the epitaxial source/drain regions 108 may include any acceptable material appropriate for p-type GAA-FETs. For example, if the second nanostructures 102 are silicon, the epitaxial source/drain regions 108 may comprise materials exerting a compressive strain on the second nanostructures 102, such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions 108 may be implanted with an n-type dopant (e.g., phosphorus) to form n-type source/drain regions or a p-type dopant (e.g., boron) to form p-type source/drain regions, followed by an anneal. In some embodiments, the epitaxial source/drain regions 108 may be in situ doped during growth.
After forming the epitaxial source/drain regions 108, an interlayer dielectric (ILD) layer 109 is formed over the dummy gate structure 105 by using suitable deposition techniques, followed by performing a planarization process (e.g., CMP) on the ILD layer 109 until the dummy gate structure 105 is exposed. The patterned mask 106 is thus removed by the planarization process. In some embodiments, the ILD layer 109 may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric material(s) of the ILD layer 109 may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. Then, a planarization process, such as a CMP, may be performed to level the top surface of the ILD layer 109 with the top surface of the dummy gate structure 105.
In
Next, the first nanostructures 101 in the gate trench GT1 are removed by an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the first nanostructures 101. Stated differently, the first nanostructures 101 are removed by using a selective etching process that etches the first nanostructures 101 at a faster etch rate than it etches the second nanostructures 102, thus forming spaces between the second nanostructures 102 (also referred to as sheet-to-sheet spaces if the nanostructures 102 are nanosheets). This step can be referred to as a channel release process. At this interim processing step, the spaces between second nanostructures 102 may be filled with ambient environment conditions (e.g., air, nitrogen, etc). In some embodiments, the second nanostructures 102 can be referred to as nanosheets, nanowires, nanoslabs, nanorings having nano-scale size (e.g., a few nanometers), depending on their geometry. For example, in some embodiments the second nanostructures 102 may be trimmed to have a substantial rounded shape (i.e., cylindrical) due to the selective etching process for completely removing the first nanostructures 101. In that case, the resultant second nanostructures 102 can be called nanowires. In embodiments in which the first nanostructures 101 include, e.g., SiGe, and the second nanostructures 102 include, e.g., Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) or the like may be used to remove the first nanostructures 101. In some embodiments, the second nanostructures 102 (also referred to as nanosheets) each have a thickness in a range from about 0.1 nm to about 100 nm, and a width in a range from about 0.1 nm to about 100 nm. In some embodiments, the cross-section profile of the second nanostructures 102 can be rectangular, square, circular, diamond, etc., with or without rounded corners.
In some embodiments, the high-k gate dielectric layer 110 includes silicon carbonnitride (SiCN) with a dielectric constant of about 4.9, silicon nitride (Si3N4) with a dielectric constant of about 7.1, aluminum oxide (Al2O3) with a dielectric constant of about 9, silicon oxide (SiO2) with a dielectric constant (i.e., k value) of about 3.9, hafnium oxide (HfO2) with a dielectric constant of about 20, zirconium oxide (ZrO2) with a dielectric constant of about 40, titanium oxide (TiO2) with a dielectric constant of about 95, tantalum oxide (Ta2O5) with a dielectric constant of about 26, hafnium zirconium oxide (H2O) with a dielectric constant of about 20 to about 45, lead zirconate titanate (PZT), e.g., PbZr0.52Ti0.48O3, with a dielectric constant of about 1400 to about 1800, yttrium oxide (Y2O3) with a dielectric constant of about 14 to about 18, poly[(vinylidenefluoride-co-trifluoroethylene] (P(VDF/TrFE)) with a dielectric constant of about 14-18, and/or barium titanium oxide (BaTi3) with a dielectric constant greater than about 200.
In some embodiments, the work function metal layer 111 includes one or more n-type work function metal (N-metal) layers and/or one or more p-type work function metal (P-metal) layers. The n-type work function metal may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and/or other suitable materials. The p-type work function metal may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials. In some embodiments, the fill metal 112 may exemplarily include, but are not limited to, Pt, Ti, TiN, Al, W. WN, Ru, RuO, Ta, Ni, Co, Cu, Ag. Au, or other suitable materials.
After forming the replacement gate structure GS1, a refill dielectric 109s is deposited over the replacement gate structure GS1. In some embodiments, the refill dielectric 109s may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric material(s) of the refill dielectric 109s may be the same as that of the ILD layer 109. For example, the refill dielectric 109s may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. The refill dielectric 109s and the previously formed ILD layer 109 are distinguished by using dash lines in
The ILD layer 109 and the STI regions 104 are patterned using suitable photolithography and etching techniques. For example, a photoresist layer is formed over the ILD layer 109 by using a spin-on coating process, followed by patterning the photoresist layer to expose target regions of the ILD layer 109 using suitable photolithography techniques. For example, photoresist layer is irradiated (exposed) and developed to remove portions of the photoresist layer. In greater detail, a photomask or reticle (not shown) may be placed above the photoresist layer, which may then be exposed to a radiation beam which may be ultraviolet (UV) or an excimer laser such as a Krypton Fluoride (KrF) excimer laser, or an Argon Fluoride (ArF) excimer laser. Exposure of the photoresist material may be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and decrease the minimum achievable pitch. A bake or cure operation may be performed to harden the exposed photoresist layer, and a developer may be used to remove either the exposed or unexposed portions of the photoresist material depending on whether a positive or negative resist is used. After the patterned photoresist layer is formed, an etching process is performed on the exposed target regions of the ILD layer 109, thus forming trenches T1 in the ILD layer 109 and the underlying STI regions 104.
Although the trenches T1 illustrated in
Silicon atoms deposited on the ILD layer 109 tend to form an amorphous solid (i.e., non-crystalline solid) that lacks the long-range order of a crystal, because the dielectric material in the ILD layer 109 is amorphous in nature. At an initial stage, the amorphous silicon layer 113 is conformally deposited into the trenches T1 in the ILD layer 109 and STI regions 104 and on a top surface of the ILD layer 109, and the deposition process then continues until the trences T1 are overfilled with the amorphous silicon layer 113.
As a result of the deposition process, the amorphous silicon layer 113 includes amorphous silicon plugs 1131 extending in the trences T1 in the ILD layer 109, and an amorphous silicon lateral portion 1132 extending along a top surface of the ILD layer 109. Height of the amorphous silicon plugs 1131 is equal to the depth of the trenches T1, and thus is greater than a full thickness of the ILD layer 109 and a full thickness of the STI regions 104. Thickness of the amorphous silicon lateral portion 1132 can be less than, greater than, or equal to the height of the amorphous silicon plugs 1131. In some embodiments, the height of amorphous silicon plugs 1131 is greater than the width of the amorphous silicon plugs 1131.
In
As illustrated in
Next, a CMP process is performed on the crystalline silicon layer 114 to remove the protrusions 114P. The resultant structure is illustrated in
In
The top epitaxial stack TE is illustrated as including three first semiconductor layers 116L and two second semiconductor layers 115L for illustrative purposes. In some embodiments, the bottom epitaxial stack TE may include any number of the first semiconductor layers 116L and the second semiconductor layers 115L. Each of the layers of the bottom epitaxial stack TE may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The bottommost layer of the top epitaxial stack TE (i.e., bottommost one of the first semiconductor layers 116L) is epitaxially grown using the crystalline silicon layer 114 as a seed layer, and thus the resultant bottommost first semiconductor layer 116L and overlying semiconductor layers will be single-crystalline.
The first semiconductor layers 116L and the second semiconductor layers 115L may be materials having a high-etch selectivity to one another. As such, the first semiconductor layers 116L of a first semiconductor material may be removed without significantly removing the second semiconductor layers 115L of a second semiconductor material, thereby allowing the second semiconductor layers 115L to serve as channel regions of top GAA-FETs. In various embodiments, the first semiconductor layers 116L and the second semiconductor layers 115L are made of different materials selected from the group consisting of Si, Ge, Sn, Si1-xGex, Ge1-ySny, Si1-x-yGexSny, III-V compound, and combinations thereof. Because of the material difference, in subsequent processing, the first semiconductor layers 116L can be selectively etched without substantially etching the second semiconductor layers 115L. In some embodiments, the channel layers 115L are formed of a different material than the nanosheets 102 of the bottom GAA transistor TR1. For example, the nanosheets 102 may be Si nanosheets, while the channel layers 115L are GeSn layers, which allows the subsequently formed top transistor TR2 having different channel materials than the bottom transistor TR1.
In
The fin structure FN2 may be patterned by any suitable method. For example, a hard mask 117 (e.g., formed of SiO2) is first formed over the top epitaxial stack TE by using suitable deposition and patterning techniques, followed by patterning the top epitaxial stack TE into the fin structure FN2 by one or more etching processes using the hard mask 117 as an etch mask. While each of the fin structure FN2 is illustrated as having a consistent width throughout, in other embodiments, the fin structures FN2 may have tapered sidewalls such that a width of the fin structure FN2 continuously increases in a direction towards the crystalline silicon layer 114. In such embodiments, each of the nanostructures 115, 116 may have a different width and be trapezoidal in shape.
In
A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures 115, 116. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process is performed until a topmost one of the first nanostructures 116 such that a top surface of the topmost one of the first nanostructures 116 and the insulation material are level after the planarization process is complete. In this way, the hard mask 117 can be removed by the planarization process.
The insulation material is then recessed to form the STI regions 118. The insulation material is recessed such that an upper portion of the fin structure FN2 protrudes from between neighboring STI regions 118. Further, the top surfaces of the STI regions 118 may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions 118 may be formed flat, convex, and/or concave by an appropriate etch. The STI regions 118 may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fin structure FN2. For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used.
In
The mask layer 120 may be patterned using acceptable photolithography and etching techniques. The pattern of the mask layer 120 then may be transferred to the dummy gate layer and to the dummy dielectric layer to form the dummy gate structure 119. The dummy gate structure 119 covers respective the channel region of the fin structure FN2. The dummy gate structure 119 may also have a lengthwise direction substantially perpendicular to the lengthwise direction of the fin structure FN2.
In
Next, exposed portions of the fin structure FN2 that laterally extend beyond the hard mask layer 120 and the gate spacers 121 are etched to form source/drain recesses R2 at opposite sides of the dummy gate structure 119, by using the hard mask layer 120 and the gate spacers 121 as an etch mask. Thereafter, portions of sidewalls of the layers in the fin structure FN2 formed of the first semiconductor materials (e.g., the first nanostructures 101) exposed by the source/drain recesses R2 are etched to form sidewall recesses between corresponding second nanostructures 115, followed by forming inner spacers 121s in the sidewall recesses. The resulting structure is illustrated in
The inner spacers 121s may be formed by, for example, depositing an inner spacer material layer in the sidewall recesses by using a conformal deposition process, such as CVD, ALD, or the like, followed by anisotropically etching the inner spacer layer to remove excessive inner spacer materials outside the sidewall recesses, while leaving the remaining inner spacer materials in the sidewall recesses to serve as the inner spacers 121s. The inner spacers 121s may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. Although outer sidewalls of the inner spacers 121s are illustrated as being flush with sidewalls of the second nanostructures 115, the outer sidewalls of the inner spacers 121s may extend beyond or be recessed from sidewalls of the second nanostructures 115.
In
In some embodiments, the epitaxial source/drain regions 122 may include any acceptable material appropriate for n-type GAA-FETs. For example, if the second nanostructures 116 are silicon, the epitaxial source/drain regions 122 may include materials exerting a tensile strain on the second nanostructures 115, such as silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. In some embodiments, the epitaxial source/drain regions 122 may include any acceptable material appropriate for p-type GAA-FETs. For example, if the second nanostructures 115 are silicon, the epitaxial source/drain regions 122 may comprise materials exerting a compressive strain on the second nanostructures 115, such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions 122 may be implanted with an n-type dopant (e.g., phosphorus) to form n-type source/drain regions or a p-type dopant (e.g., boron) to form p-type source/drain regions, followed by an anneal. In some embodiments, the epitaxial source/drain regions 122 may be in situ doped during growth. In some embodiments, the top source/drain regions 122 have different types of dopant than the bottom source/drain regions 108, which allows the subsequently formed top transistor TR2 being formed of a different conductivity type than the bottom transistor TR1. For example, the bottom source/drain regions 108 may include Si: P to serve as n-type source/drain regions, while the top source/drain regions 122 may include SiGe: B to serve as p-type source/drain regions.
In
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Next, the first nanostructures 116 in the gate trench GT2 are removed by an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the first nanostructures 116. Stated differently, the first nanostructures 116 are removed by using a selective etching process that etches the first nanostructures 116 at a faster etch rate than it etches the second nanostructures 115, thus forming spaces between the second nanostructures 115 (also referred to as sheet-to-sheet spaces if the nanostructures 115 are nanosheets). This step can be referred to as a channel release process. At this interim processing step, the spaces between second nanostructures 115 may be filled with ambient environment conditions (e.g., air, nitrogen, etc). In some embodiments, the second nanostructures 115 can be referred to as nanosheets, nanowires, nanoslabs, nanorings having nano-scale size (e.g., a few nanometers), depending on their geometry. For example, in some embodiments the second nanostructures 115 may be trimmed to have a substantial rounded shape (i.e., cylindrical) due to the selective etching process for completely removing the first nanostructures 116. In that case, the resultant second nanostructures 115 can be called nanowires. In embodiments in which the first nanostructures 116 include, e.g., SiGe, and the second nanostructures 115 include, e.g., Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) or the like may be used to remove the first nanostructures 116. In some embodiments, the second nanostructures 115 (also referred to as nanosheets) each have a thickness in a range from about 0.1 nm to about 100 nm, and a width in a range from about 0.1 nm to about 100 nm. In some embodiments, the cross-section profile of the second nanostructures 115 can be rectangular, square, circular, diamond, etc., with or without rounded corners. In some embodiments, the number of the nanostructures 115 in the top transistor TR2 is different from the number of the nanostructures 102 in the bottom transistor TR1.
In some embodiments, the high-k gate dielectric layer 124 includes silicon carbonnitride (SiCN) with a dielectric constant of about 4.9, silicon nitride (Si3N4) with a dielectric constant of about 7.1, aluminum oxide (Al2O3) with a dielectric constant of about 9, silicon oxide (SiO2) with a dielectric constant (i.e., k value) of about 3.9, hafnium oxide (HfO2) with a dielectric constant of about 20, zirconium oxide (ZrO2) with a dielectric constant of about 40, titanium oxide (TiO2) with a dielectric constant of about 95, tantalum oxide (Ta2O5) with a dielectric constant of about 26, hafnium zirconium oxide (H2O) with a dielectric constant of about 20 to about 45, lead zirconate titanate (PZT), e.g., PbZr0.52Ti0.48O3, with a dielectric constant of about 1400 to about 1800, yttrium oxide (Y2O3) with a dielectric constant of about 14 to about 18, poly[(vinylidenefluoride-co-trifluoroethylene] (P (VDF/TrFE)) with a dielectric constant of about 14-18, and/or barium titanium oxide (BaTiO3) with a dielectric constant greater than about 200.
In some embodiments, the work function metal layer 125 includes one or more n-type work function metal (N-metal) layers and/or one or more p-type work function metal (P-metal) layers. The n-type work function metal may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and/or other suitable materials. The p-type work function metal may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials. In some embodiments, the fill metal 126 may exemplarily include, but are not limited to, Pt, Ti, TiN, Al, W, WN, Ru, RuO, Ta, Ni, Co, Cu, Ag, Au, or other suitable materials. In some embodiments where the bottom transistor TRI and the top transistor TR2 are of different conductivity types, the bottom gate structure GS1 may have a different work function metal composition than the top gate structure GS2. For example, the work function metal layer 125 the top gate structure GS2 may include one or more metals different from that of the work function metal layer 111 of the bottom gate structure GS1.
After forming the replacement gate structure GS2, a refill dielectric 123s is deposited over the replacement gate structure GS2. In some embodiments, the refill dielectric 123s may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric material(s) of the refill dielectric 123s may be the same as that of the ILD layer 123. For example, the refill dielectric 123s may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. The refill dielectric 123s and the previously formed ILD layer 123 are distinguished by using dash lines in
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In the foregoing embodiments, the 3D IC structure includes GAA transistors at different level heights. However, in some other embodiments, planar transistors, FinFETs, or fork-sheet transistors can also be used for the 3D IC structure. Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that the 3D IC structure comprising bottom-tier transistors and top-tier transistors can be formed without wafer bonding. Another advantage is that the 3D IC structure utilizes a laser-liquid-phase-epitaxy technique to create an epitaxial layer above the bottom-tier transistors, which can function as a seed layer, enabling the growth of an epitaxial stack for fabricating top-tier transistors on an elevated level.
In some embodiments, a method includes forming a first transistor on a substrate, forming a first dielectric layer over the first transistor, forming a first trench in the first dielectric layer, depositing an amorphous semiconductor layer in the first trench and over the first dielectric layer, crystallizing the amorphous semiconductor layer into a crystalline semiconductor layer, and forming a second transistor over the crystalline semiconductor layer. A bottom of the first trench is at the substrate. In some embodiments, a second trench is formed in the first dielectric layer. A bottom of the second trench is at the substrate. The first transistor is laterally between the first trench and the second trench. In some embodiments, the amorphous semiconductor layer is further deposited in the second trench. In some embodiments, a chemical mechanical polish (CMP) process is performed to remove a protrusion from the crystalline semiconductor layer. In some embodiments, the second transistor has a channel material different from a channel material of the first transistor. In some embodiments, the first transistor and the second transistor are of different conductivity types. In some embodiments, the amorphous semiconductor layer is crystallized into the crystalline semiconductor layer by using a laser anneal. In some embodiments, the laser anneal is performed such that the amorphous semiconductor layer is turned into a liquid phase. In some embodiments, forming the second transistor includes forming an epitaxial stack on the crystalline semiconductor layer, the epitaxial stack comprising first semiconductor layers and second semiconductor layers alternating with the first semiconductor layers; forming a dummy gate structure over the epitaxial stack; forming gate spacers on opposite sides of the dummy gate structure; etching portions of the epitaxial stack that are not covered by the dummy gate structure and the gate spacers; after etching the portions of the epitaxial stack, forming epitaxial source/drain regions on the crystalline semiconductor layer; removing the dummy gate structure and the first semiconductor layers; and forming a gate structure surrounding the semiconductor layers. In some embodiments, the method further includes forming a second dielectric layer over the second transistor, forming a first via extending in the second dielectric layer to the second transistor, and forming a second via extending in the first dielectric layer and the second dielectric layer to the first transistor. In some embodiments, the method further includes forming metal vias and metal lines in the first dielectric layer prior to forming the first trench in the first dielectric layer.
In some embodiments, a method includes forming a first transistor on a substrate, forming a dielectric layer over the substrate; etching a first trench in the dielectric layer until the substrate is exposed in the first trench; forming an amorphous semiconductor material in the first trench and over the dielectric layer; performing an anneal process on the amorphous semiconductor material, the anneal process turning the amorphous semiconductor material into a crystalline semiconductor material; forming an epitaxial stack on the crystalline semiconductor material, the epitaxial stack comprising first semiconductor layers and second semiconductor layers alternating with the first semiconductor layers; and replacing the first semiconductor layers with a gate structure.
In some embodiments, an IC structure includes a first transistor, a second transistor, a first dielectric layer, a first crystalline semiconductor plug, a crystalline semiconductor lateral portion. The first transistor is over a substrate. The second transistor is at a different level height than the first transistor. The first dielectric layer interposes the first transistor and the second transistor. The first crystalline semiconductor plug extends through the first dielectric layer. The crystalline semiconductor lateral portion extends along a top surface of the first dielectric layer. The second transistor is formed over the crystalline semiconductor lateral portion, and the crystalline semiconductor lateral portion is formed of a same material as the first crystalline semiconductor plug. In some embodiments, the crystalline semiconductor plug is spaced apart from the crystalline semiconductor lateral portion. In some embodiments, the crystalline semiconductor plug is in contact with the substrate. In some embodiments, the IC structure further includes a second crystalline semiconductor plug extending through the first dielectric layer. The first transistor is laterally between the first crystalline semiconductor plug and the second crystalline semiconductor plug. In some embodiments, the IC structure further includes a second dielectric layer over the second transistor, and metal vias in the second dielectric layer.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.