Patent Application
20240250023
The present disclosure relates generally to the field of semiconductor devices, and particularly to methods for forming a three-dimensional memory device including expanded support openings and double spacer word line contact formation, and structures formed by the same.
A three-dimensional memory device including three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
According to an aspect of the present disclosure, a memory device is provided, which comprises: at least one alternating stack of insulating layers and electrically conductive layers; memory stack structures vertically extending through the at least one alternating stack, wherein each of the memory stack structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel; an electrically conductive layer contact via structure vertically extending through an upper portion of the at least one alternating stack and contacting a top surface of one of the electrically conductive layers; a plurality of support pillar structures having at least a dielectric outer sidewall vertically extending through each layer within the at least one alternating stack and contacting a respective first sidewall segment of the layer contact via structure; and a plurality of dielectric spacers vertically extending through the upper portion of the at least one alternating stack and contacting a respective second sidewall segment of the layer contact via structure.
According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method comprises: forming a first alternating stack of first insulating layers and first sacrificial material layers over a substrate; forming first sacrificial pillar structures through the first alternating stack; forming a first via cavity through a subset of layers within the first alternating stack; forming a first sacrificial via fill structure in a volume of the first via cavity; forming pillar cavities by removing at least the first sacrificial pillar structures; laterally expanding at least some of the pillar cavities by performing at least one isotropic etch process; forming dielectric pillar structures in the laterally expanded pillar cavities; replacing the first sacrificial material layers with first electrically conductive layers; and replacing the via-shaped material portion with an electrically conductive layer contact via structure that directly contacts a top surface of one of the first electrically conductive layers.
According to yet another aspect of the present disclosure, a device structure is provided, which comprises: at least one alternating stack of respective insulating layers and respective electrically conductive layers that are interlaced along a vertical direction; memory stack structures vertically extending through the at least one alternating stack, wherein each of the memory stack structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel; and an electrically conductive layer contact via structure vertically extending through an upper portion of the at least one alternating stack and contacting a top surface of one of the electrically conductive layers, wherein the layer contact via structure is electrically isolated from each electrically conductive layer within the at least one alternating stack that overlies the one of the electrically conductive layers by a set of at least one dielectric isolation structure that comprises a first dielectric spacer, and wherein a sidewall of the layer contact via structure comprises a first straight sidewall segment that contacts a first portion of the first dielectric spacer and a first convex surface segment that contacts a concave surface of a second portion of the first dielectric spacer.
According to still another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method comprises: forming a first alternating stack of first insulating layers and first sacrificial material layers over a substrate; forming a first via cavity through a subset of layers within the first alternating stack; forming a layer stack of a dielectric spacer material layer and a sacrificial spacer material layer in the first via cavity and over the first alternating stack; forming a tubular sacrificial spacer by anisotropically etching the sacrificial spacer material layer; performing an isotropic etch process that etches a material of the dielectric spacer material layer selective to a material of the tubular sacrificial spacer, wherein a remaining portion of the dielectric spacer material layer comprises a main dielectric spacer portion; removing the tubular sacrificial spacer; forming a first sacrificial via fill structure in a void in the first via cavity; replacing the first sacrificial material layers with first electrically conductive layers; and replacing the first sacrificial via fill structure with an electrically conductive layer contact via structure that directly contacts a top surface of one of the first electrically conductive layers.
As discussed above, the embodiments of the present disclosure are directed to a three-dimensional memory device and methods of forming the same including expanded support openings and double spacer word line contact formation, the various aspects of which are now described in detail.
The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The term “at least one” element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.
The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition and the same function. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. If two or more elements are not in direct contact with each other or from each other, the two elements are “disjoined from” each other or “disjoined among” one another. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the first element and the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.
As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the first continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the first continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.
As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface overlies or underlies the first surface and there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from a vertical direction by an angle less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction, and may or may not, include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.
As used herein, a “memory level” or a “memory array level” refers to the level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including topmost surfaces of an array of memory elements and a second horizontal plane including bottommost surfaces of the array of memory elements. As used herein, a “through-stack” element refers to an element that vertically extends through a memory level.
As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−5 S/m to 1.0 S/m in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/m to 1.0×107 S/m upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105 S/m. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−5 S/m. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to provide electrical conductivity greater than 1.0×105 S/m. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10−5 S/m to 1.0×107 S/m. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.
Generally, a semiconductor package (or a “package”) refers to a unit semiconductor device that may be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or a “chip”) or a plurality of semiconductor chips that are bonded throughout, for example, by flip-chip bonding or another chip-to-chip bonding. A package or a chip may include a single semiconductor die (or a “die”) or a plurality of semiconductor dies. A die is the smallest unit that may independently execute external commands or report status. Typically, a package or a chip with multiple dies is capable of simultaneously executing as many number of external commands as the total number of dies therein. Each die includes one or more planes. Identical concurrent operations may be executed in each plane within a same die, although there may be some restrictions. In case a die is a memory die, i.e., a die including memory elements, concurrent read operations, concurrent write operations, or concurrent erase operations may be performed in each plane within a same memory die. In a memory die, each plane contains a number of memory blocks (or “blocks”), which are the smallest unit that may be erased by in a single erase operation. Each memory block contains a number of pages, which are the smallest units that may be selected for programming. A page is also the smallest unit that may be selected to a read operation.
Referring to
An alternating stack of first material layers and second material layers is subsequently formed. Each first material layer may include a first material, and each second material layer may include a second material that is different from the first material. In case at least another alternating stack of material layers is subsequently formed over the alternating stack of the first material layers and the second material layers, the alternating stack is herein referred to as a first alternating stack. The level of the first alternating stack is herein referred to as a first-tier level, and the level of the alternating stack to be subsequently formed immediately above the first-tier level is herein referred to as a second-tier level, etc.
The first alternating stack may include first insulting layers 132 as the first material layers, and first spacer material layers as the second material layers. In one embodiment, the first spacer material layers may be sacrificial material layers that are subsequently replaced with electrically conductive layers. In another embodiment, the first spacer material layers may be electrically conductive layers that are not subsequently replaced with other layers. While an embodiment is described in which sacrificial material layers are replaced with electrically conductive layers, alternative embodiments in which the spacer material layers are formed as electrically conductive layers (thereby obviating the need to perform replacement processes) are expressly contemplated herein.
In one embodiment, the first material layers and the second material layers may be first insulating layers 132 and first sacrificial material layers 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. As used herein, a “sacrificial material” refers to a material that is removed during a subsequent processing step.
As used herein, an alternating stack of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of the first elements that is not an end element of the alternating plurality is adjoined by two instances of the second elements on both sides, and each instance of the second elements that is not an end element of the alternating plurality is adjoined by two instances of the first elements on both ends. The first elements may have the same thickness throughout, or may have different thicknesses. The second elements may have the same thickness throughout, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of the first material layers or with an instance of the second material layers, and may end with an instance of the first material layers or with an instance of the second material layers. In one embodiment, an instance of the first elements and an instance of the second elements may form a unit that is repeated with periodicity within the alternating plurality.
The first alternating stack (132, 142) may include first insulating layers 132 composed of the first material, and first sacrificial material layers 142 composed of the second material, which is different from the first material. The first material of the first insulating layers 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layers 132 include, but are not limited to silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first insulating layers 132 may be silicon oxide.
The second material of the first sacrificial material layers 142 is a sacrificial material that may be removed selective to the first material of the first insulating layers 132. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material.
The first sacrificial material layers 142 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layers 142 may be subsequently replaced with electrically conductive electrodes which may function, for example, as control gate electrodes of a vertical NAND device. In one embodiment, the first sacrificial material layers 142 may be material layers that comprise silicon nitride.
In one embodiment, the first insulating layers 132 may include silicon oxide, and sacrificial material layers may include silicon nitride sacrificial material layers. The first material of the first insulating layers 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layers 132, tetraethylorthosilicate (TEOS) may be used as the precursor material for the CVD process. The second material of the first sacrificial material layers 142 may be formed, for example, CVD or atomic layer deposition (ALD).
The thicknesses of the first insulating layers 132 and the first sacrificial material layers 142 may be in a range from 20 nm to 50 nm, although lesser and greater thicknesses may be used for each first insulating layer 132 and for each first sacrificial material layer 142. The number of repetitions of the pairs of a first insulating layer 132 and a first sacrificial material layer 142 may be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions may also be used. In one embodiment, each first sacrificial material layer 142 in the first alternating stack (132, 142) may have a uniform thickness that is substantially invariant within each respective first sacrificial material layer 142. In one embodiment, the bottommost layer of the first alternating stack (132, 142) may be the bottommost one of the first insulating layers 132, which is herein referred to as a bottommost first insulating layer 132B or a bottommost insulating layer. The topmost layer of the first alternating stack (132, 142) may be a topmost one of the first insulating layers, which is herein referred to as a topmost first insulating layer 132T.
Referring to
The first memory openings 149 are openings that are formed in the memory array region 100 through each layer within the first alternating stack (132, 142) and are subsequently used to form memory stack structures therein. The first memory openings 149 may be formed in rows of first memory openings 149 that are arranged along a first horizontal direction (e.g., word line direction) hd1. Clusters of first memory openings 149 may be laterally spaced apart along a second horizontal direction (e.g., bit line direction) hd2. Each cluster of first memory openings 149 may comprise multiple rows of first memory openings 149. In one embodiment, each cluster of first memory openings 149 may be formed as a two-dimensional array of first memory openings 149.
The primary first support openings 129 are openings that are formed in areas around layer contact via structures to be subsequently formed. Primary dielectric support pillar structures can be subsequently formed in and around the areas of the primary first support openings 129. The supplementary first support openings 139 are optional openings that may be subsequently formed in areas distal from layer contact via structures to be subsequently formed. Supplementary dielectric support pillar structures may subsequently be formed in the supplementary first support openings 139. The supplementary first support openings 139 and the supplementary dielectric support pillar structures are optional structures, and as such, may be omitted. In one embodiment, the pattern of the various first-tier openings (149, 139, 129) may be formed with a periodicity along the second horizontal direction hd2 such that a pattern in a repetition unit RU is repeated along the second horizontal direction hd2 with a periodicity.
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In one embodiment, the first sacrificial fill material may include a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. In another embodiment, the first sacrificial fill material may include a silicon oxide material having a higher etch rate than the materials of the first insulating layers 132. For example, the first sacrificial fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etch rate that is at least 100 times higher than the etch rate of densified TEOS oxide (i.e., a silicon oxide material formed by decomposition of tetraethylorthosilicate glass in a chemical vapor deposition process and subsequently densified in an anneal process) in a 100:1 dilute hydrofluoric acid. In this case, a thin etch stop liner (such as a silicon nitride layer having a thickness in a range from 1 nm to 3 nm) may be used prior to depositing the first sacrificial fill material. The first sacrificial fill material may be formed by a non-conformal deposition or a conformal deposition method. In yet another embodiment, the first sacrificial fill material may include a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently removed selective to the materials of the first alternating stack (132, 142).
Portions of the deposited sacrificial material may be removed from above the topmost layer of the first alternating stack (132, 142) by a planarization process. The planarization process may include a recess etch, chemical mechanical planarization (CMP), or a combination thereof. Remaining portions of the first sacrificial fill material comprise first sacrificial opening fill structures {(145, 147), (135, 137), (125, 127)}. For example, a first sacrificial memory opening fill structure (145, 147) may be formed in each first memory opening 149. A primary first sacrificial pillar structure (125, 127) may be formed in each primary first sacrificial opening 129. A supplementary first sacrificial pillar structure (135, 137) may be formed in each supplementary first sacrificial opening 139. Each first sacrificial memory opening fill structure (145, 147) may comprise an optional first etch stop liner 145 and a first sacrificial memory opening fill material portion 147. Each primary first sacrificial pillar structure (125, 127) may comprise an optional first etch stop liner 125 and a primary first sacrificial fill material portion 127. Each supplementary first sacrificial pillar structure (135, 137) may comprise an optional first etch stop liner 135 and a supplementary first sacrificial fill material portion 137. The top surfaces of the first sacrificial opening fill structures {(145, 147), (135, 137), (125, 127)} may be coplanar with the top surface of the topmost first insulating layer 132T. Each of the first sacrificial opening fill structures {(145, 147), (135, 137), (125, 127)} may or may not, include cavities therein.
Referring to
For example, a patterned hard mask layer (not shown) can be formed over the first alternating stack (132, 142) such that openings extend through the patterned hard mask layer in areas in which the first via cavities 189 are to be subsequently formed. In case the total number of the first sacrificial material layers 142 is less than 2N in which P is a positive integer, a combination of an etch mask formation process and an anisotropic etch process may be repeated N times with variations in the patterns of openings in the etch masks and with changes in the duration of the anisotropic etch processes. The integer N may be in integer from 2 to 10, such as from 3 to 8. The first via cavities 189 are formed in areas of the openings in the patterned hard mask layer.
For each i-th iteration of the combination of an etch mask formation process and an anisotropic etch process for which the integer i runs from 1 to N, an i-th masking layer, such as an i-th photoresist, can be applied over the patterned hard mask layer (not illustrated), and can be lithographically patterned to form openings therethrough. The areas of the pattern of the openings in the i-th masking layer includes areas of an i-th subset of the mask openings in the patterned hard mask layer. In one embodiment, the i-th subset of the mask openings may comprise about one half of all i-th subset of the mask openings.
An i-th anisotropic etch process can be performed to transfer the pattern of the openings in the i-th masking layer through a respective set of F(i) first insulating layers 132 and F(i) first sacrificial material layers 142 within each opening in the i-th masking layer. In one embodiment, each function F(i) may have a different positive integer value for each integer value i. In one embodiment, the value of each function F(i) may be positive integers that are integer powers of 2. In an illustrative example, F(i) may be 2(i−1) . In another example, F(i) may be 2(N−i). In yet another example, the set of all values for F(i), 0<i<N+1, may include all integer powers of 2 between 1 and 2N−1 in any order. In still another example, the set of all values of F(i) may include any set of non-overlapping positive integers less than 2N−1.
In one embodiment, the first insulating layers 132 can include silicon oxide and the first sacrificial material layers 142 can include a sacrificial material, such as silicon nitride. In this case, an anisotropic etch process that etches F(i) pairs of first insulating layers 132 and first sacrificial material layers 142 can include F(i) iterations of a first anisotropic etch step that etches the sacrificial material of the first sacrificial material layers 142 selective to silicon oxide, and a second anisotropic etch step that etches silicon oxide selective to the sacrificial material of the first sacrificial material layers 142. The i-th subset of the first via cavities 189 can be vertically extended through a respective contiguous set of F(i) first sacrificial material layers 142 and F(i) first insulating layers 132. The i-th subset of the first via cavities 189 can be vertically extended through a respective contiguous set of F(i) first sacrificial material layers 142 and F(i) first insulating layers 132. The i-th masking layer can be subsequently removed, for example, by ashing and/or selective etching.
Generally, the masking patterns for the N masking layers (which may be N patterned photoresist layers) and the set of values for F(i), 0<i<N+1, may be selected such that the first via cavities 189 (which are formed underneath the mask openings a respective patterned photoresist layer) have different depths. In one embodiment, the masking patterns for the N masking layers (which may be N patterned photoresist layers) and the set of values for F(i), 0<i<N+1, may be selected such that each first insulating layer 132 other than the bottommost first insulating layer 132B is physically exposed to a respective first via cavity 189.
The patterned hard mask layer can be removed after formation of the first via cavities 189. Generally, each first via cavity 189 can be formed through a respective subset of layers within the first alternating stack (132, 242). It is understood that only a subset of the first via cavities 189 is illustrated in the drawings.
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The sacrificial spacer material layer 822L comprises a material that may be removed selective to the material of the dielectric spacer material layer 821L. For example, the sacrificial spacer material layer 822L may comprise a semiconductor material, such as amorphous silicon or polysilicon. The sacrificial spacer material layer 822L may have a second thickness t2, which can be measured along a horizontal direction on a sidewall of the first insulating layers 132 (such as the topmost first insulating layer 132T). The second thickness may be in a range from 20 nm to 200 nm, such as from 40 nm to 100 nm, although lesser and greater thicknesses may also be employed.
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A contoured etch front develops during the isotropic etch process underneath each void 189′ in the first via cavities 189. Thus, each main dielectric spacer portion 821 comprises a respective concave annular surface segment 821C that is located below the tubular sacrificial spacers 822 and is physically exposed to a respective void 189′. In one embodiment, each main dielectric spacer portion 821 may comprise at least one annular dielectric fin 821F that fills a respective annular lateral recess 142R and contacts a cylindrical sidewall of a respective one of the first sacrificial material layers 142. In one embodiment, a subset of the main dielectric spacer portions 821 may comprise a respective plurality of annular dielectric fins 821F. Such main dielectric spacer portions 821 may have a vertical cross-sectional profile in which a plurality of annular dielectric fins 821F laterally protrude outward to contact a subset of the first sacrificial material layers 142.
Referring to
The tubular sacrificial spacers 822 can be removed selective to the materials of the first sacrificial material layers 142 and the main dielectric spacer portions 821. For example, if the tubular sacrificial spacers 822 comprise polysilicon or amorphous silicon, a wet etch process using hot trimethyl-2 hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) may be employed to remove the tubular sacrificial spacers 822. The patterned etch mask layer 117 may be subsequently removed, for example, by ashing.
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According to an aspect of the present disclosure, one, a plurality and/or each of the first sacrificial via fill structures 183 may comprise a respective straight sidewall segment 183S and a respective convex surface segment 183C that is adjoined to a bottom periphery of the respective straight sidewall segment. The respective convex surface 183C segment laterally protrudes outward relative to the respective straight sidewall segment 183S.
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The second sacrificial opening fill structures {(245, 247), (235, 237), (225, 227)} may comprise second sacrificial memory opening fill structures (245, 247) that are formed in the second memory opening, primary second sacrificial pillar structure (225, 227) that are formed in the primary second sacrificial opening, and supplementary second sacrificial pillar structure (235, 237) that are formed in the supplementary second sacrificial openings. Each second sacrificial memory opening fill structure (245, 247) may comprise an optional second etch stop liner 245 and a second sacrificial memory opening fill material portion 247. Each primary second sacrificial pillar structure (225, 227) may comprise an optional second etch stop liner 225 and a primary second sacrificial fill material portion 227. Each supplementary second sacrificial pillar structure (235, 237) may comprise an optional second etch stop liner 235 and a supplementary second sacrificial fill material portion 237. The top surfaces of the second sacrificial opening fill structures {(245, 247), (235, 237), (225, 227)} may be coplanar with the top surface of the topmost second insulating layer 232T. Each of the second sacrificial opening fill structures {(245, 247), (235, 237), (225, 227)} may, or may not, include cavities therein.
Referring to
A second subset of the second via cavities 289 may be formed at the first layer contact via locations LCV1. Each second via cavity 289 within the second subset of the second via cavities 289 may be formed such that a top surface of a first sacrificial via fill structure 183 is physically exposed underneath each second via cavity 289 within the second subset of the second via cavities 289. In one embodiment, each of the first sacrificial via fill structures 183 may be exposed underneath a respective second via cavity 289 within the second subset of the second via cavities 289. Alternatively, rather than separately forming the first via cavities 189 prior to forming the second alternating stack (232, 242) and then forming the second via cavities 289 after forming the second alternating stack (232, 242), combined first and second via cavities (189, 289) may be formed during the same etching step after forming the second alternating stack (232, 242).
Generally, each second via cavity 289 within the first subset of the second via cavities 289 may be formed by performing a respective anisotropic etch process including a respective terminal etch step that etches one of the second sacrificial material layers 242 selective to a material of the second insulating layers 232. A horizontal top surface of a second insulating layer 232 can be physically exposed at the bottom of each second via cavity 289 within the first subset of the second via cavities. Each second via cavity 289 within the second subset of the second via cavities 289 may be formed through each layer of the second alternating stack (232, 242) such that a top surface of a first sacrificial via fill structure 183 is exposed underneath each second via cavity 289 within the second subset of the second via cavities 289.
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In one embodiment, the first thickness t1′ may be in a range from 1 times the thickness of each second sacrificial material layer 242 to 6 times the thickness of each second sacrificial material layer 242. Each annular lateral recess is filled with the dielectric spacer material layer 821L.
The sacrificial spacer material layer 822L comprises a material that may be removed selective to the material of the dielectric spacer material layer 821L. For example, the sacrificial spacer material layer 822L may comprise a semiconductor material such as amorphous silicon or polysilicon. The sacrificial spacer material layer 822L may have a second thickness t2′, which can be measured along a horizontal direction on a sidewall of the second insulating layers 232. The second thickness may be in a range from 20 nm to 200 nm, such as from 40 nm to 100 nm, although lesser and greater thicknesses may also be employed.
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A contoured etch front develops during the isotropic etch process underneath each void 289′ in the second via cavities 289. Thus, each main dielectric spacer portion 821 comprises a respective concave annular surface segment that is physically exposed to a respective void 289′. In one embodiment, each main dielectric spacer portion 821 may comprise at least one annular dielectric fin that fills a respective annular lateral recess and contacts a cylindrical sidewall of a respective one of the second sacrificial material layers 242. In one embodiment, a subset of the main dielectric spacer portions 821 may comprise a respective plurality of annular dielectric fins. Such main dielectric spacer portions 821 may have a vertical cross-sectional profile in which a plurality of annular dielectric fins laterally protrude outward to contact a subset of the second sacrificial material layers 242. An inner sidewall of one, a plurality and/or each of the first dielectric spacers 182 may be collaterally chamfered during the isotropic etch process.
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Portions of the second sacrificial via fill material layer 283 and the optional silicon oxide liner layer 824L that overlie the horizontal plane including the top surface of the topmost second insulating layer 232T may be removed by a planarization process, which may employ a chemical mechanical polishing process and/or a recess etch process. Each remaining portion of the second sacrificial via fill material layer constitutes a second sacrificial via fill structure 283. Each remaining portion of the silicon oxide liner layer 824L constitutes a silicon oxide liner 824. Each second sacrificial via fill structure 283 is laterally surrounded by a respective second dielectric spacer 282. Each second dielectric spacer 282 comprises a main dielectric spacer portion 821 and an optional silicon oxide liner 824, if present. In one embodiment, each second dielectric spacer 282 may be a tubular dielectric spacer having a tubular configuration and located within a peripheral portion of a respective second via cavity 289. Each second sacrificial via fill structure 283 can be formed inside a respective tubular dielectric spacer as embodied as a second dielectric spacer 282.
According to an aspect of the present disclosure, one, a plurality and/or each of the second sacrificial via fill structures 283 may comprise a respective straight sidewall segment and a respective convex surface segment that is adjoined to a bottom periphery of the respective straight sidewall segment. The respective convex surface segment laterally protrudes outward relative to the respective straight sidewall segment.
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The third sacrificial opening fill structures {(345, 347), (335, 337), (335, 337)} may comprise third sacrificial memory opening fill structures (345, 347) that are formed in the third memory opening, primary third sacrificial pillar structure (325, 327) that are formed in the primary third sacrificial opening, and supplementary third sacrificial pillar structure (335, 337) that are formed in the supplementary third sacrificial openings. Each third sacrificial memory opening fill structure (345, 347) may comprise an optional third etch stop liner 345 and a third sacrificial memory opening fill material portion 347. Each primary third sacrificial pillar structure (325, 327) may comprise an optional third etch stop liner 325 and a primary third sacrificial fill material portion 327. Each supplementary third sacrificial pillar structure (335, 337) may comprise an optional third etch stop liner 335 and a supplementary third sacrificial fill material portion 337. The top surfaces of the third sacrificial opening fill structures {(345, 347), (335, 337), (335, 337)} may be coplanar with the top surface of the topmost third insulating layer 332T. Each of the third sacrificial opening fill structures {(345, 347), (335, 337), (335, 337)} may, or may not, include cavities therein.
Each vertical stack of a first sacrificial memory opening fill structure (145, 147), a second sacrificial memory opening fill structure (245, 247), and a third sacrificial memory opening fill structure (345, 347) constitutes a sacrificial memory opening fill structure stack 47. Each vertical stack of a primary first sacrificial pillar structure (125, 127), a primary second sacrificial pillar structure (225, 227), and a primary third sacrificial pillar structure (325, 327) constitutes a primary sacrificial pillar structure stack 27. Each vertical stack of a supplementary first sacrificial pillar structure (135, 137), a supplementary second sacrificial pillar structure (235, 237), and a supplementary third sacrificial pillar structure (335, 337) constitutes a supplementary sacrificial pillar structure stack 37.
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Referring to
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A second subset of the third via cavities 389 may be formed at the second layer contact via locations LCV2 and at the first layer contact via locations LCV1. Each third via cavity 389 within the second subset of the third via cavities 389 may be formed such that a top surface of a second sacrificial via fill structure 283 is physically exposed underneath each third via cavity 389 within the second subset of the third via cavities 389. In one embodiment, each of the second sacrificial via fill structures 283 may be exposed underneath a respective third via cavity 389 within the second subset of the third via cavities 389.
Generally, each third via cavity 389 within the first subset of the third via cavities 389 may be formed by performing a respective anisotropic etch process including a respective terminal etch step that etches one of the third sacrificial material layers 342 selective to a material of the third insulating layers 332. A horizontal top surface of a third insulating layer 332 can be physically exposed at the bottom of each third via cavity 389 within the first subset of the third via cavities. Each third via cavity 389 within the second subset of the third via cavities 389 may be formed through each layer of the third alternating stack (232, 342) such that a top surface of a second sacrificial via fill structure 283 is exposed underneath each third via cavity 389 within the third subset of the third via cavities 389.
Referring to
An isotropic etch process can be performed, which etches the material of the dielectric spacer material layer selective to the material of the tubular sacrificial spacers 822. The duration of the isotropic etch process can be selected such that the isotropic etch process removes horizontally-extending portions of the dielectric spacer material layer underlying the third via cavities 389 and removes a third insulating layer 332 that underlies the horizontally-extending portions of the dielectric spacer material layer. Each remaining portion of the dielectric spacer material layer constitutes a dielectric spacer portion, which is herein referred to as main dielectric spacer portion 821. The isotropic etch process may be selective to the third sacrificial material layers 342. A top surface of a third sacrificial material layer 342 can be physically exposed at the bottom of each void 389′ in the first subset of the third via cavities 389. A top surface of a second sacrificial via fill structure 283 can be physically exposed at the bottom of each void 389′ in the second subset of the second via cavities 389.
A contoured etch front develops during the isotropic etch process underneath each void 389′ in the third via cavities 389. Thus, each main dielectric spacer portion 821 comprises a respective concave annular surface segment that is physically exposed to a respective void 389′. In one embodiment, each main dielectric spacer portion 821 may comprise at least one annular dielectric fin that fills a respective annular lateral recess and contacts a cylindrical sidewall of a respective one of the third sacrificial material layers 342. In one embodiment, a subset of the main dielectric spacer portions 821 may comprise a respective plurality of annular dielectric fins. Such main dielectric spacer portions 821 may have a vertical cross-sectional profile in which a plurality of annular dielectric fins laterally protrude outward to contact a subset of the third sacrificial material layers 342. An inner sidewall of one, a plurality and/or each of the second dielectric spacers 282 may be collaterally chamfered during the isotropic etch process.
The tubular sacrificial spacers 822 can be removed selective to the materials of the third sacrificial material layers 342 and the main dielectric spacer portions 821. A conformal silicon-containing layer may be optionally deposited over the exemplary structure directly on inner sidewalls of the main dielectric spacer portions 821 and directly on a top surface of the topmost third insulating layer 332T, and a thermal oxidation process can be performed to convert the conformal silicon-containing layer into a silicon oxide liner layer.
Subsequently, an anisotropic etch process may be performed to remove horizontally-extending portions of the silicon oxide liner layer. A top surface of a second sacrificial via fill structure 283 can be exposed underneath each third via cavity 389 within the second subset of the third via cavities 389. Each remaining portion of the silicon oxide liner layer 824L constitutes a silicon oxide liner 824. Each void 383′ is laterally surrounded by a respective third dielectric spacer 382. Each third dielectric spacer 382 comprises a main dielectric spacer portion 821 and an optional silicon oxide liner 824, if present. In one embodiment, each third dielectric spacer 382 may be a tubular dielectric spacer having a tubular configuration and located within a peripheral portion of a respective third via cavity 389.
According to an aspect of the present disclosure, one, a plurality and/or each of the voids 389′ may comprise a respective straight sidewall segment and a respective convex surface segment that is adjoined to a bottom periphery of the respective straight sidewall segment. The respective convex surface segment laterally protrudes outward relative to the respective straight sidewall segment.
Referring to
Referring to
While an embodiment is described in which each layer contact via cavity 89 is filled with a respective sacrificial via fill structure 83, an alternative embodiment is expressly contemplated herein in which each layer contact via cavity is filled with a respective set of at least one sacrificial via fill structure (183, 283, 383). In the alternative embodiment, the processing steps described with reference to
Referring to
Referring to
Referring to
Subsequently, the memory material layer 54 can be formed. Generally, the memory material layer may comprise any memory material such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store data bits in the form of presence or absence of electrical charges, a direction of ferroelectric polarization, electrical resistivity, or another measurable physical parameter. In one embodiment, the memory material layer 54 can be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the memory material layer 54 can include discrete floating gates of a conductive material, such as heavily doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions (e.g., floating gates), for example, by being formed within lateral recesses into sacrificial material layers (142, 242, 342). In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layers (142, 242, 342) and the insulating layers (132, 232, 332) can have vertically coincident sidewalls, and the memory material layer 54 can be formed as a single continuous layer.
In another embodiment, the sacrificial material layers (142, 242, 342) can be laterally recessed with respect to the sidewalls of the insulating layers (132, 232, 332), and a combination of a deposition process and an anisotropic etch process can be employed to form the memory material layer 54 as a plurality of memory material portions that are vertically spaced apart. While the present disclosure is described employing an embodiment in which the memory material layer 54 is a single continuous layer, embodiments are expressly contemplated herein in which the memory material layer 54 is replaced with a plurality of memory material portions (which can be charge trapping material portions or electrically isolated conductive material portions) that are vertically spaced apart. The memory material layer 54 can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. The thickness of the memory material layer 54 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.
Generally, any vertical stack of memory elements known in the art may replace the memory material layer 54. The vertical stack of memory elements can be formed at levels of the sacrificial material layers (142, 242, 342) within each memory opening 49, and may be formed as portions of a continuous memory material layer, or may be formed as discrete memory material portions.
The optional dielectric liner 56, if present, includes a dielectric material. In one embodiment, the optional dielectric liner 56 comprises a tunneling dielectric layer through which charge tunneling can be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The optional dielectric liner 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the optional dielectric liner 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the optional dielectric liner 56 can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the optional dielectric liner 56 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. The stack of the blocking dielectric layer 52, the memory material layer 54, and the optional dielectric liner 56 constitutes a memory film 50 that stores memory bits.
The semiconductor channel material layer 60L includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L includes amorphous silicon or polysilicon. The semiconductor channel material layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A cavity 49′ is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 60L).
Referring to
Referring to
Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region 63. The drain regions 63 can have a doping of a second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the drain regions 63 can be in a range from 5.0×1018/cm3 to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.
Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60 through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. An optional dielectric liner 56 is surrounded by a memory material layer 54, and laterally surrounds a vertical semiconductor channel 60. Each adjoining set of a blocking dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56 collectively constitute a memory film 50, which can store electrical charges with a macroscopic retention time. In some embodiments, a blocking dielectric layer 52 may not be present in the memory film 50 at this step, and a blocking dielectric layer may be subsequently formed after formation of backside recesses. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.
Each combination of a memory film 50 and a vertical semiconductor channel 60 within a memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a vertical semiconductor channel 60, a optional dielectric liner 56, a plurality of memory elements comprises portions of the memory material layer 54, and an optional blocking dielectric layer 52. Each combination of a memory stack structure 55, a dielectric core 62, and a drain region 63 within a memory opening 49 constitutes a memory opening fill structure 58.
While an embodiment is described in which three alternating stacks {(132, 142), (232, 242), (332, 342)} are formed over a substrate, embodiments are expressly contemplated herein in which one, two, or four or more alternating stacks are formed over a substrate. Generally, each of the memory stack structures 55 vertically extends through each layer within at least one alternating stack {(132, 142), (232, 242), (332, 342)}. Each of the memory stack structures 55 comprises a respective vertical stack of memory elements.
Referring to
Referring to
A patterned etch mask layer 87 (such as a patterned photoresist layer) can be applied over the contact-level dielectric layer 80, and is lithographically patterned to form discrete openings over the primary sacrificial pillar structure stacks 27. An anisotropic etch can be performed to form openings through the contact-level dielectric layer 80 so that each top surface of the primary sacrificial pillar structure stacks 27 is physically exposed.
Referring to
Referring to
As discussed above, the first sacrificial via fill structures 183 and the second sacrificial via fill structures 283 may or may not be replaced with the sacrificial via fill structures 83. In case the first sacrificial via fill structures 183 and the second sacrificial via fill structures 283 are replaced with the sacrificial via fill structures 83, surface segments of the sacrificial via fill structures 83 can be exposed to expanded pillar cavities 29′, which are pillar cavities formed by lateral expansion of the primary pillar cavities 29.
In case the first sacrificial via fill structures 183 and the second sacrificial via fill structures 283 are not replaced with sacrificial via fill structures 83 and a third sacrificial via fill structure fills each void 389′ as provided at the processing steps of
As used herein, a “via-shaped” material portion refers to a material portion having a top surface, a bottom surface, and vertically-extending surfaces that may be vertical, tapered, or may have lateral protrusions. In the instant case, the via-shaped material portions comprise at least one annular lateral protrusion having a respective annular convex surface.
In one embodiment, the at least one isotropic etch process employed to form the expanded pillar cavities 29′ may comprise an isotropic etch process that isotropically etches the insulating layers (132, 232, 332) and the sacrificial material layers (142, 242, 342) simultaneously. Alternatively, the at least one isotropic etch process employed to form the expanded pillar cavities 29′ may comprise a combination of a first isotropic etch process and a second isotropic etch process that is performed after, or prior to, the first isotropic etch process. The first isotropic etch process isotropically etches the sacrificial material layers (142, 242, 342) selective to the insulating layers (132, 232, 332) and selective to the via-shaped material portions (such as the sacrificial via fill structures 83), and the second isotropic etch process isotropically etches the insulating layers (132, 232, 332) selective to the sacrificial material layers (142, 242, 342) and selective to the via-shaped material portions (such as the sacrificial via fill structures 83).
In one embodiment, the duration(s) of the at least one isotropic etch process can be selected such that dielectric spacers (182, 282, 382) are etched through. In one embodiment, each of the dielectric spacers (182, 282, 382) may be formed as tubular dielectric spacers having a tubular configuration (and including ribbed outer sidewalls), and the at least one isotropic etch process may etch portions of the tubular dielectric spacer until sidewall segments of the via-shaped material portions are exposed. In this case, the tubular dielectric spacer is divided into a plurality of dielectric spacers (182, 282, 382) that are azimuthally spaced apart around the via-shaped material portions. In this case, a dielectric spacer (182, 282, 382) can be divided into a plurality of dielectric spacers (182, 282, 382) that are azimuthally spaced apart around a vertical axis VA passing through a center (e.g., geometrical center) GC of a respective via-shaped material portion (such as a sacrificial via fill structure 83).
In one embodiment, a plurality of surfaces of each via-shaped material portion (such as the sacrificial via fill structures 83) can be exposed to a respective subset of the expanded pillar cavities 29′ upon laterally expanding the primary pillar cavities 29. In one embodiment, each exposed surface of the via-shaped material portions (such as the sacrificial via fill structures 83) that is exposed to a respective one of the expanded pillar cavities 29′ continuously extends from a top surface of a respective via-shaped material portion to a bottom surface of the respective via-shaped material portion. The patterned etch mask layer 87 can be subsequently removed, for example, by ashing.
Referring to
In one embodiment, lower portions of the primary dielectric support pillar structures 20 extend below the sacrificial via structures filling the layer contact via cavities 89 while upper portions of the primary dielectric support pillar structures 20 may contact surface segments of the material portions occupying the sacrificial via structures filling the layer contact via cavities 89. The lower portions provide additional structural support to the in-process structure. The upper portions of the primary dielectric support pillar structures 20 may comprise a respective laterally-concave and vertically-straight surface that contacts a respective via-shaped material portion (such as a sacrificial via fill structure 83).
In one embodiment shown in
In one embodiment shown in
In some embodiments, the at least one alternating stack {(132, 142), (232, 242), (332, 342)} comprises M alternating stacks {(132, 142), (232, 242), (332, 342)}, in which M is an integer greater than 1; and the plurality of dielectric spacers (182, 282, 382) comprises a total of M×P dielectric spacers (182, 282, 382). In the illustrated example shown in
In one embodiment, each of the plurality of dielectric support pillar structures 20 has a respective geometrical center GC and a respective vertical axis VA passing through the respective geometrical center GC; and each of the vertical axes VA of the plurality of dielectric support pillar structures 20 is laterally spaced from the vertical axis VA passing through the geometrical center GC of a respective via-shaped material portion by a greater lateral distance than any point within the plurality of dielectric spacers (182, 282, 382) is from the vertical axis VA passing through the geometrical center GC of the via-shaped material portion.
In one embodiment, each surface segment of a via-shaped material portion located below a horizontal surface including a topmost surface of the at least one alternating stack {(132, 142), (232, 242), (332, 342)} is in direct contact with one of plurality of dielectric support pillar structures 20 or with one of the plurality of dielectric spacers (182, 282, 382).
In one embodiment, each interface between a via-shaped material portion (such as a sacrificial via fill structure 83) and a plurality of dielectric support pillar structures 20 has a horizontal cross-sectional profile in which a convex surface segment of the via-shaped material portion is in direct contact with a concave surface segment of a respective one of the dielectric support pillar structures 20. In one embodiment, each of the plurality of dielectric support pillar structures 20 may be in in direct contact with a respective pair of dielectric spacers (182, 282, 382) among the plurality of dielectric spacers (182, 282, 382); and each of the plurality of dielectric spacers (182, 282, 382) may be in direct contact with a respective pair of dielectric support pillar structures 20.
In one embodiment, each of the plurality of dielectric support pillar structures 20 is in direct contact with each insulating layer (132, 232, 332) within the at least one alternating stack {(132, 142), (232, 242), (332, 342)}; and each insulating layer (132, 232, 332) within the at least one alternating stack {(132, 142), (232, 242), (332, 342)} that overlies a horizontal plane including the bottom surface of the via-shaped material portion may be in direct contact with at least two dielectric spacers (182, 282, 382) within the plurality of dielectric spacers (182, 282, 382).
In one embodiment, top surfaces of the plurality of dielectric support pillar structures 20 may be located within a horizontal plane including a top surface of the contact-level dielectric layer 80; and topmost surfaces of the plurality of dielectric spacers (182, 282, 382) may be located within a horizontal plane including top surfaces of the at least one alternating stack {(132, 142), (232, 242), (332, 342)}.
In one embodiment, each interface between a via-shaped material portion (such as a sacrificial via fill structure 83) and a respective one of the plurality of dielectric support pillar structures 20 vertically extends from a bottommost surface of the via-shaped material portion to a horizontal plane including a topmost surface of the at least one alternating stack {(132, 142), (232, 242), (332, 342)} without horizontally-extending surface segments.
Generally, a via-shaped material portion (such as a sacrificial via fill structure 83) vertically extends through a respective subset of layers within at least one alternating stack {(132, 142), (232, 242), (332, 342)}. In one embodiment, the via-shaped material portion is laterally surrounded by and is laterally contacted by a set of at least one dielectric isolation structure (182, 282, 382, 20).
In one embodiment, the via-shaped material portion (such as a sacrificial via fill structure 83) comprises a sidewall that includes a first straight sidewall segment that contacts a first portion of a first dielectric spacer 182 and a first convex surface segment that contacts a concave surface of a second portion of the first dielectric spacer 182. In one embodiment, a top periphery of the first convex surface segment is adjoined to a bottom periphery of the first straight sidewall segment. In one embodiment, the first convex surface segment laterally protrudes outward relative to the bottom periphery of the first straight sidewall segment. In one embodiment, the first convex surface segment laterally protrudes outward from a periphery of an interface between the via-shaped material portion and an underlying sacrificial material layer (142, 242, 342).
In one embodiment, the at least one alternating stack {(132, 142), (232, 242), (332, 342)} comprises a plurality of alternating stacks {(132, 142), (232, 242), (332, 342)} that are stacked along the vertical direction; the set of at least one dielectric isolation structure (182, 282, 382, 20) comprises at least one additional dielectric spacer (282, 382) that overlies the first dielectric spacer 182 and laterally surrounded by a respective alternating stack {(232, 242) or (332, 342)} among the plurality of alternating stacks {(132, 142), (232, 242), (332, 342)}; and each of the at least one additional dielectric spacer (282, 382) has a respective top surface located within a horizontal plane including a top surface of a respective alternating stack {(132, 142), (232, 242), or (332, 342)}. In one embodiment, the plurality of alternating stacks {(132, 142), (232, 242), (332, 342)} comprises a second alternating stack (232, 242) that overlies, and is in contact with, the first alternating stack (132, 242); the at least one additional dielectric spacer (282, 382) comprises a second dielectric spacer 282 that contacts the first dielectric spacer 182; and the sidewall of the via-shaped material portion comprises a second straight sidewall segment that contacts the second dielectric spacer 282 and a second convex surface segment that contacts a concave surface of the second dielectric spacer 282. In one embodiment, a top periphery of the second convex surface segment is adjoined to a bottom periphery of the second straight sidewall segment; and a bottom portion of the second convex surface segment is in contact with a chamfered surface of the first insulating spacer.
In one embodiment, a plurality of dielectric support pillar structures 20 vertically extends through each layer within the at least one alternating stack {(132, 142), (232, 242), (332, 342)} and contact a respective sidewall segment of the via-shaped material portion. In one embodiment, the set of at least one dielectric isolation structure (182, 282, 382, 20) comprises at least one additional first dielectric spacer 182 having a same vertical extent as the first dielectric spacer 182; and the first dielectric spacer 182 and the at least one additional first dielectric spacer 182 are azimuthally spaced apart around the layer contact via structure 86 and are not in direct contact among one another. In one embodiment, the first dielectric spacer 182 and the at least one additional first dielectric spacer 182 are azimuthally interlaced with the plurality of dielectric support pillar structures 20 around a vertical axis VA passing through a geometrical center GC of the via-shaped material portion (such as a sacrificial via fill structure 83).
In one embodiment, the first dielectric spacer 182 and the at least one additional first dielectric spacer 182 comprises P dielectric spacers 182; the plurality of dielectric support pillar structures 20 comprises P dielectric support pillar structures 20; P is an integer greater than 1; and each of the P dielectric spacers 182 is located within a respective azimuthal angle range (α1, α2, α3) around the vertical axis VA that has a magnitude less than 2π/P radian.
In one embodiment, each of the respective sidewall segment of the via-shaped material portion comprises: at least one straight sidewall segment that contacts a straight sidewall surface segment of a respective one of the plurality of dielectric support pillar structures 20; and at least one convex surface segment that contacts a concave surface segment of the respective one of the plurality of dielectric support pillar structures 20. In one embodiment, the at least one alternating stack {(132, 142), (232, 242), (332, 342)} comprises a plurality of alternating stacks {(132, 142), (232, 242), (332, 342)} that are stacked along the vertical direction; at least one straight sidewall segment comprises a plurality of straight sidewall segments; the at least one convex surface segment comprises a plurality of convex surface segments; and one of the plurality of convex surface segments intersects a horizontal plane including an interface between one of the plurality of alternating stacks {(132, 142), (232, 242), (332, 342)} and another of the alternating stacks {(132, 142), (232, 242), (332, 342)}.
Referring to
Referring to
The isotropic etch process can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trenches 79. For example, if the sacrificial material layers (142, 242, 342) include silicon nitride, the etch process can be a wet etch process in which the exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art.
Each of the backside recesses (143, 243, 343) can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses (143, 243, 343) can be greater than the height of the respective backside recess 43. Each of the backside recesses (143, 243, 343) can laterally extend substantially parallel to the top surface of the substrate 8. A backside recess (143, 243, 343) can be vertically bounded by a top surface of an underlying insulating layer (132, 232, 332) and a bottom surface of an overlying insulating layer (132, 232, 332). In one embodiment, each of the backside recesses (143, 243, 343) can have a uniform height throughout.
Referring to
At least one alternating stack {(132, 142), (232, 246), (332, 346)} of respective insulating layers (132, 232, 332) and respective electrically conductive layers (146, 246, 346) can be formed over the substrate 8. The combination of the memory stack structures 55 located in the memory opening fill structures 58 and the at least one alternating stack {(132, 142), (232, 246), (332, 346)} constitute a three-dimensional array of memory elements. In this case, the electrically conductive layers (146, 246, 346) may comprise word lines of the three-dimensional array of memory elements, while one or more topmost and bottommost electrically conductive layers (146, 346) comprise drain side and source side select gate electrodes, respectively.
Referring to
A backside contact via structure 76 can be formed within each backside cavity. Each backside contact via structure 76 can fill a respective backside cavity. Each contact via structures 76 can be formed by depositing at least one conductive material in a remaining unfilled volume (i.e., a backside cavity) of the backside trenches 79. For example, the at least one conductive material can include a conductive liner and a conductive fill material portion. The conductive liner can include a conductive metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The conductive fill material portion can include a metal or a metallic alloy. For example, the conductive fill material portion can include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.
The at least one conductive material can be planarized employing the contact-level dielectric layer 80 as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer 80 can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches 79 constitutes a backside contact via structure 76. Each contiguous combination of an insulating spacer 74 and a backside contact via structure 76 constitutes a backside trench fill structure (74, 76). Generally, each backside trench fill structures (74, 76) can vertically extend through each layer within the at least one alternating stack {(132, 142), (232, 246), (332, 346)} of respective insulating layers (132, 232, 332) and respective electrically conductive layers (146, 246, 346).
Referring to
Referring to
As shown in
Referring to
For example, at least one conductive material can be deposited in the layer contact via cavities 85, and excess portions of the at least one conductive material can be removed from above the horizontal plane including the top surface of the contact-level dielectric layer 80 by a planarization process such as a chemical mechanical polishing process. The at least one conductive material may comprise a metallic barrier material and a metallic fill material. In this case, each layer contact via structure 86 may comprise a metallic barrier liner 86A and a metallic fill material portion 86B. Each metallic barrier liner 86A may comprise a metallic barrier material such as TiN, TaN, WN, MoN, TiC, TaC, WC, or a combination thereof, and may have a thickness in a range from 3 nm to 50 nm, such as from 6 nm to 30 nm, although lesser and greater thicknesses may also be employed. Each metallic fill material portion 86B may comprise a material such as W, Ti, Ta, Ru, Co, Mo, Cu, etc.
The layer contact via structures 86 may comprise first layer contact via structures 861 that contact a top surface of a first electrically conductive layer 146, second layer contact via structures 862 that contact a top surface of a second electrically conductive layer 246, and third layer contact via structures 863 that contact a top surface of a third electrically conductive layer 346. Each first layer contact via structure 861 can be laterally surrounded by, and can be laterally contacted by, a respective set of first dielectric spacers 182, a respective set of second dielectric spacers 282, and a respective set of third dielectric spacers 382. Each second layer contact via structure 862 can be laterally surrounded by, and can be laterally contacted by, a respective set of second dielectric spacers 282 and a respective set of third dielectric spacers 382. Each third layer contact via structure 863 can be laterally surrounded by, and can be laterally contacted by, a respective set of third dielectric spacers 382.
As shown in
Generally speaking, a set of material portions comprising a first sacrificial via fill structure 183 can be replaced with a first layer contact via structure 861 that directly contacts a top surface of a first electrically conductive layer 146, with or without intermediate replacement of the first sacrificial via fill structure 183 with a portion of a sacrificial via fill structure 83. A set of material portions comprising a second sacrificial via fill structure 283 can be replaced with a second layer contact via structure 862 that directly contacts a top surface of a second electrically conductive layer 246, with or without intermediate replacement of the second sacrificial via fill structure 283 with a portion of a sacrificial via fill structure 83. Each material portion that fills a void 389′ in a third via cavity 389 (such as a sacrificial via fill structure 83) may be replaced with a third layer contact via structure 863.
In one embodiment, a layer contact via structure 86 (such as a first layer contact via structure 861) vertically extends through an upper portion of the at least one alternating stack {(132, 142), (232, 246), (332, 346)} and contacts a top surface of one of the electrically conductive layers (146, 246, 346). A plurality of dielectric support pillar structures 20 vertically extend through each layer within the at least one alternating stack {(132, 142), (232, 246), (332, 346)} and contact a respective first sidewall segment of the layer contact via structure 86. A plurality of dielectric spacers (182, 282, 382) vertically extend through the upper portion of the at least one alternating stack {(132, 142), (232, 246), (332, 346)} and contact a respective second sidewall segment of the layer contact via structure 86. In one embodiment shown in
In one embodiment, the plurality of dielectric support pillar structures 20 comprises P dielectric support pillar structures 20; and the plurality of dielectric spacers (182, 282, 382) comprises at least P dielectric spacers (182, 282, 382); and P is an integer greater than 1. In one embodiment, each of the plurality of dielectric spacers (182, 282, 382) is located within a respective azimuthal angle range (α1, α2, α3) around the vertical axis VA that has a magnitude less than 2π/P radian. In one embodiment, the at least one alternating stack {(132, 142), (232, 246), (332, 346)} comprises M alternating stacks {(132, 142), (232, 246), (332, 346)}, in which M is an integer greater than 1; and the plurality of dielectric spacers (182, 282, 382) comprises a total of M×P dielectric spacers (182, 282, 382). In one embodiment, the M×P dielectric spacers (182, 282, 382) comprises M sets of P dielectric spacers (182, 282, 382) that are azimuthally spaced apart around the vertical axis VA. Each set of respective P dielectric spacers (182, 282, 382) overlies or underlies any other set of respective P dielectric spacers (182, 282, 382).
In one embodiment, each of the plurality of dielectric support pillar structures 20 has a respective center and a respective vertical axis VA′ passing through the respective center; and each of the vertical axes VA′ of the plurality of dielectric support pillar structures 20 is laterally spaced from the vertical axis VA passing through the center GC of the layer contact via structure 86 by a greater lateral distance than any point within the plurality of dielectric spacers (182, 282, 382) is from the vertical axis VA passing through the center GC of the layer contact via structure 86.
In one embodiment, each surface segment of the layer contact via structure 86 located above a horizontal plane including a top surface of the one of the electrically conductive layers (146, 246, 346) and below a horizontal surface including a topmost surface of the at least one alternating stack {(132, 142), (232, 246), (332, 346)} is in direct contact with one of plurality of dielectric support pillar structures 20 or with one of the plurality of dielectric spacers (182, 282, 382).
In one embodiment, each interface between the layer contact via structure 86 and the plurality of dielectric support pillar structures 20 has a horizontal cross-sectional profile in which a convex surface segment of the layer contact via structure 86 is in direct contact with a concave surface segment of a respective one of the dielectric support pillar structures 20.
In one embodiment, each of the plurality of dielectric support pillar structures 20 is in in direct contact with a respective pair of dielectric spacers (182, 282, 382) among the plurality of dielectric spacers (182, 282, 382); and each of the plurality of dielectric spacers (182, 282, 382) is in direct contact with a respective pair of dielectric support pillar structures 20.
In one embodiment, each of the plurality of dielectric support pillar structures 20 is in direct contact with each insulating layer (132, 232, 332) within the at least one alternating stack {(132, 142), (232, 246), (332, 346)}; and each insulating layer (132, 232, 332) within the at least one alternating stack {(132, 142), (232, 246), (332, 346)} that overlies the one of the electrically conductive layers (146, 246, 346) is in direct contact with at least two dielectric spacers (182, 282, 382) (which may be P dielectric spacers (182, 282, 382)) within the plurality of dielectric spacers (182, 282, 382).
In one embodiment, a contact-level dielectric layer 80 overlies the at least one alternating stack {(132, 142), (232, 246), (332, 346)}. Top surfaces of the plurality of dielectric support pillar structures 20 located within a horizontal plane including a top surface of the contact-level dielectric layer 80; and topmost surfaces of the plurality of dielectric spacers (182, 282, 382) is located within a horizontal plane including topmost surfaces of the at least one alternating stack {(132, 142), (232, 246), (332, 346)}.
In one embodiment, each interface between the layer contact via structure 86 and a respective one of the plurality of dielectric support pillar structures 20 vertically extends from the one of the electrically conductive layers (146, 246, 346) to a horizontal plane including a topmost surface of the at least one alternating stack {(132, 142), (232, 246), (332, 346)} without horizontally-extending surface segments.
In one embodiment, each of the plurality of dielectric spacers (182, 282, 382) comprises at least one laterally-extending fin portion which is located at a level of a respective one of the electrically conductive layers (146, 246, 346), has a respective horizontally-extending top surface contacting a respective overlying insulating layer (132, 232, 332) within the at least one alternating stack {(132, 142), (232, 246), (332, 346)}, and has a respective horizontally-extending bottom surface segment contacting a respective underlying insulating layer (132, 232, 332) within the at least one alternating stack {(132, 142), (232, 246), (332, 346)}.
According to an aspect of the present disclosure, a layer contact via structure 86 vertically extends through an upper portion of the at least one alternating stack {(132, 142), (232, 246), (332, 346)} and contacts a top surface of one of the electrically conductive layers (146, 246, 346). The layer contact via structure 86 is electrically isolated from each electrically conductive layer within the at least one alternating stack {(132, 142), (232, 246), (332, 346)} that overlies the one of the electrically conductive layers (146, 246, 346) by a set of at least one dielectric isolation structure (182, 282, 382, 20) that comprises a first dielectric spacer 182. A sidewall of the layer contact via structure 86 comprises a first straight sidewall segment that contacts a first portion of the first dielectric spacer 182 and a first convex surface segment that contacts a concave surface of a second portion of the first dielectric spacer 182.
In one embodiment, a top periphery of the first convex surface segment is adjoined to a bottom periphery of the first straight sidewall segment. In one embodiment, the first convex surface segment laterally protrudes outward relative to the bottom periphery of the first straight sidewall segment. In one embodiment, the first convex surface segment laterally protrudes outward from a periphery of an interface between the layer contact via structure 86 and the one of the electrically conductive layers (146, 246, 346).
In one embodiment, the at least one alternating stack {(132, 142), (232, 246), (332, 346)} comprises a plurality of alternating stacks {(132, 142), (232, 246), (332, 346)} that are stacked along the vertical direction; the set of at least one dielectric isolation structure (182, 282, 382, 20) comprises at least one additional dielectric spacer (282, 382) that overlies the first dielectric spacer 182 and laterally surrounded by a respective alternating stack {(132, 142), (232, 246), or (332, 346)} among the plurality of alternating stacks {(132, 142), (232, 246), (332, 346)}; and each of the at least one additional dielectric spacer (282, 382) has a respective top surface located within a horizontal plane including a top surface of a respective alternating stack {(232, 246) or (332, 346)}.
In one embodiment, the plurality of alternating stacks {(132, 142), (232, 246), (332, 346)} comprises a second alternating stack (232, 246) that overlies, and is in contact with, the first alternating stack (132, 246); the at least one additional dielectric spacer (282, 382) comprises a second dielectric spacer 282 that contacts the first dielectric spacer 182; and the sidewall of the layer contact via structure 86 comprises a second straight sidewall segment that contacts the second dielectric spacer 282 and a second convex surface segment that contacts a concave surface of the second dielectric spacer 282. In one embodiment, a top periphery of the second convex surface segment is adjoined to a bottom periphery of the second straight sidewall segment; and a bottom portion of the second convex surface segment is in contact with a chamfered surface of the first insulating spacer.
In one embodiment, a plurality of dielectric support pillar structures 20 may vertically extend through each layer within the at least one alternating stack {(132, 142), (232, 246), (332, 346)} and may contact a respective sidewall segment of the layer contact via structure 86. In one embodiment, the set of at least one dielectric isolation structure (182, 282, 382, 20) comprises at least one additional first dielectric spacer 182 having a same vertical extent as the first dielectric spacer 182; and the first dielectric spacer 182 and the at least one additional first dielectric spacer 182 are azimuthally spaced apart around the layer contact via structure 86 and are not in direct contact among one another. In one embodiment, the first dielectric spacer 182 and the at least one additional first dielectric spacer 182 are azimuthally interlaced with the plurality of dielectric support pillar structures 20 around a vertical axis VA passing through a center GC of the layer contact via structure 86.
In one embodiment, the first dielectric spacer 182 and the at least one additional first dielectric spacer 182 comprises P dielectric spacers (182, 282, 382); the plurality of dielectric support pillar structures 20 comprises P dielectric support pillar structures 20; P is an integer greater than 1; and each of the P dielectric spacers (182, 282, 382) is located within a respective azimuthal angle range (α1, α2, α3) around the vertical axis VA that has a magnitude less than 2π/P radian.
In one embodiment, each of the respective sidewall segment of the layer contact via structure 86 comprises: at least one straight sidewall segment that contacts a straight sidewall surface segment of a respective one of the plurality of dielectric support pillar structures 20; and at least one convex surface segment that contacts a concave surface segment of the respective one of the plurality of dielectric support pillar structures 20. In one embodiment, the at least one alternating stack {(132, 142), (232, 246), (332, 346)} comprises a plurality of alternating stacks {(132, 142), (232, 246), (332, 346)} that are stacked along the vertical direction; at least one straight sidewall segment comprises a plurality of straight sidewall segments; the at least one convex surface segment comprises a plurality of convex surface segments; and one of the plurality of convex surface segments intersects a horizontal plane including an interface between one of the plurality of alternating stacks {(132, 142), (232, 246), (332, 346)} and another of the alternating stacks {(132, 142), (232, 246), (332, 346)}.
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In one embodiment, a control circuitry (e.g., driver circuit) configured to control operation of the vertical stack of memory cell within each NAND memory string (e.g., in the memory opening fill structure 58) may be located on the substrate 8 below the alternating stacks{(132, 142), (232, 246), (332, 346)}. In another embodiment, the control circuitry (e.g., driver circuit) may be formed on a separate substrate and then bonded to the three-dimensional memory device, will be described with respect to
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Generally, the logic-side semiconductor devices 720 comprise the control circuitry configured to control operation of the vertical stack of memory elements within each memory opening fill structure 58 in the memory die 900. The logic-side semiconductor devices 720 may be electrically connected to the logic-side bonding pads 788 through the logic-side metal interconnect structures 780. Thus, the logic-side bonding pads 788 are electrically connected to the logic-side semiconductor devices 720 through the logic-side metal interconnect structures 780.
The logic die 700 can be attached to the memory die 900, for example, by bonding the memory-side bonding pads 388 with the logic-side bonding pads 788. For example, the memory-side bonding pads 388 can be bonded with the logic-side bonding pads 788 by metal-to-metal bonding such as copper-to-copper bonding. In some embodiments, hybrid bonding may be employed, in which contacting surfaces of the memory-side dielectric material layers 960 and the logic-side dielectric material layers 760 are bonded through dielectric-to-dielectric bonding (such as oxide-to-oxide bonding). In one embodiment, a plurality of logic dies 700 such as a two-dimensional array of logic dies 700 may be provided on the logic-side substrate, and the plurality of logic dies 700 may be simultaneously bonded to a plurality of memory dies 900 employing wafer-to-wafer bonding.
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Each of the dielectric support pillar structures in the alternative configuration of the exemplary structure can be formed as supplementary dielectric support pillar structures 30. Thus, the supplementary dielectric support pillar structures 30 in the alternative configuration of the exemplary structure are herein referred to as dielectric support pillar structures 30.
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In the alternative configuration of the exemplary structure, the layer contact via structures 86 may comprise first layer contact via structures 861 that contacts a top surface of a first electrically conductive layer 146, second layer contact via structures 862 that contacts a top surface of a second electrically conductive layer 246, and third layer contact via structures 863 that contacts a top surface of a third electrically conductive layer 346. Each first layer contact via structure 861 can be laterally surrounded by, and can be laterally contacted by, a respective first dielectric spacer 182, a respective second dielectric spacer 282, and a third dielectric spacer 382. Each second layer contact via structure 862 can be laterally surrounded by, and can be laterally contacted by, a respective second dielectric spacer 282 and a respective third dielectric spacer 382. Each third layer contact via structure 863 can be laterally surrounded by, and can be laterally contacted by, a respective third dielectric spacer 382.
Generally speaking, a set of material portions comprising a first sacrificial via fill structure 183 can be replaced with a first layer contact via structure 861 that directly contacts a top surface of a first electrically conductive layer 146, with, or without, intermediate replacement of the first sacrificial via fill structure 183 with a portion of a sacrificial via fill structure 83. A set of material portions comprising a second sacrificial via fill structure 283 can be replaced with a second layer contact via structure 862 that directly contacts a top surface of a second electrically conductive layer 246, with, or without, intermediate replacement of the second sacrificial via fill structure 283 with a portion of a sacrificial via fill structure 83. Each material portion that fills a void 389′ in a third via cavity 389 (such as a sacrificial via fill structure 83) may be replaced with a third layer contact via structure 863.
In the alternative configuration of the exemplary structure, each of the dielectric spacers (182, 282, 382) can be formed as a tubular dielectric spacer, i.e., a dielectric spacer having a generally tubular configuration. For example, each first dielectric spacer 182 may comprise a tubular dielectric spacer that laterally encloses a respective first layer contact via structure 861; each second dielectric spacer 282 may comprise a tubular dielectric spacer that laterally encloses a respective first layer contact via structure 861 or a respective second layer contact via structure 862; and each third dielectric spacer 382 may comprise a tubular dielectric spacer that laterally encloses a respective first layer contact via structure 861, a respective second layer contact via structure 862, or a respective third layer contact via structure. Each tubular dielectric spacer may comprise a straight cylindrical outer sidewall that vertically extends from an outer periphery of a top surface of the tubular dielectric spacer to an outer periphery of a bottom surface of the tubular dielectric spacer.
Referring to all drawings and according to various embodiments of the present disclosure, a memory device is provided, which comprises: at least one alternating stack {(132, 142), (232, 246), (332, 346)} of insulating layers (132, 232, 332) and electrically conductive layers (146, 246, 346); memory stack structures 55 vertically extending through the at least one alternating stack {(132, 142), (232, 246), (332, 346)}, wherein each of the memory stack structures 55 comprises a respective vertical stack of memory elements (e.g., portions of the memory film 50) and a vertical semiconductor channel 60; and an electrically conductive layer contact via structure 86 vertically extending through an upper portion of the at least one alternating stack {(132, 142), (232, 246), (332, 346)} and contacting a top surface of one of the electrically conductive layers (146, 246, 346); a plurality of dielectric support pillar structures 20 vertically extending through each layer within the at least one alternating stack {(132, 142), (232, 246), (332, 346)} and contacting a respective first sidewall segment of the layer contact via structure 86; and a plurality of dielectric spacers (182, 282, 382) vertically extending through the upper portion of the at least one alternating stack {(132, 142), (232, 246), (332, 346)} and contacting a respective second sidewall segment of the layer contact via structure 86.
In one embodiment of the present disclosure, at least one of the plurality of dielectric support pillar structures 20 comprises a lower portion which is located under a bottom surface of the layer contact via structure 86.
According to another aspect of the present disclosure, a device structure is provided, which comprises: at least one alternating stack {(132, 142), (232, 246), (332, 346)} of insulating layers (132, 232, 332) and electrically conductive layers (146, 246, 346); memory stack structures 55 vertically extending through the at least one alternating stack {(132, 142), (232, 246), (332, 346)}, wherein each of the memory stack structures 55 comprises a respective vertical stack of memory elements and a vertical semiconductor channel 60; and an electrically conductive layer contact via structure 86 vertically extending through an upper portion of the at least one alternating stack {(132, 142), (232, 246), (332, 346)} and contacting a top surface of one of the electrically conductive layers (146, 246, 346), wherein the layer contact via structure 86 is electrically isolated from each electrically conductive layer within the at least one alternating stack {(132, 142), (232, 246), (332, 346)} that overlies the one of the electrically conductive layers (146, 246, 346) by a set of at least one dielectric isolation structure (182, 282, 382, 20) that comprises a first dielectric spacer 182, and wherein a sidewall of the layer contact via structure 86 comprises a first straight sidewall segment that contacts a first portion of the first dielectric spacer 182 and a first convex surface segment that contacts a concave surface of a second portion of the first dielectric spacer 182.
The various embodiments of the present disclosure may be employed to provide contact via structures that contact a respective electrically conductive layer within an alternating stack of insulating layers and electrically conductive layers without forming a staircase region including stepped surfaces. In one embodiment, the methods and structures of the present disclosure may be employed to provide a three-dimensional memory array including layer contact via structures 86 that contact a respective electrically conductive layer (146, 256, 346) in at least one alternating stack of insulating layers and electrically conductive layers. In a non-limiting example, the methods and structures of the present disclosure may be employed to form a three-dimensional NAND array.
Although the foregoing refers to particular embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Where an embodiment using a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63480636 | Jan 2023 | US |
