Patent Application
20240074200
The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device and a method of making thereof by selectively growing sacrificial pillar structures to suppress of memory opening widening.
A three-dimensional memory device including three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
According to an embodiment of the present disclosure, a method of forming a semiconductor structure is provided, which comprises: forming a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers over a substrate; forming a first-tier memory opening through the first-tier alternating stack; forming a first-tier sacrificial memory opening fill structure in the first-tier memory opening; forming a second-tier alternating stack of second-tier insulating layers and second-tier sacrificial material layers over the first-tier alternating stack; forming an etch mask layer comprising an opening therethrough over the second-tier alternating stack; forming a second-tier memory opening through the second-tier alternating stack, wherein a top surface of the first-tier sacrificial memory opening fill structure is physically exposed underneath the second-tier memory opening; removing the etch mask layer employing an etch mask removal process that collaterally removes a top portion of the first-tier sacrificial memory opening fill structure; forming a sacrificial pillar structure by performing a selective material deposition process that grows a sacrificial fill material from a top surface of a remaining portion of the first-tier sacrificial memory opening fill structure while suppressing growth of the sacrificial fill material from physically exposed surfaces of the first-tier alternating stack and the second-tier alternating stack; forming an inter-tier memory opening by removing the first-tier sacrificial memory opening fill structure and at least a central portion of the sacrificial pillar structure; forming a memory opening fill structure in the inter-tier memory opening, wherein the memory opening fill structure comprises a vertical stack of memory elements that are formed at levels of the first-tier sacrificial material layers and the second-tier sacrificial material layers; and replacing the first-tier sacrificial material layers and the second-tier sacrificial material layers with electrically conductive layers.
According to another aspect of the present disclosure, a memory device is provided, which comprises: a first-tier alternating stack of first-tier insulating layers and first-tier electrically conductive layers; a second-tier alternating stack of second-tier insulating layers and second-tier electrically conductive layers located over the first-tier alternating stack; a memory opening fill structure vertically extending through the second-tier alternating stack and the first-tier alternating stack and comprising a memory film and a vertical semiconductor channel; and a tubular carbon-based structure laterally surrounded by a topmost first-tier insulating layer within the first-tier alternating stack and laterally surrounding and contacting the memory opening fill structure.
According to yet another aspect of the present disclosure, a memory device is provided, which comprises: a first-tier alternating stack of first-tier insulating layers and first-tier electrically conductive layers; a second-tier alternating stack of second-tier insulating layers and second-tier electrically conductive layers located over the first-tier alternating stack; and a memory opening fill structure vertically extending through the second-tier alternating stack and the first-tier alternating stack and comprising a memory film and a vertical semiconductor channel, wherein the memory opening fill structure comprises: a first straight section comprising a first cylindrical straight sidewall that vertically extends through each of the first-tier electrically conductive layers, a second straight section comprising a second cylindrical straight sidewall that vertically extends through each of the second-tier electrically conductive layers, and a laterally-protruding section that laterally protrudes outward from a top periphery of the first cylindrical straight sidewall and from a bottom periphery of the second cylindrical straight sidewall; and wherein a bottom portion of the second straight section has a greater lateral dimension than a top portion of the first straight section.
Embodiments of the present disclosure are directed to a three-dimensional memory device and a method of making thereof by selectively growing sacrificial pillar structures to suppress of memory opening widening. The embodiments of the present disclosure may be used to form various semiconductor devices, such as three-dimensional memory Devices comprising a plurality of NAND memory strings.
The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The term “at least one” element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.
The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition and the same function. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. If two or more elements are not in direct contact with each other or among one another, the two elements are “disjoined from” each other or “disjoined among” one another. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the first element and the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.
As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.
As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface overlies or underlies the first surface and there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from a vertical direction by an angle less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction, and may, or may not, include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.
As used herein, a “memory level” or a “memory array level” refers to the level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including topmost surfaces of an array of memory elements and a second horizontal plane including bottommost surfaces of the array of memory elements. As used herein, a “through-stack” element refers to an element that vertically extends through a memory level.
As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0×10−5 S/m to 1.0×105 S/m. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−5 S/m to 1.0 S/m in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/m to 1.0×107 S/m upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105 S/m. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−5 S/m. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to provide electrical conductivity greater than 1.0×105 S/m. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10−5 S/m to 1.0×107 S/m. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.
Generally, a semiconductor package (or a “package”) refers to a unit semiconductor device that may be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or a “chip”) or a plurality of semiconductor chips that are bonded throughout, for example, by flip-chip bonding or another chip-to-chip bonding. A package or a chip may include a single semiconductor die (or a “die”) or a plurality of semiconductor dies. A die is the smallest unit that may independently execute external commands or report status. Typically, a package or a chip with multiple dies is capable of simultaneously executing as many number of external commands as the total number of dies therein. Each die includes one or more planes. Identical concurrent operations may be executed in each plane within a same die, although there may be some restrictions. In case a die is a memory die, i.e., a die including memory elements, concurrent read operations, concurrent write operations, or concurrent erase operations may be performed in each plane within a same memory die. In a memory die, each plane contains a number of memory blocks (or “blocks”), which are the smallest unit that may be erased by in a single erase operation. Each memory block contains a number of pages, which are the smallest units that may be selected for programming. A page is also the smallest unit that may be selected to a read operation.
In a multi-tier 3D NAND structure, memory openings vertically extend through multiple tier structures (e.g., alternating stacks of insulating layers and electrically conductive layers comprising word lines and select gate electrodes). Portions of memory openings in a lower-tier structure (such as a bottom-tier structure) tend to become wider due to subsequent etch steps, recess steps, and clean steps that are performed after initial formation of portions of the memory opening through the lower-tier structure. The increase in the lateral dimension of each portion of the memory opening in the lower-tier structure through the various etch steps, recess steps, and clean steps is herein referred to as an integration critical dimension (CD) bias. The greater the total number of tiers in a 3D NAND structure, the larger the integration CD bias for the portions of the memory openings in a lower tier. In comparative exemplary methods, the lower portions of the memory openings may be initially formed with a smaller lateral dimension to compensate for the integration CD bias for the portions of the memory openings in the lower tier. The reduction in the lateral dimension of the lower portions of the memory openings employing a reactive ion etch process is difficult because etch rate of materials in a high aspect ratio opening is reduced significantly. The reduction in the etch rate during the reactive ion etch process limits the total stack height for the lower tier, and thus also limits the total number of memory bits that can be stored within the lower tier per memory opening fill structure.
According to an aspect of the present disclosure, selective regrowth of a sacrificial fill material after collateral recessing of a pre-existing sacrificial fill material can be employed to reduce the impact of a memory opening widening only to upper tier structures. In this case, the integration CD bias decreases for a lower tier, and the memory openings through the lower tier may be formed with greater lateral dimensions, and thus, at a higher etch rate during a reactive ion etch process. The selective regrowth of a sacrificial memory opening fill material can be employed to reduce the integration CD bias and to reduce the memory opening aspect ratio for the tier structures for which the selective regrowth is employed. Generally, the selective regrowth sacrificial material may comprise carbon-based material such as undoped or doped carbon.
Referring to
Dielectric material layers are formed over the semiconductor devices, which are herein referred to as lower-level dielectric material layers 760. The lower-level dielectric material layers 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks diffusion of mobile ions and/or apply appropriate stress to underlying structures), first dielectric material layers 764 that overlie the dielectric liner 762, a silicon nitride layer (e.g., hydrogen diffusion barrier) 766 that overlies the first dielectric material layers 764, and at least one second dielectric layer 768.
The dielectric layer stack including the lower-level dielectric material layers 760 functions as a matrix for lower-level metal interconnect structures 780 that provide electrical wiring to and from the various nodes of the semiconductor devices and landing pads for through-memory-level contact via structures to be subsequently formed. The lower-level metal interconnect structures 780 are formed within the dielectric layer stack of the lower-level dielectric material layers 760, and comprise a lower-level metal line structure located under and optionally contacting a bottom surface of the silicon nitride layer 766.
For example, the lower-level metal interconnect structures 780 may be formed within the first dielectric material layers 764. The first dielectric material layers 764 may be a plurality of dielectric material layers in which various elements of the lower-level metal interconnect structures 780 are sequentially formed. Each dielectric material layer selected from the first dielectric material layers 764 may include any of doped silicate glass, undoped silicate glass, organosilicate glass, silicon nitride, silicon oxynitride, and dielectric metal oxides (such as aluminum oxide). In one embodiment, the first dielectric material layers 764 may comprise, or consist essentially of, dielectric material layers having dielectric constants that do not exceed the dielectric constant of undoped silicate glass (silicon oxide) of 3.9. The lower-level metal interconnect structures 780 may include various device contact via structures 782 (e.g., source and drain electrodes which contact the respective source and drain nodes of the device or gate electrode contacts), intermediate lower-level metal line structures 784, lower-level metal via structures 786, and landing-pad-level metal line structures 788 that are configured to function as landing pads for through-memory-level contact via structures to be subsequently formed.
The landing-pad-level metal line structures 788 may be formed within a topmost dielectric material layer of the first dielectric material layers 764 (which may be a plurality of dielectric material layers). Each of the lower-level metal interconnect structures 780 may include a metallic nitride liner and a metal fill structure. Top surfaces of the landing-pad-level metal line structures 788 and the topmost surface of the first dielectric material layers 764 may be planarized by a planarization process, such as chemical mechanical planarization. The silicon nitride layer 766 may be formed directly on the top surfaces of the landing-pad-level metal line structures 788 and the topmost surface of the first dielectric material layers 764.
The at least one second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. Each dielectric material layer selected from the at least one second dielectric material layer 768 may include any of doped silicate glass, undoped silicate glass, and organosilicate glass. In one embodiment, the at least one first second material layer 768 may comprise, or consist essentially of, dielectric material layers having dielectric constants that do not exceed the dielectric constant of undoped silicate glass (silicon oxide) of 3.9.
An optional layer of a metallic material and a layer of a semiconductor material may be deposited over, or within patterned recesses of, the at least one second dielectric material layer 768, and is lithographically patterned to provide an optional conductive plate layer 6 and in-process source-level material layers 110′. The optional conductive plate layer 6, if present, provides a high conductivity conduction path for electrical current that flows into, or out of, the in-process source-level material layers 110′. The optional conductive plate layer 6 includes a conductive material such as a metal or a heavily doped semiconductor material. The optional conductive plate layer 6, for example, may include a tungsten layer having a thickness in a range from 3 nm to 100 nm, although lesser and greater thicknesses may also be used. A metal nitride layer (not shown) may be provided as a diffusion barrier layer on top of the conductive plate layer 6. The conductive plate layer 6 may function as a special source line in the completed device. In addition, the conductive plate layer 6 may comprise an etch stop layer and may comprise any suitable conductive, semiconductor or insulating layer. The optional conductive plate layer 6 may include a metallic compound material such as a conductive metallic nitride (e.g., TiN) and/or a metal (e.g., W). The thickness of the optional conductive plate layer 6 may be in a range from 5 nm to 100 nm, although lesser and greater thicknesses may also be used.
The in-process source-level material layers 110′ may include various layers that are subsequently modified to form source-level material layers. The source-level material layers, upon formation, include a source contact layer that functions as a common source region for vertical field effect transistors of a three-dimensional memory device. In one embodiment, the in-process source-level material layers 110′ may include, from bottom to top, a lower source-level semiconductor layer 112, a lower sacrificial liner 103, a source-level sacrificial layer 104, an upper sacrificial liner 105, an upper source-level semiconductor layer 116, a source-level insulating layer 117, and an optional source-select-level conductive layer 118.
The lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may be the opposite of the conductivity of vertical semiconductor channels to be subsequently formed. For example, if the vertical semiconductor channels to be subsequently formed have a doping of a first conductivity type, the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 have a doping of a second conductivity type that is the opposite of the first conductivity type. The thickness of each of the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may be in a range from 10 nm to 300 nm, such as from 20 nm to 150 nm, although lesser and greater thicknesses may also be used.
The source-level sacrificial layer 104 includes a sacrificial material that may be removed selective to the lower sacrificial liner 103 and the upper sacrificial liner 105. In one embodiment, the source-level sacrificial layer 104 may include a semiconductor material such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source-level sacrificial layer 104 may be in a range from 30 nm to 400 nm, such as from 60 nm to 200 nm, although lesser and greater thicknesses may also be used.
The lower sacrificial liner 103 and the upper sacrificial liner 105 include materials that may function as an etch stop material during removal of the source-level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 may include silicon oxide, silicon nitride, and/or a dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 may include a silicon oxide layer having a thickness in a range from 2 nm to 30 nm, although lesser and greater thicknesses may also be used.
The source-level insulating layer 117 includes a dielectric material such as silicon oxide. The thickness of the source-level insulating layer 117 may be in a range from 20 nm to 400 nm, such as from 40 nm to 200 nm, although lesser and greater thicknesses may also be used. The optional source-select-level conductive layer 118 may include a conductive material that may be used as a source-select-level gate electrode. For example, the optional source-select-level conductive layer 118 may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon that may be subsequently converted into doped polysilicon by an anneal process. The thickness of the optional source-select-level conductive layer 118 may be in a range from 30 nm to 200 nm, such as from 60 nm to 100 nm, although lesser and greater thicknesses may also be used.
The in-process source-level material layers 110′ may be formed directly above a subset of the semiconductor devices on the substrate 8 (e.g., silicon wafer). As used herein, a first element is located “directly above” a second element if the first element is located above a horizontal plane including a topmost surface of the second element and an area of the first element and an area of the second element has an areal overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the substrate 8.
The optional conductive plate layer 6 and the in-process source-level material layers 110′ may be patterned to provide openings in areas in which through-memory-level contact via structures and through-dielectric contact via structures are to be subsequently formed. Patterned portions of the stack of the conductive plate layer 6 and the in-process source-level material layers 110′ are present in each memory array region 100 in which three-dimensional memory stack structures are to be subsequently formed.
The optional conductive plate layer 6 and the in-process source-level material layers 110′ may be patterned such that an opening extends over a staircase region 200 in which contact via structures contacting word line electrically conductive layers are to be subsequently formed. In one embodiment, the staircase region 200 may be laterally spaced from the memory array region 100 along a first horizontal direction hd1. A horizontal direction that is perpendicular to the first horizontal direction hd1 is herein referred to as a second horizontal direction hd2. In one embodiment, additional openings in the optional conductive plate layer 6 and the in-process source-level material layers 110′ may be formed within the area of a memory array region 100, in which a three-dimensional memory array including memory stack structures is to be subsequently formed. A peripheral device region 400 that is subsequently filled with a field dielectric material portion may be provided adjacent to the staircase region 200.
The region of the semiconductor devices 710 and the combination of the lower-level dielectric material layers 760 and the lower-level metal interconnect structures 780 is herein referred to an underlying peripheral device region 700, which is located underneath a memory-level assembly to be subsequently formed and includes peripheral devices for the memory-level assembly. The lower-level metal interconnect structures 780 are formed in the lower-level dielectric material layers 760.
The lower-level metal interconnect structures 780 may be electrically connected to active nodes (e.g., transistor active regions 742 or gate electrodes 754) of the semiconductor devices 710 (e.g., CMOS devices), and are located at the level of the lower-level dielectric material layers 760. Through-memory-level contact via structures may be subsequently formed directly on the lower-level metal interconnect structures 780 to provide electrical connection to memory devices to be subsequently formed. In one embodiment, the pattern of the lower-level metal interconnect structures 780 may be selected such that the landing-pad-level metal line structures 788 (which are a subset of the lower-level metal interconnect structures 780 located at the topmost portion of the lower-level metal interconnect structures 780) may provide landing pad structures for the through-memory-level contact via structures to be subsequently formed.
Referring to
The first-tier alternating stack may include first insulting layers 132 as the first material layers, and first spacer material layers as the second material layers. In one embodiment, the first spacer material layers may be sacrificial material layers that are subsequently replaced with electrically conductive layers. In another embodiment, the first spacer material layers may be electrically conductive layers that are not subsequently replaced with other layers. While the present disclosure is described using embodiments in which sacrificial material layers are replaced with electrically conductive layers, embodiments in which the spacer material layers are formed as electrically conductive layers (thereby obviating the need to perform replacement processes) are expressly contemplated herein.
In one embodiment, the first material layers and the second material layers may be first insulating layers 132 and first sacrificial material layers 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. An alternating plurality of first insulating layers 132 and first sacrificial material layers 142 is formed over the in-process source-level material layers 110′. As used herein, a “sacrificial material” refers to a material that is removed during a subsequent processing step.
As used herein, an alternating stack of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of the first elements that is not an end element of the alternating plurality is adjoined by two instances of the second elements on both sides, and each instance of the second elements that is not an end element of the alternating plurality is adjoined by two instances of the first elements on both ends. The first elements may have the same thickness throughout, or may have different thicknesses. The second elements may have the same thickness throughout, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of the first material layers or with an instance of the second material layers, and may end with an instance of the first material layers or with an instance of the second material layers. In one embodiment, an instance of the first elements and an instance of the second elements may form a unit that is repeated with periodicity within the alternating plurality.
The first-tier alternating stack (132, 142) may include first insulating layers 132 composed of the first material, and first sacrificial material layers 142 composed of the second material, which is different from the first material. The first material of the first insulating layers 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layers 132 include, but are not limited to silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first insulating layers 132 may be silicon oxide.
The second material of the first sacrificial material layers 142 is a sacrificial material that may be removed selective to the first material of the first insulating layers 132. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material.
The first sacrificial material layers 142 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layers 142 may be subsequently replaced with electrically conductive electrodes which may function, for example, as control gate electrodes of a vertical NAND device. In one embodiment, the first sacrificial material layers 142 may be material layers that comprise silicon nitride.
In one embodiment, the first insulating layers 132 may include silicon oxide, and sacrificial material layers may include silicon nitride sacrificial material layers. The first material of the first insulating layers 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layers 132, tetraethylorthosilicate (TEOS) may be used as the precursor material for the CVD process. The second material of the first sacrificial material layers 142 may be formed, for example, CVD or atomic layer deposition (ALD).
The thicknesses of the first insulating layers 132 and the first sacrificial material layers 142 may be in a range from 20 nm to 50 nm, although lesser and greater thicknesses may be used for each first insulating layer 132 and for each first sacrificial material layer 142. The number of repetitions of the pairs of a first insulating layer 132 and a first sacrificial material layer 142 may be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions may also be used. In one embodiment, each first sacrificial material layer 142 in the first-tier alternating stack (132, 142) may have a uniform thickness that is substantially invariant within each respective first sacrificial material layer 142.
A first insulating cap layer 170 is subsequently formed over the first-tier alternating stack (132, 142). The first insulating cap layer 170 includes a dielectric material, which may be any dielectric material that may be used for the first insulating layers 132. In one embodiment, the first insulating cap layer 170 includes the same dielectric material as the first insulating layers 132. The thickness of the first insulating cap layer 170 may be in a range from 20 nm to 300 nm, although lesser and greater thicknesses may also be used.
Referring to
A dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material may be removed from above the horizontal plane including the top surface of the first insulating cap layer 170. A remaining portion of the dielectric fill material that fills the region overlying the first stepped surfaces constitute a first retro-stepped dielectric material portion 165. As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. The first-tier alternating stack (132, 142) and the first retro-stepped dielectric material portion 165 collectively constitute a first-tier structure, which is an in-process structure that is subsequently modified.
Referring to
The first-tier memory openings 149 are openings that are formed in the memory array region 100 through each layer within the first-tier alternating stack (132, 142) and are subsequently used to form memory stack structures therein. The first-tier memory openings 149 may be formed in clusters of first-tier memory openings 149 that are laterally spaced apart along the second horizontal direction hd2. Each cluster of first-tier memory openings 149 may be formed as a two-dimensional array of first-tier memory openings 149.
The first-tier support openings 129 are openings that are formed in the staircase region 200, and are subsequently employed to form support pillar structures. A subset of the first-tier support openings 129 that is formed through the first retro-stepped dielectric material portion 165 may be formed through a respective horizontal surface of the first stepped surfaces.
In one embodiment, the first anisotropic etch process may include an initial step in which the materials of the first-tier alternating stack (132, 142) are etched concurrently with the material of the first retro-stepped dielectric material portion 165. The chemistry of the initial etch step may alternate to optimize etching of the first and second materials in the first-tier alternating stack (132, 142) while providing a comparable average etch rate to the material of the first retro-stepped dielectric material portion 165. The first anisotropic etch process may use, for example, a series of reactive ion etch processes or a single reaction etch process (e.g., CF4/O2/Ar etch). The sidewalls of the various first-tier openings (149, 129) may be substantially vertical, or may be tapered.
The photoresist layer may be consumed during the first anisotropic etch process, and the patterned carbon-based hard mask layer may be employed as an etch mask during a remainder of the first anisotropic etch process. After etching through the alternating stack (132, 142) and the first retro-stepped dielectric material portion 165, the chemistry of a terminal portion of the first anisotropic etch process may be selected to etch through the dielectric material(s) of the at least one second dielectric layer 768 with a higher etch rate than an average etch rate for the in-process source-level material layers 110′. For example, the terminal portion of the anisotropic etch process may include a step that etches the dielectric material(s) of the at least one second dielectric layer 768 selective to a semiconductor material within a component layer in the in-process source-level material layers 110′. In one embodiment, the terminal portion of the first anisotropic etch process may etch through the source-select-level conductive layer 118, the source-level insulating layer 117, the upper source-level semiconductor layer 116, the upper sacrificial liner 105, the source-level sacrificial layer 104, and the lower sacrificial liner 103, and at least partly into the lower source-level semiconductor layer 112. The terminal portion of the first anisotropic etch process may include at least one etch chemistry for etching the various semiconductor materials of the in-process source-level material layers 110′. The patterned carbon-based hard mask layer may be subsequently removed, for example, by ashing.
Referring to
In one embodiment, the first-tier sacrificial fill material may include a first carbon-based material. In one embodiment, the first carbon-based material may comprise carbon atoms at an atomic concentration greater than 90%, such as 95 to 100 atomic percent. In one embodiment, the first-tier sacrificial fill material may comprise amorphous carbon, diamond-like carbon (DLC), or a doped carbon material that may be amorphous or nanocrystalline. The first-tier sacrificial fill material may be formed by a non-conformal deposition or a conformal deposition method. For example, the first-tier sacrificial fill material may be formed by chemical vapor deposition or spin-coating. Excess portions of the first-tier sacrificial fill material may be removed from above the horizontal plane including the top surface of the first insulating cap layer 170 by a recess etch or by chemical mechanical polishing.
Remaining portions of the first-tier sacrificial fill material comprise sacrificial first-tier opening fill material portions (148, 128). Specifically, each remaining portion of the sacrificial material in a first-tier memory opening 149 constitutes a sacrificial first-tier memory opening fill material portion 148. Each remaining portion of the sacrificial material in a first-tier support opening 129 constitutes a sacrificial first-tier support opening fill material portion 128. The various sacrificial first-tier opening fill material portions (148, 128) are concurrently formed, i.e., during a same set of processes including the deposition process that deposits the first-tier sacrificial fill material and the planarization process that removes the first-tier deposition process from above the first-tier alternating stack (132, 142). The top surfaces of the sacrificial first-tier opening fill material portions (148, 128) may be coplanar with the top surface of the first-tier structure (132, 142, 170, 165). Each of the sacrificial first-tier opening fill material portions (148, 128) may, or may not, include cavities therein.
Referring to
In one embodiment, the third material layers may be second insulating layers 232 and the fourth material layers may be second spacer material layers that provide vertical spacing between each vertically neighboring pair of the second insulating layers 232. In one embodiment, the third material layers and the fourth material layers may be second insulating layers 232 and second sacrificial material layers 242, respectively. The third material of the second insulating layers 232 may be at least one insulating material. The fourth material of the second sacrificial material layers 242 may be a sacrificial material that may be removed selective to the third material of the second insulating layers 232. The second sacrificial material layers 242 may comprise an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layers 242 may be subsequently replaced with electrically conductive electrodes which may function, for example, as control gate electrodes of a vertical NAND device.
In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second-tier alternating stack (232, 242) may include an alternating plurality of second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layers 232 may be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layers 242 may be formed, for example, CVD or atomic layer deposition (ALD).
The third material of the second insulating layers 232 may be at least one insulating material. Insulating materials that may be used for the second insulating layers 232 may be any material that may be used for the first insulating layers 132. The fourth material of the second sacrificial material layers 242 is a sacrificial material that may be removed selective to the third material of the second insulating layers 232. Sacrificial materials that may be used for the second sacrificial material layers 242 may be any material that may be used for the first sacrificial material layers 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.
The thicknesses of the second insulating layers 232 and the second sacrificial material layers 242 may be in a range from 20 nm to 50 nm, although lesser and greater thicknesses may be used for each second insulating layer 232 and for each second sacrificial material layer 242. The number of repetitions of the pairs of a second insulating layer 232 and a second sacrificial material layer 242 may be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions may also be used. In one embodiment, each second sacrificial material layer 242 in the second-tier alternating stack (232, 242) may have a uniform thickness that is substantially invariant within each respective second sacrificial material layer 242.
Second stepped surfaces in the second stepped area may be formed in the staircase region 200 using a same set of processing steps as the processing steps used to form the first stepped surfaces in the first stepped area with suitable adjustment to the pattern of at least one masking layer. A second retro-stepped dielectric material portion 265 may be formed over the second stepped surfaces in the staircase region 200.
A second insulating cap layer 270 may be subsequently formed over the second-tier alternating stack (232, 242). The second insulating cap layer 270 includes a dielectric material that is different from the material of the second sacrificial material layers 242. In one embodiment, the second insulating cap layer 270 may include silicon oxide. In one embodiment, the first and second sacrificial material layers (142, 242) may comprise silicon nitride. Generally speaking, at least one alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) may be formed over the in-process source-level material layers 110′, and at least one retro-stepped dielectric material portion (165, 265) may be formed over the staircase regions on the at least one alternating stack (132, 142, 232, 242).
Optionally, drain-select-level isolation structures 72 may be formed through a subset of layers in an upper portion of the second-tier alternating stack (232, 242). The second sacrificial material layers 242 that are cut by the drain-select-level isolation structures 72 correspond to the levels in which drain-select-level electrically conductive layers are subsequently formed. The drain-select-level isolation structures 72 include a dielectric material such as silicon oxide. The drain-select-level isolation structures 72 may laterally extend along a first horizontal direction hd1, and may be laterally spaced apart along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The combination of the second-tier alternating stack (232, 242), the second retro-stepped dielectric material portion 265, the second insulating cap layer 270, and the optional drain-select-level isolation structures 72 collectively constitute a second-tier structure (232, 242, 265, 270, 72).
Referring to
A photoresist layer (not shown) may be applied over the etch mask layer 277, and may be lithographically patterned to form various openings therethrough. The pattern of the openings may be the same as the pattern of the various first-tier openings (149, 129), which is the same as the sacrificial first-tier opening fill material portions (148, 128). Thus, the lithographic mask used to pattern the first-tier openings (149, 129) may be used to pattern the photoresist layer. The pattern of openings in the photoresist layer may be transferred through the etch mask layer 277, and subsequently through the second-tier structure (232, 242, 265, 270, 72) by a second anisotropic etch process to form various second-tier openings (249, 229) concurrently, i.e., during the second anisotropic etch process. The photoresist layer may be consumed during the second anisotropic etch process, and the patterned etch mask layer 277 may be partially consumed and its remaining portion is employed thereafter as an etch mask that defines the pattern of the second-tier openings (249, 229). The various second-tier openings (249, 229) may include second-tier memory openings 249 and second-tier support openings 229.
The second-tier memory openings 249 are formed directly on a top surface of a respective one of the sacrificial first-tier memory opening fill material portions 148. In one embodiment, a top surface of a respective first-tier sacrificial memory opening fill structure 148 is physically exposed underneath each second-tier memory opening 249. The second-tier support openings 229 are formed directly on a top surface of a respective one of the sacrificial first-tier support opening fill material portions 128. Further, each second-tier support openings 229 may be formed through a horizontal surface within the second stepped surfaces, which include the interfacial surfaces between the second-tier alternating stack (232, 242) and the second retro-stepped dielectric material portion 265. Locations of steps S in the first-tier alternating stack (132, 142) and the second-tier alternating stack (232, 242) are illustrated as dotted lines in
The second anisotropic etch process may include an etch step in which the materials of the second-tier alternating stack (232, 242) are etched concurrently with the material of the second retro-stepped dielectric material portion 265. The chemistry of the etch step may alternate to optimize etching of the materials in the second-tier alternating stack (232, 242) while providing a comparable average etch rate to the material of the second retro-stepped dielectric material portion 265. The second anisotropic etch process may use, for example, a series of reactive ion etch processes or a single reaction etch process (e.g., CF4/O2/Ar etch). The sidewalls of the various second-tier openings (249, 229) may be substantially vertical, or may be tapered. A bottom periphery of each second-tier opening (249, 229) may be laterally offset, and/or may be located entirely within, a periphery of a top surface of an underlying sacrificial first-tier opening fill material portion (148, 128). The thickness of the remaining portion of the etch mask layer 277 after the second anisotropic etch process may be in a range from 0.1 micron to 1 micron, such as from 0.3 micron to 0.7 micron, although lesser and greater thicknesses may also be employed.
Referring to
Referring to
In one embodiment, the sacrificial fill material that is grown during the selective material deposition process may comprise a third carbon-based material. The third carbon-based material may comprise, for example, amorphous carbon, diamond-like carbon, or a doped carbon material in an amorphous phase or in a nanocrystalline phase. In one embodiment, the third carbon-based material may comprise carbon atoms at an atomic concentration greater than 90%, such as 95 to 100 atomic percent. The third carbon-based material may, or may not, have a same material composition as the first carbon-based material and/or as the second carbon-based material. In one embodiment, the sacrificial fill material (i.e., the sacrificial pillar material) may be grown employing a selective chemical vapor deposition process employing a carbon-based precursor gas and an etchant gas. In this case, the nucleation rate of the third carbon-based material on surfaces of carbon-based materials due to the carbon-based precursor gas may be greater than the etch rate of the third carbon-based material due to the etchant gas. Further, the nucleation rate of the third carbon-based material on surfaces of the first insulating cap layer 170, the second insulating cap layer, the first retro-stepped dielectric material portion 165, and the second retro-stepped dielectric material portion 265 (which may comprise silicon oxide surface and silicon nitride surfaces) due to the carbon-based precursor gas is less than the etch rate of the third carbon-based material due to the etchant gas. Thus, the third carbon-based material grows only from the physically exposed surfaces of the first-tier sacrificial memory opening fill structures 148 and the first-tier sacrificial support opening fill structures 128, while growth of the third carbon-based material from surfaces of the first insulating cap layer 170, the second insulating cap layer, the first retro-stepped dielectric material portion 165, and the second retro-stepped dielectric material portion 265 is avoided.
The deposited portions of the third carbon-based material form pillar-shaped structures, which are herein referred to as the sacrificial pillar structures 168. According to an aspect of the present disclosure, the duration of the selective material deposition process may be selected such that the top surfaces of the sacrificial pillar structures 168 are formed above a horizontal plane including the top surface of the topmost first-tier sacrificial material layer 142 of the first-tier sacrificial material layers 142, and underneath a horizontal plane including a topmost surface of the first-tier structure. In one embodiment, the top surfaces of the sacrificial pillar structures 168 are formed above a horizontal plane including the bottom surface of the first insulating cap layer 170, and underneath a horizontal plane including a top surface of the first insulating cap layer 170.
Referring to
The second isotropic etch process may be performed before or after the first isotropic etch process. In an illustrative example, the second-tier insulating layers 232, the first-tier insulating layers 132, and the first insulating cap layer 170 may comprise silicon oxide, and the first isotropic etch process may comprise a wet etch process employing dilute hydrofluoric acid. Further, the second-tier sacrificial material layers 242 and the first-tier sacrificial material layers 142 may comprise silicon nitride, and the second isotropic etch process may comprise a wet etch process employing phosphoric acid. In one embodiment, the second-tier memory openings 249 and the top portion of the first-tier memory openings 149 may be laterally expanded such that a lateral dimension (i.e., a maximum lateral extent such as a diameter or a major axis) of a bottom portion of a second-tier memory opening 249 has a greater lateral dimension than a lateral dimension (i.e., a maximum lateral extent such as a diameter or a major axis) of a bottom portion of an underlying first-tier memory opening 149 (i.e., the bottom portion of an underlying first-tier sacrificial memory opening fill structure 148). Further, a lateral dimension (i.e., a maximum lateral extent such as a diameter or a major axis) of a top-portion of the second-tier memory opening 249 has a greater lateral dimension than a lateral dimension (i.e., a maximum lateral extent such as a diameter or a major axis) of the underlying first-tier memory opening 149 at a height of a top surface of the topmost first-tier sacrificial material layer 142.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
In one embodiment, the first and second insulating cap layers (170, 270) may comprise material which have a higher etch rate than the first and second insulating layers (132, 232) in the etchant used during the first isotropic etching step. For example, the first and second insulating cap layers (170, 270) may comprise a doped silicon oxide, such as borosilicate glass, phosphosilicate glass or borophosphosilicate glass, while the first and second insulating layers (132, 232) may comprise undoped silicon oxide (e.g., silicon dioxide). In this case, the first and second insulating cap layers (170, 270) may be laterally recessed father than first and second insulating layers (132, 232) during the first isotropic etching step. This forms lateral recesses 49R at the level of at least first insulating cap layer 170 above the top surface of the first sacrificial pillar structures 168 and optionally at the level of the second insulating cap layer 270.
Referring to
Referring to
The processing steps described above with reference to
A photoresist layer (not shown) may be applied over the second etch mask layer 377, and may be lithographically patterned to form various openings therethrough. The pattern of the openings may be the same as the pattern of the various second-tier openings (249, 229), which is the same as the sacrificial second-tier opening fill material portions 248. The pattern of openings in the photoresist layer may be transferred through the second etch mask layer 377, and subsequently through the third-tier structure by a third anisotropic etch process to form various third-tier openings concurrently. The photoresist layer may be consumed during the third anisotropic etch process, and the second patterned etch mask layer 377 may be partially consumed and its remaining portion employed thereafter as an etch mask that defines the pattern of the third-tier openings. The various third-tier openings may include third-tier memory openings 349 and second-tier support openings (not shown).
The third-tier memory openings 349 are formed directly on a top surface of a respective one of the sacrificial second-tier memory opening fill material portions 248. In one embodiment, a top surface of a respective second-tier sacrificial memory opening fill structure 248 is physically exposed underneath each third-tier memory opening 349. The third-tier support openings (not shown) are formed directly on a top surface of a respective one of the sacrificial second-tier support opening fill material portions. The thickness of the remaining portion of the second etch mask layer 377 after the second anisotropic etch process may be in a range from 0.1 micron to 1 micron, such as from 0.3 micron to 0.7 micron, although lesser and greater thicknesses may also be employed.
Referring to
Referring to
The additional sacrificial fill material that is grown during the additional selective material deposition process may comprise a carbon-based material, which includes any material that may be employed for the first sacrificial pillar structures. The additional carbon-based material may comprise, for example, amorphous carbon, diamond-like carbon, or a doped carbon material in an amorphous phase or in a nanocrystalline phase. In one embodiment, the additional carbon-based material may comprise carbon atoms at an atomic concentration greater than 90%, such as 95 to 100 atomic percent. The additional carbon-based material may or may not have a same material composition as the first carbon-based material and/or as the second carbon-based material and/or the third carbon-based material. The additional selective material deposition process may be a same type of deposition process as the selective material deposition process that forms the first sacrificial pillar structures 168.
The second sacrificial pillar structures 268 can be formed on the recessed top surfaces of the second-tier sacrificial memory opening fill structures 248 and the second-tier sacrificial support opening fill structures (not illustrated). According to an aspect of the present disclosure, the duration of the additional selective material deposition process may be selected such that the top surfaces of the second sacrificial pillar structures 268 are formed above a horizontal plane including the top surface of the topmost second-tier sacrificial material layer 242 of the second-tier sacrificial material layers 242, and underneath a horizontal plane including a topmost surface of the second-tier structure. In one embodiment, the top surfaces of the second sacrificial pillar structures 268 are formed above a horizontal plane including the bottom surface of the second insulating cap layer 270, and underneath a horizontal plane including a top surface of the second insulating cap layer 270.
Referring to
The second isotropic etch process may be performed before or after the first isotropic etch process. In an illustrative example, the third-tier insulating layers 332, the second-tier insulating layers 232, and the second insulating cap layer 270 may comprise silicon oxide, and the first isotropic etch process may comprise a wet etch process employing dilute hydrofluoric acid. Further, the third-tier sacrificial material layers 342 and the second-tier sacrificial material layers 242 may comprise silicon nitride, and the second isotropic etch process may comprise a wet etch process employing phosphoric acid. In one embodiment, the third-tier memory openings 349 and the top portion of the second-tier memory openings 249 may be laterally expanded such that a lateral dimension (i.e., a maximum lateral extent such as a diameter or a major axis) of a bottom portion of a third-tier memory opening 349 has a greater lateral dimension than a lateral dimension (i.e., a maximum lateral extent such as a diameter or a major axis) of a bottom portion of an underlying second-tier memory opening 249 (i.e., the bottom portion of an underlying second-tier sacrificial memory opening fill structure 248). Further, a lateral dimension (i.e., a maximum lateral extent such as a diameter or a major axis) of a top-portion of the third-tier memory opening 349 has a greater lateral dimension than a lateral dimension (i.e., a maximum lateral extent such as a diameter or a major axis) of the underlying second-tier memory opening 249 at a height of a top surface of the topmost second-tier sacrificial material layer 242.
Optionally, lateral recesses 49R may be formed at the level of the second insulating cap layer 270 above the top surface of the second sacrificial pillar structures 268, as described above with respect to
Referring to
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Referring to
The at least one high etch rate layer 331 may comprise a high etch rate oxide layer 331A and a high etch rate nitride layer 331B formed over the second-tier alternating stack (232, 242) and over the second insulating cap layer 270 prior to forming the third-tier alternating stack (332, 342). The high etch rate oxide layer 331A may comprise a silicon oxide layer which has a higher wet etch rate (e.g., at least 30% higher, such as 50 to 100% higher) than the third insulating layers 332 during the isotropic etch step described above with respect to
Referring to
Referring to
Subsequently, the charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions (e.g., floating gates), for example, by being formed within lateral recesses into sacrificial material layers (142, 242). In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layers (142, 242) and the insulating layers (132, 232) may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layers (142, 242) may be laterally recessed with respect to the sidewalls of the insulating layers (132, 232), and a combination of a deposition process and an anisotropic etch process may be used to form the charge storage layer 54 as a plurality of memory material portions that are vertically spaced apart. The thickness of the charge storage layer 54 may be in a range from 2 nm to 20 nm, although lesser and greater thicknesses may also be used.
The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling may be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the tunneling dielectric layer 56 may be in a range from 2 nm to 20 nm, although lesser and greater thicknesses may also be used. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits.
The semiconductor channel material layer 60L includes a p-doped semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may having a uniform doping. In one embodiment, the semiconductor channel material layer 60L has a p-type doping in which p-type dopants (such as boron atoms) are present at an atomic concentration in a range from 1.0×1012/cm3 to 1.0×1018/cm3, such as from 1.0×1014/cm3 to 1.0×1017/cm3. In one embodiment, the semiconductor channel material layer 60L includes, and/or consists essentially of, boron-doped amorphous silicon or boron-doped polysilicon. In another embodiment, the semiconductor channel material layer 60L has an n-type doping in which n-type dopants (such as phosphor atoms or arsenic atoms) are present at an atomic concentration in a range from 1.0×1012/cm3 to 1.0×1018/cm3, such as from 1.0×1014/cm3 to 1.0×1017/cm3. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in a range from 2 nm to 10 nm, although lesser and greater thicknesses may also be used. A cavity 49′ is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 60L).
Referring to
Referring to
Each remaining portion of the doped semiconductor material of the second conductivity type constitutes a drain region 63. The dopant concentration in the drain regions 63 may be in a range from 5.0×1019/cm3 to 2.0×1021/cm3, although lesser and greater dopant concentrations may also be used. The doped semiconductor material may be, for example, doped poly silicon.
Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60 through which electrical current may flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a charge storage layer 54, and laterally surrounds a vertical semiconductor channel 60. Each adjoining set of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 collectively constitute a memory film 50, which may store electrical charges with a macroscopic retention time. In some embodiments, a blocking dielectric layer 52 may not be present in the memory film 50 at this step, and a blocking dielectric layer may be subsequently formed after formation of backside recesses. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.
Each combination of a memory film 50 and a vertical semiconductor channel 60 within a memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a vertical semiconductor channel 60, a tunneling dielectric layer 56, a plurality of memory elements comprising portions of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of a memory stack structure 55, a dielectric core 62, and a drain region 63 within a memory opening 49 constitutes a memory opening fill structure 58. The in-process source-level material layers 110′, the first-tier structure (132, 142, 170, 165), the second-tier structure (232, 242, 270, 265, 72), the memory opening fill structures 58, and support pillar structures that are formed in the support openings 19 collectively constitute a memory-level assembly.
Referring to
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Referring to
A photoresist layer may be applied over the first contact-level dielectric layer 280 and may be lithographically patterned to form elongated openings that extend along the first horizontal direction hd1 between clusters of memory opening fill structures 58. Backside trenches 79 may be formed by transferring the pattern in the photoresist layer (not shown) through the first contact-level dielectric layer 280, the second-tier structure (232, 242, 270, 265, 72), and the first-tier structure (132, 142, 170, 165), and into the in-process source-level material layers 110′. Portions of the first contact-level dielectric layer 280, the second-tier structure (232, 242, 270, 265, 72), the first-tier structure (132, 142, 170, 165), and the in-process source-level material layers 110′ that underlie the openings in the photoresist layer may be removed to form the backside trenches 79. In one embodiment, the backside trenches 79 may be formed between clusters of memory stack structures 55. The clusters of the memory stack structures 55 may be laterally spaced apart along the second horizontal direction hd2 by the backside trenches 79.
Referring to
Referring to
Wet etch chemicals such as hot TMY and TMAH are selective to doped semiconductor materials such as the p-doped semiconductor material and/or the n-doped semiconductor material of the upper source-level semiconductor layer 116 and the lower source-level semiconductor layer 112. Thus, use of selective wet etch chemicals such as hot TMY and TMAH for the wet etch process that forms the source cavity 109 provides a large process window against etch depth variation during formation of the backside trenches 79. Specifically, even if sidewalls of the upper source-level semiconductor layer 116 are physically exposed or even if a surface of the lower source-level semiconductor layer 112 is physically exposed upon formation of the source cavity 109 and/or the backside trench spacers 77, collateral etching of the upper source-level semiconductor layer 116 and/or the lower source-level semiconductor layer 112 is minimal, and the structural change to the exemplary structure caused by accidental physical exposure of the surfaces of the upper source-level semiconductor layer 116 and/or the lower source-level semiconductor layer 112 during manufacturing steps do not result in device failures. Each of the memory opening fill structures 58 is physically exposed to the source cavity 109. Specifically, each of the memory opening fill structures 58 includes a sidewall and that are physically exposed to the source cavity 109.
Referring to
Referring to
In one embodiment, the doped semiconductor material of the second conductivity type may be deposited on the physically exposed semiconductor surfaces around the source cavity 109 by a selective semiconductor deposition process. A semiconductor precursor gas, an etchant, and a dopant gas may be flowed concurrently into a process chamber including the exemplary structure during the selective semiconductor deposition process. For example, the semiconductor precursor gas may include silane, disilane, or dichlorosilane, the etchant gas may include gaseous hydrogen chloride, and the dopant gas may include a hydride of a dopant atom such as phosphine, arsine, stibine, or diborane. In this case, the selective semiconductor deposition process grows a doped semiconductor material having a doping of the second conductivity type from physically exposed semiconductor surfaces around the source cavity 109. The deposited doped semiconductor material forms a source contact layer 114, which may contact sidewalls of the vertical semiconductor channels 60. The atomic concentration of the dopants of the second conductivity type in the deposited semiconductor material may be in a range from 1.0×1020/cm3 to 2.0×1021/cm3, such as from 2.0×1020/cm3 to 8.0×1020/cm3. The source contact layer 114 as initially formed may consist essentially of semiconductor atoms and dopant atoms of the second conductivity type. Alternatively, at least one non-selective doped semiconductor material deposition process may be used to form the source contact layer 114. Optionally, one or more etch back processes may be used in combination with a plurality of selective or non-selective deposition processes to provide a seamless and/or voidless source contact layer 114.
The duration of the selective semiconductor deposition process may be selected such that the source cavity 109 is filled with the source contact layer 114, and the source contact layer 114 contacts bottom end portions of inner sidewalls of the backside trench spacers 77. In one embodiment, the source contact layer 114 may be formed by selectively depositing a doped semiconductor material having a doping of the second conductivity type from semiconductor surfaces around the source cavity 109. In one embodiment, the doped semiconductor material may include doped polysilicon. Thus, the source-level sacrificial layer 104 may be replaced with the source contact layer 114.
The layer stack including the lower source-level semiconductor layer 112, the source contact layer 114, and the upper source-level semiconductor layer 116 constitutes a buried source layer (112, 114, 116). The set of layers including the buried source layer (112, 114, 116), the source-level insulating layer 117, and the source-select-level conductive layer 118 constitutes source-level material layers 110, which replaces the in-process source-level material layers 110′.
Referring to
An oxidation process may be performed to convert physically exposed surface portions of semiconductor materials into dielectric semiconductor oxide portions. For example, surfaces portions of the source contact layer 114 and the upper source-level semiconductor layer 116 may be converted into dielectric semiconductor oxide plates 122, and surface portions of the source-select-level conductive layer 118 may be converted into annular dielectric semiconductor oxide spacers 124.
Referring to
Backside recesses (143, 243) are formed in volumes from which the sacrificial material layers (142, 242) are removed. The backside recesses (143, 243) include first backside recesses 143 that are formed in volumes from which the first sacrificial material layers 142 are removed and second backside recesses 243 that are formed in volumes from which the second sacrificial material layers 242 are removed. Each of the backside recesses (143, 243) may be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses (143, 243) may be greater than the height of the respective backside recess (143, 243). A plurality of backside recesses (143, 243) may be formed in the volumes from which the material of the sacrificial material layers (142, 242) is removed. Each of the backside recesses (143, 243) may extend substantially parallel to the top surface of the substrate semiconductor layer 9. A backside recess (143, 243) may be vertically bounded by a top surface of an underlying insulating layer (132, 232) and a bottom surface of an overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143, 243) may have a uniform height throughout.
Referring to
At least one conductive material may be deposited in the plurality of backside recesses (143, 243), on the sidewalls of the backside trenches 79, and over the first contact-level dielectric layer 280. The at least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.
In one embodiment, the at least one conductive material may include at least one metallic material, i.e., an electrically conductive material that includes at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recesses (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metallic nitride liner that includes a conductive metallic nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive fill material such as W, Co, Ru, Mo, Cu, or combinations thereof. In one embodiment, the at least one conductive material for filling the backside recesses (143, 243) may be a combination of titanium nitride layer and a tungsten fill material.
Electrically conductive layers (146, 246) may be formed in the backside recesses (143, 243) by deposition of the at least one conductive material. A plurality of first electrically conductive layers 146 may be formed in the plurality of first backside recesses 143, a plurality of second electrically conductive layers 246 may be formed in the plurality of second backside recesses 243, and a continuous metallic material layer (not shown) may be formed on the sidewalls of each backside trench 79 and over the first contact-level dielectric layer 280. Each of the first electrically conductive layers 146 and the second electrically conductive layers 246 may include a respective conductive metallic nitride liner and a respective conductive fill material. Thus, the first and second sacrificial material layers (142, 242) may be replaced with the first and second electrically conductive layers (146, 246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of the backside blocking dielectric layer and a first electrically conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of the backside blocking dielectric layer and a second electrically conductive layer 246. A backside cavity is present in the portion of each backside trench 79 that is not filled with the continuous metallic material layer.
Residual conductive material may be removed from inside the backside trenches 79. Specifically, the deposited metallic material of the continuous metallic material layer may be etched back from the sidewalls of each backside trench 79 and from above the first contact-level dielectric layer 280, for example, by an anisotropic or isotropic etch. Each remaining portion of the deposited metallic material in the first backside recesses constitutes a first electrically conductive layer 146. Each remaining portion of the deposited metallic material in the second backside recesses constitutes a second electrically conductive layer 246. Sidewalls of the first electrically conductive material layers 146 and the second electrically conductive layers may be physically exposed to a respective backside trench 79. The backside trenches may have a pair of curved sidewalls having a non-periodic width variation along the first horizontal direction hd1 and a non-linear width variation along the vertical direction.
Each electrically conductive layer (146, 246) may be a conductive sheet including openings therein. A first subset of the openings through each electrically conductive layer (146, 246) may be filled with memory opening fill structures 58. A second subset of the openings through each electrically conductive layer (146, 246) may be filled with the support pillar structures 20. Each electrically conductive layer (146, 246) may have a lesser area than any underlying electrically conductive layer (146, 246) because of the first and second stepped surfaces. Each electrically conductive layer (146, 246) may have a greater area than any overlying electrically conductive layer (146, 246) because of the first and second stepped surfaces.
In some embodiment, drain-select-level isolation structures 72 may be provided at topmost levels of the second electrically conductive layers 246. A subset of the second electrically conductive layers 246 located at the levels of the drain-select-level isolation structures 72 constitutes drain select gate electrodes. A subset of the electrically conductive layer (146, 246) located underneath the drain select gate electrodes may function as combinations of a control gate and a word line located at the same level. The control gate electrodes within each electrically conductive layer (146, 246) are the control gate electrodes for a vertical memory device including the memory stack structure 55.
Each of the memory stack structures 55 comprises a vertical stack of memory elements located at each level of the electrically conductive layers (146, 246). A subset of the electrically conductive layers (146, 246) may comprise word lines for the memory elements. The semiconductor devices in the underlying peripheral device region 700 may comprise word line switch devices configured to control a bias voltage to respective word lines. The memory-level assembly is located over the substrate semiconductor layer 9. The memory-level assembly includes at least one alternating stack (132, 146, 232, 246) and memory stack structures 55 vertically extending through the at least one alternating stack (132, 146, 232, 246).
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A photoresist layer (not shown) may be applied over the second contact-level dielectric layer 282, and may be lithographically patterned to form various contact via openings. For example, openings for forming drain contact via structures may be formed in the memory array region 100, and openings for forming staircase region contact via structures may be formed in the staircase region 200. An anisotropic etch process is performed to transfer the pattern in the photoresist layer through the second and first contact-level dielectric layers (282, 280) and underlying dielectric material portions. The drain regions 63 and the electrically conductive layers (146, 246) may be used as etch stop structures. Drain contact via cavities may be formed over each drain region 63, and staircase-region contact via cavities may be formed over each electrically conductive layer (146. 246) at the stepped surfaces underlying the first and second retro-stepped dielectric material portions (165, 265). The photoresist layer may be subsequently removed, for example, by ashing.
Drain contact via structures 88 are formed in the drain contact via cavities and on a top surface of a respective one of the drain regions 63. Staircase-region contact via structures 86 are formed in the staircase-region contact via cavities and on a top surface of a respective one of the electrically conductive layers (146, 246). The staircase-region contact via structures 86 may include drain select level contact via structures that contact a subset of the second electrically conductive layers 246 that function as drain select level gate electrodes. Further, the staircase-region contact via structures 86 may include word line contact via structures that contact electrically conductive layers (146, 246) that underlie the drain select level gate electrodes and function as word lines for the memory stack structures 55.
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At least one additional dielectric layer may be formed over the contact-level dielectric layers (280, 282), and additional metal interconnect structures (herein referred to as upper-level metal interconnect structures) may be formed in the at least one additional dielectric layer. For example, the at least one additional dielectric layer may include a line-level dielectric layer 290 that is formed over the contact-level dielectric layers (280, 282). The upper-level metal interconnect structures may include bit lines 98 contacting a respective one of the drain contact via structures 88, and interconnection line structures 96 contacting, and/or electrically connected to, at least one of the staircase-region contact via structures 86 and/or the peripheral-region contact via structures 488. The word line contact via structures (which are provided as a subset of the staircase-region contact via structures 86) may be electrically connected to the word line driver circuit through a subset of the lower-level metal interconnect structures 780 and through a subset of the peripheral-region contact via structures 488.
In one embodiment, the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device, the electrically conductive strips (146, 246) comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device, the substrate 8 comprises a silicon substrate, the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate, and at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate may contain an integrated circuit comprising a driver circuit for the memory device located thereon, the electrically conductive strips (146, 246) comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate 8, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level. The array of monolithic three-dimensional NAND strings comprises a plurality of semiconductor channels 60, wherein at least one end portion of each of the plurality of semiconductor channels 60 extends substantially perpendicular to a top surface of the substrate 8, and one of the plurality of semiconductor channels including the vertical semiconductor channel 60. The array of monolithic three-dimensional NAND strings comprises a plurality of charge storage elements (comprising portions of the memory films 50), each charge storage element located adjacent to a respective one of the plurality of semiconductor channels 60.
Referring to all drawings and according to various embodiments of the present disclosure, a memory device is provided, which comprises: a first-tier alternating stack (132, 146) of first-tier insulating layers 132 and first-tier electrically conductive layers 146; a second-tier alternating stack (232, 246) of second-tier insulating layers 232 and second-tier electrically conductive layers 246 located over the first-tier alternating stack (132, 146); a memory opening fill structure 58 vertically extending through the second-tier alternating stack (232, 246) and the first-tier alternating stack (132, 146) and comprising a memory film 50 and a vertical semiconductor channel 60; and a tubular carbon-based structure 41 laterally surrounded by a topmost first-tier insulating layer 132 within the first-tier alternating stack (132, 146) and laterally surrounding, and contacting, the memory opening fill structure 58.
In one embodiment, the tubular carbon-based structure 41 comprises carbon atoms at an atomic concentration greater than 90%. In one embodiment, the tubular carbon-based structure 41 comprises: an annular top surface located within a horizontal plane including an interface between the first-tier alternating stack (132, 146) and the second-tier alternating stack (232, 246); and an annular bottom surface located above a horizontal plane including a topmost first-tier electrically conductive layer within the first-tier alternating stack (132, 146).
According to another aspect of the present disclosure, a memory device is provided, which comprises: a first-tier alternating stack (132, 146) of first-tier insulating layers 132 and first-tier electrically conductive layers 146; a second-tier alternating stack (232, 246) of second-tier insulating layers 232 and second-tier electrically conductive layers 246 located over the first-tier alternating stack (132, 146); and a memory opening fill structure 58 vertically extending through the second-tier alternating stack (232, 246) and the first-tier alternating stack (132, 146) and comprising a memory film 50 and a vertical semiconductor channel 60, wherein the memory opening fill structure 58 comprises: a first straight section comprising a first cylindrical straight sidewall that vertically extends through each of the first-tier electrically conductive layers 146, a second straight section comprising a second cylindrical straight sidewall that vertically extends through each of the second-tier electrically conductive layers 246, and a laterally-protruding section that laterally protrudes outward from a top periphery of the first cylindrical straight sidewall and from a bottom periphery of the second cylindrical straight sidewall; and wherein a bottom portion of the second straight section has a greater lateral dimension than a top portion of the first straight section.
In one embodiment, the memory device further comprises a third-tier alternating stack (332, 346) of third-tier insulating layers 332 and third-tier electrically conductive layers 346 located over the second-tier alternating stack (232, 246), wherein the memory opening fill structure 58 comprises: a third straight section comprising a third cylindrical straight sidewall that vertically extends through each of the third-tier electrically conductive layers 346, and an additional laterally-protruding section that laterally protrudes outward from a top periphery of the second cylindrical straight sidewall and from a bottom periphery of the third cylindrical straight sidewall; and wherein a bottom portion of the third straight section has a greater lateral dimension than a top portion of the second straight section.
In one embodiment, the memory device further comprises at least one of a layered double oxide layer 231A and an oxygen doped nitride layer 231B located between the second-tier alternating stack (232, 246) and the third-tier alternating stack (332, 346).
In one embodiment, the memory device further comprises a tubular carbon-based structure 41 laterally surrounded by a topmost first-tier insulating layer 132 within the first-tier alternating stack (132, 146) and laterally surrounding, and contacting, the memory opening fill structure 58.
Although the foregoing refers to particular embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Where an embodiment using a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
