Patent Application
20240074170
The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device including dipole-containing blocking dielectric layers and methods of manufacturing the same.
Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
According to an aspect of the present disclosure, a memory device includes an alternating stack of insulating layers and electrically conductive layers arranged along a vertical direction, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film. The memory film includes a blocking dielectric film, a tunneling dielectric layer and a vertical stack of memory elements located between the blocking dielectric film and the tunneling dielectric layer. The blocking dielectric film includes component layers which include, from a side that is proximal to the vertical stack of memory elements toward a side that is distal from the vertical stack of memory elements, an inner silicon oxide blocking dielectric layer, a middle dielectric metal oxide blocking dielectric layer, an outer silicon oxide blocking dielectric layer, and an outer dielectric metal oxide blocking dielectric layer.
According to another aspect of the present disclosure, a method of forming a memory device comprises forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a vertical semiconductor channel and a memory film, forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the memory opening fill structure, and forming electrically conductive layers in the backside recesses. The memory film comprises a blocking dielectric film, a tunneling dielectric layer and a vertical stack of memory elements located between the blocking dielectric film and the tunneling dielectric layer. The blocking dielectric film comprises component layers which comprise, from a side that is proximal to the vertical stack of memory elements toward a side that is distal from the vertical stack of memory elements, an inner silicon oxide blocking dielectric layer, a middle dielectric metal oxide blocking dielectric layer, an outer silicon oxide blocking dielectric layer, and an outer dielectric metal oxide blocking dielectric layer.
As discussed above, the present disclosure is directed to a three-dimensional memory device including dipole-containing blocking dielectric layers and methods of manufacturing the same, the various aspects of which are described below.
The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are used merely to identify similar elements, and different ordinals may be used across the specification and the claims of the instant disclosure. The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. As used herein, an element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, an element is located “directly on” a second element if there exist a physical contact between a surface of the element and a surface of the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein. As used herein, an electrical component is electrically connected to a second electrical component if there exists an electrically conductive path between the electrical component and the second electrical component.
As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/cm to 1.0×105 S/cm upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105 S/cm. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−6 S/cm. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to have electrical conductivity greater than 1.0×105 S/cm. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.
As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.
Generally, a semiconductor package (or a “package”) refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or a “chip”) or a plurality of semiconductor chips that are bonded thereamongst, for example, by flip-chip bonding or another chip-to-chip bonding. A package or a chip may include a single semiconductor die (or a “die”) or a plurality of semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or a chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. Identical concurrent operations can be executed in each plane within a same die, although there may be some restrictions. In case a die is a memory die, i.e., a die including memory elements, concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within a same memory die. Each plane contains a number of memory blocks (or “blocks”), which are the smallest unit that can be erased by in a single erase operation. Each memory block contains a number of pages, which are the smallest units that can be selected for programming.
Referring to
Dielectric material layers are formed over the semiconductor devices, which are herein referred to as lower-level dielectric material layers 760. The lower-level dielectric material layers 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks diffusion of mobile ions and/or apply appropriate stress to underlying structures), first dielectric material layers 764 that overlie the dielectric liner 762, a silicon nitride layer (e.g., hydrogen diffusion barrier) 766 that overlies the first dielectric material layers 764, and at least one second dielectric layer 768.
The dielectric layer stack including the lower-level dielectric material layers 760 functions as a matrix for lower-level metal interconnect structures 780 that provide electrical wiring to and from the various nodes of the semiconductor devices and landing pads for through-memory-level contact via structures to be subsequently formed. The lower-level metal interconnect structures 780 are formed within the dielectric layer stack of the lower-level dielectric material layers 760, and comprise a lower-level metal line structure located under and optionally contacting a bottom surface of the silicon nitride layer 766.
For example, the lower-level metal interconnect structures 780 may be formed within the first dielectric material layers 764. The first dielectric material layers 764 may be a plurality of dielectric material layers in which various elements of the lower-level metal interconnect structures 780 are sequentially formed. Each dielectric material layer selected from the first dielectric material layers 764 may include any of doped silicate glass, undoped silicate glass, organosilicate glass, silicon nitride, silicon oxynitride, and dielectric metal oxides (such as aluminum oxide). In one embodiment, the first dielectric material layers 764 may comprise, or consist essentially of, dielectric material layers having dielectric constants that do not exceed the dielectric constant of undoped silicate glass (silicon oxide) of 3.9. The lower-level metal interconnect structures 780 may include various device contact via structures 782 (e.g., source and drain electrodes which contact the respective source and drain nodes of the device or gate electrode contacts), intermediate lower-level metal line structures 784, lower-level metal via structures 786, and landing-pad-level metal line structures 788 that are configured to function as landing pads for through-memory-level contact via structures to be subsequently formed.
The landing-pad-level metal line structures 788 may be formed within a topmost dielectric material layer of the first dielectric material layers 764 (which may be a plurality of dielectric material layers). Each of the lower-level metal interconnect structures 780 may include a metallic nitride liner and a metal fill structure. Top surfaces of the landing-pad-level metal line structures 788 and the topmost surface of the first dielectric material layers 764 may be planarized by a planarization process, such as chemical mechanical planarization. The silicon nitride layer 766 may be formed directly on the top surfaces of the landing-pad-level metal line structures 788 and the topmost surface of the first dielectric material layers 764.
The at least one second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. Each dielectric material layer selected from the at least one second dielectric material layer 768 may include any of doped silicate glass, undoped silicate glass, and organosilicate glass. In one embodiment, the at least one second dielectric material layer 768 may comprise, or consist essentially of, dielectric material layers having dielectric constants that do not exceed the dielectric constant of undoped silicate glass (silicon oxide) of 3.9.
The region of the semiconductor devices 710 and the combination of the lower-level dielectric material layers 760 and the lower-level metal interconnect structures 780 is herein referred to an underlying peripheral device region 700, which is located underneath a memory-level assembly to be subsequently formed and includes peripheral devices for the memory-level assembly.
Referring to
The doped semiconductor material of the second source-level semiconductor layer 116 may be the same as, or may be different from, the doped semiconductor material of the source-level semiconductor layer 112. For example, the doped semiconductor material may comprise heavily doped polysilicon. Each of the source-level semiconductor layer 112 and the second source-level semiconductor layer 116 may have a thickness in a range from 100 nm to 1,000 nm, although lesser and greater thicknesses may also be employed.
The source-level dielectric layer 103 and the second source-level dielectric layer 105 comprises a dielectric material, such as silicon oxide. Each of the source-level dielectric layer 103 and the second source-level dielectric layer 105 may have a thickness in a range from 5 nm to 200 nm, although lesser and greater thicknesses may also be employed.
The source-level sacrificial material of the source-level sacrificial layer 104 comprises a material that may be removed selective to the doped semiconductor materials of the source-level semiconductor layer 112 and the second source-level semiconductor layer 116. The source-level sacrificial material of the source-level sacrificial layer 104 may comprise silicon nitride, a silicon-germanium alloy, undoped amorphous silicon, undoped polysilicon, organosilicate glass, or any other material that may be subsequently removed selective to the materials of the source-level semiconductor layer 112 and the second source-level semiconductor layer 116. The thickness of the source-level sacrificial layer 104 may be in a range from 50 nm to 600 nm, such as from 100 nm to 300 nm, although lesser and greater thicknesses may also be employed.
A stack of an alternating plurality of insulating layers 32 and sacrificial material layer 42 is formed over the top surface of the in-process source-level material layers 110′. As used herein, a “material layer” refers to a layer including a material throughout the entirety thereof. As used herein, an alternating plurality of elements and second elements refers to a structure in which instances of the elements and instances of the second elements alternate. Each instance of the elements that is not an end element of the alternating plurality is adjoined by two instances of the second elements on both sides, and each instance of the second elements that is not an end element of the alternating plurality is adjoined by two instances of the elements on both ends. The elements may have the same thickness thereamongst, or may have different thicknesses. The second elements may have the same thickness thereamongst, or may have different thicknesses. An alternating plurality of first material layers and second material layers may begin with an instance of the first material layers or with an instance of the second material layers, and may end with an instance of the first material layers or with an instance of the second material layers. In one embodiment, an instance of the elements and an instance of the second elements may form a unit that is repeated with periodicity within the alternating plurality.
The stack of the alternating plurality of insulating layers 32 and sacrificial material layer 42 is herein referred to as an alternating stack (32, 42). In one embodiment, each insulating layer 32 may consist essentially of an insulating material. Insulating materials that can be used for the insulating layers 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the material of the insulating layers 32 can be silicon oxide.
The sacrificial material layers 42 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layers 42 can be subsequently replaced with electrically conductive layers which can function, for example, as control gate electrodes/word lines of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial material layers 42 can be spacer material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium.
In one embodiment, the insulating layers 32 can include silicon oxide, and sacrificial material layers 42 can include silicon nitride sacrificial material layers. The first material of the insulating layers 32 can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the insulating layers 32, tetraethyl orthosilicate (TEOS) can be used as the precursor material for the CVD process. The second material of the sacrificial material layers 42 can be formed, for example, CVD or atomic layer deposition (ALD).
The topmost layer of the alternating stack (32, 42) may be an insulating layer 32, which is hereafter referred to as a topmost insulating layer 32T. The thicknesses of the insulating layers 32 and the sacrificial material layers 42 can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be used for each insulating layer 32 and for each sacrificial material layer 42. The number of repetitions of the pairs of an insulating layer 32 and a sacrificial material layer (e.g., a control gate electrode or a sacrificial material layer) 42 can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be used. The top and bottom gate electrodes in the stack may function as the select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer 42.
Referring to
The stepped cavity 69 can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in steps as a function of the vertical distance from the bottom surface of the buffer dielectric layer 111. In one embodiment, the stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type. As used herein, a “level” of a structure including alternating plurality is defined as the relative position of a pair of a first material layer and a second material layer within the structure.
Each sacrificial material layer 42 other than a topmost sacrificial material layer 42 within the alternating stack (32, 42) laterally extends farther than any overlying sacrificial material layer 42 within the alternating stack (32, 42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32, 42) that continuously extend from a bottommost layer within the alternating stack (32, 42) to a topmost layer within the alternating stack (32, 42).
In one embodiment, all layers of the alternating stack (32, 42) other than the bottommost insulating layer 32 may be patterned to provide stepped surfaces. In this case, each layer of the alternating stack (32, 42) other than the bottommost insulating layer 32 may have a respective physically exposed sidewall that is exposed to the stepped cavity 69. In one embodiment, each physically exposed sidewall of a sacrificial material layer 42 may be vertically coincident with a physically exposed sidewall of a respective overlying or underlying insulating material layer 32. Upon formation of the stepped surfaces, lateral extents of the sacrificial material layers 42 decrease with a vertical distance from the in-process a source-level material layers (112, 103, 104, 105, 116).
Referring to
The stepped dielectric material portion 65 contacts sidewalls of the insulating layers 32 of the alternating stack (32, 42). In one embodiment, the stepped dielectric material portion 65 contacts stepped surfaces of the alternating stack (32, 42), and has a variable lateral extent that increases with a vertical distance from a horizontal plane including an interface between the alternating stack (32, 42) and the in-process source-level material layers (112, 103, 104, 105, 116).
Optionally, drain-select-level isolation structures 72 can be formed through the topmost insulating layer 32T and a subset of the sacrificial material layers 42 located at drain select levels. The drain-select-level isolation structures 72 can be formed, for example, by forming drain-select-level isolation trenches and filling the drain-select-level isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the topmost insulating layer 32T.
Referring to
The memory openings 49 extend through the entirety of the alternating stack (32, 42). The support openings 19 extend through a subset of layers within the alternating stack (32, 42). The chemistry of the anisotropic etch process used to etch through the materials of the alternating stack (32, 42) can alternate to optimize etching of the first and second materials in the alternating stack (32, 42). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the memory openings 49 and the support openings 19 can be substantially vertical, or can be tapered. The patterned lithographic material stack can be subsequently removed, for example, by ashing.
The memory openings 49 and the support openings 19 can extend from the top surface of the alternating stack (32, 42) to on upper portion of the first source-level semiconductor layer 112. A surface of the first to source-level semiconductor layer 112 may be physically exposed at the bottom of each memory opening 49 and at the bottom of each support opening 19.
Referring to
The outer silicon oxide blocking dielectric layer 524 and the inner silicon oxide blocking dielectric layer 522 consists essentially of silicon oxide (e.g., silicon dioxide or non-stoichiometric silicon rich silicon oxide having a silicon to oxygen ration greater than 1:2). Each of the outer silicon oxide blocking dielectric layer 524 and the inner silicon oxide blocking dielectric layer 524 may be deposited by a respective conformal deposition process such as a low pressure chemical vapor deposition process (LPCVD) or atomic layer deposition (ALD). The thickness of the outer silicon oxide blocking dielectric layer 524 may be in a range from 3 nm to 10 nm, although lesser and greater thicknesses may also be employed. The thickness of the inner silicon oxide blocking dielectric layer 522 may be in a range from 3 nm to 30 nm, although lesser and greater thicknesses may also be employed.
The outer dielectric metal oxide blocking dielectric layer 525, the middle dielectric metal oxide blocking dielectric layer 523, and the inner dielectric metal oxide blocking dielectric layer 521 includes a respective dielectric metal oxide material. The dielectric metal oxide materials of the outer dielectric metal oxide blocking dielectric layer 525, the middle dielectric metal oxide blocking dielectric layer 523, and the inner dielectric metal oxide blocking dielectric layer 521 may be the same, or may be different. Generally, the dielectric metal oxide material of each of the outer dielectric metal oxide blocking dielectric layer 525, the middle dielectric metal oxide blocking dielectric layer 523, and the inner dielectric metal oxide blocking dielectric layer 521 may be independently selected from aluminum oxide or a dielectric transition metal oxide material. Exemplary dielectric transition metal oxide materials that may be employed for any of the outer dielectric metal oxide blocking dielectric layer 525, the middle dielectric metal oxide blocking dielectric layer 523, and/or the inner dielectric metal oxide blocking dielectric layer 521 include tantalum oxide, hafnium oxide, lanthanum oxide, yttrium oxide, zirconium oxide, niobium oxide, other dielectric transition metal oxides, and alloys or layer stacks thereof. In an illustrative example, each of the outer dielectric metal oxide blocking dielectric layer 525, the middle dielectric metal oxide blocking dielectric layer 523, and the inner dielectric metal oxide blocking dielectric layer 521 may comprise, and/or may consist essentially of, aluminum oxide (e.g., Al2O3). Each of the outer dielectric metal oxide blocking dielectric layer 525, the middle dielectric metal oxide blocking dielectric layer 523, and the inner dielectric metal oxide blocking dielectric layer 521 may be deposited by a respective conformal deposition process such as on low pressure chemical vapor deposition process or an atomic layer deposition process.
The thickness of the outer dielectric metal oxide blocking dielectric layer 525 may be in a range from 3 nm to 12 nm, although lesser and greater thicknesses may also be employed. The thickness of the middle dielectric metal oxide blocking dielectric layer 523 may be in a range from 0.6 nm to 4 nm, such as from 1.2 nm to 3 nm, although lesser and greater thicknesses may also be employed. The thickness of the inner dielectric metal oxide blocking dielectric layer 521 may be in a range from 0.6 nm to 4 nm, such as from 1.2 nm to 3 nm, although lesser and greater thicknesses may also be employed. Generally, the thickness of the middle dielectric metal oxide blocking dielectric layer 523 may be less than one half of the thickness of the outer silicon oxide blocking dielectric layer 524, and maybe less than one half of the thickness of the inner silicon oxide blocking dielectric layer 522. The thickness of the inner dielectric metal oxide blocking dielectric layer 521 may be the same as, or about the same as, the thickness of the middle dielectric metal oxide blocking dielectric layer 523.
According to an aspect of the present disclosure, a first electric dipole interface EDI1 is formed between the outer silicon oxide blocking dielectric layer 524 and the middle dielectric metal oxide blocking dielectric layer 523. The first electric dipole interface EDI1 has a dipole moment pointing from the outer silicon oxide blocking dielectric layer 524 toward the middle dielectric metal oxide blocking dielectric layer 523. Generally, the material of the middle dielectric metal oxide blocking dielectric layer 523 is a selected such that the middle dielectric metal oxide blocking dielectric layer 523 has a higher atomic density of oxygen atoms than the outer silicon oxide blocking dielectric layer 524. Without wishing to be bound by a particular theory, it is believed that oxygen atoms are transferred from a surface portion of the middle dielectric metal oxide blocking dielectric layer 523 to a surface portion of the outer silicon oxide blocking dielectric layer 524 upon deposition of the middle dielectric metal oxide blocking dielectric layer 523 on an inner sidewall of the outer silicon oxide blocking dielectric layer 524. As a consequence, it is believed that a surface portion of the middle dielectric metal oxide blocking dielectric layer 523 that is proximal to the outer silicon oxide blocking dielectric layer 524 should contain oxygen vacancies at a higher vacancy concentration than a surface portion of the outer silicon oxide blocking dielectric layer 524 that is proximal to the middle dielectric metal oxide blocking dielectric layer 523. Without wishing to be bound by a particular theory, it is believed that this oxygen vacancy transfer is responsible for generation of electric dipole moments at an interface between the middle dielectric metal oxide blocking dielectric layer 523 and the outer silicon oxide blocking dielectric layer 524, and formation of the first electric dipole interface EDI1. The first electric dipole interface EDI1 continuously extends across the entirety of the interface between the middle dielectric metal oxide blocking dielectric layer 523 and the outer silicon oxide blocking dielectric layer 524.
In one embodiment, the middle dielectric metal oxide blocking dielectric layer 523 consists essentially of aluminum oxide or a dielectric transition metal oxide material. In one embodiment, the middle dielectric metal oxide blocking dielectric layer 523 has a thickness that is less than one half of a thickness of the inner silicon oxide blocking dielectric layer 522, and is less than one half of a thickness of the outer silicon oxide blocking dielectric layer 524. In one embodiment, the outer dielectric metal oxide blocking dielectric layer 525 consists essentially of aluminum oxide.
In one embodiment, a second electric dipole interface EDI2 is present between the inner silicon oxide blocking dielectric layer 522 and the first electric dipole interface EDI1. In one embodiment, the second electric dipole interface EDI2 has a dipole moment pointing from the inner silicon oxide blocking dielectric layer 522 toward the first electric dipole interface EDI1.
In one embodiment, the first electric dipole interface EDI1 is located entirely within the blocking dielectric film 52, which includes the first subset of the component layers. In this case, the first electric dipole interface EDI1 may vertically extend through a plurality of sacrificial material layers 42 within the alternating stack (32, 42). In one embodiment, the second electric dipole interface EDI2 is located entirely within the blocking dielectric film 52. The second electric dipole interface EDI2 may vertically extend through a plurality of sacrificial material layers 42 within the alternating stack (32, 42).
Referring to
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Generally, the memory material layer 54 may comprise any memory material such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store data bits in the form of presence or absence of electrical charges, a direction of ferroelectric polarization, electrical resistivity, or another measurable physical parameter. In one embodiment, the memory material layer 54 can be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the memory material layer 54 can include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions (e.g., floating gates), for example, by being formed within lateral recesses into sacrificial material layers 42. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layers 42 and the insulating layers 32 can have vertically coincident sidewalls, and the memory material layer 54 can be formed as a single continuous layer.
The memory material layer 54 can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. The thickness of the memory material layer 54 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. Each tubular portion of the memory material layer 54 that laterally surrounds a respective memory opening 49 constitutes a memory element that can store data therein. In case the memory material layer 54 comprises a charge storage layer including a charge storage material, such as silicon nitride, each memory element may be a charge storage element. Generally, each portion of the memory material layer 54 located within a respective memory opening 49 comprises a vertical stack of memory elements. Each tubular portion of the memory material layer located at a level of a sacrificial material layer 42, i.e., between a horizontal plane including the bottom surface of the sacrificial material layer 42 and a horizontal plane including the top surface of the sacrificial material layer 42, constitutes a memory element.
In one embodiment, each vertical stack of memory elements comprise portions of a charge storage layer that vertically extends continuously through a plurality of sacrificial material layers 42, and/or through each of the sacrificial material layers 42, within the alternating stack (32, 46). In the first embodiment employing the configuration illustrated in
The dielectric material liner 56 is an optional material layer that may, or may not, be employed. In case the memory material layer 54 comprises a charge storage layer, the dielectric material liner 56 may comprise a tunneling dielectric layer including a dielectric material through which charge tunneling may be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The dielectric material liner 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the dielectric material liner 56 may include a stack of a silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the dielectric material liner 56 may include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the dielectric material liner 56 may be in a range from 2 nm to 20 nm, although lesser and greater thicknesses may also be used.
The combination of the blocking dielectric film 52, the memory material layer 54, and the dielectric material liner 56 is herein referred to as a memory film 50. The memory film 50 can be a stack of continuous material layers that extend into each of the memory openings 49 and the support openings 19.
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Each remaining portion of the doped semiconductor material of the second conductivity type constitutes a drain region 63. The dopant concentration in the drain regions 63 may be in a range from 5.0×1018/cm3 to 2.0×1021/cm3, although lesser and greater dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.
Each remaining portion of the thinned semiconductor channel material layer 60T constitutes a vertical semiconductor channel 60 through which electrical current may flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A dielectric material liner 56 is surrounded by a memory material layer 54, and laterally surrounds a vertical semiconductor channel 60. Each adjoining set of a blocking dielectric film 52, a memory material layer 54, and a dielectric material liner 56 collectively constitute a memory film 50, which may store electrical charges with a macroscopic retention time in some embodiments. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.
Each combination of a memory film 50 and a vertical semiconductor channel 60 within a memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a vertical semiconductor channel 60, a dielectric material liner 56, a plurality of memory elements comprising portions of a memory material layer 54, and a blocking dielectric film 52. Each combination of a memory stack structure 55, a dielectric core 62, and a drain region 63 within an memory opening 49 constitutes a memory opening fill structure 58. Generally, memory opening fill structures 58 are formed within the memory openings 49. Each of the memory opening fill structures 58 comprises a respective memory film 50 and a respective vertical semiconductor channel 60.
Referring to
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A photoresist layer (not shown) can be applied over the contact-level dielectric layer 80, and is lithographically patterned to form openings in areas between clusters of memory opening fill structures 58. The pattern in the photoresist layer can be transferred through the contact-level dielectric layer 80, the alternating stack (32, 42) and/or the stepped dielectric material portion 65 using an anisotropic etch to form through-stack trenches 79, which vertically extend from the top surface of the contact-level dielectric layer 80 at least to the top surface of the source-level sacrificial layer 104.
In one embodiment, the through-stack trenches 79 can laterally extend along a first horizontal direction hd1 and can be laterally spaced apart one from another along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The memory opening fill structures 58 can be arranged in rows that extend along the first horizontal direction hd1. The drain-select-level isolation structures 72 can laterally extend along the first horizontal direction hd1. Each through-stack trench 79 can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd1). Each drain-select-level isolation structure 72 can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd1 that is invariant with translation along the first horizontal direction hd1. Multiple rows of memory opening fill structures 58 can be located between a neighboring pair of a through-stack trench 79 and a drain-select-level isolation structure 72, or between a neighboring pair of drain-select-level isolation structures 72. In one embodiment, the through-stack trenches 79 can include a source contact opening in which a source contact via structure can be subsequently formed. The photoresist layer can be removed, for example, by ashing.
Referring to
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Subsequently, a sequence of isotropic etch processes may be performed to remove physically exposed portions of the memory films 50. The first and second dielectric liners (103, 104) may be collaterally etched during removal of the physically exposed portions of the memory films 50, For example, the sequence of isotropic etch processes may sequentially etch portions of the blocking dielectric film 52, memory material layers 54, and the dielectric material liners 56. A cylindrical outer surface segment of each vertical semiconductor channel 60 can be physically exposed to the source cavity 109.
Referring to
Alternatively, the source contact layer 114 may be formed by a non-selective doped semiconductor deposition process. In this case, a doped semiconductor material can be deposited on all physically exposed surfaces of the first exemplary structure. The duration of the non-selective doped semiconductor deposition process can be selected such that the entire volume of the source cavity 109 is filled with the doped semiconductor material. An etch back process can be performed to remove portions of the doped semiconductor material that are present in the through-stack trenches 79 or above the contact-level dielectric layer 80. The etch back process may comprise an isotropic etch process or an anisotropic etch process. The remaining portion of the doped semiconductor material that fills the source cavity 109 constitutes the source contact layer 114.
The combination of the first source-level semiconductor layer 112, the source contact layer 114, and the second source-level semiconductor layer 116 constitutes source-level material layers (112, 114, 116). Generally, the source-level material layers (112, 114, 116) comprise at least one semiconductor material layer including a doped semiconductor material. In one embodiment, each of the first source-level semiconductor layer 112, the source contact layer 114, and the second source-level semiconductor layer 116 may be a doped semiconductor (e.g., polysilicon) layer having a doping of the second conductivity type, which is the opposite of the first conductivity type of the vertical semiconductor channels 60. As such, p-n junctions may be formed between the source contact layer 114 and the vertical semiconductor channels 60. The dopant concentrations in the first source-level semiconductor layer 112, the source contact layer 114, and the second source-level semiconductor layer 116 may be different from each other. In one embodiment, each of the vertical semiconductor channels 60 comprises a respective cylindrical surface in contact with a respective surface segment of the source contact layer 114.
Referring to
The etch process that removes the second material selective to the first material and the outermost layer of the memory films 50 can be a wet etch process using a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the through-stack trenches 79. For example, if the sacrificial material layers 42 include silicon nitride, the etch process can be a wet etch process in which the exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials used in the art. The support pillar structure 20, the stepped dielectric material portion 65, and the memory opening fill structures 58 provide structural support while the backside recesses 43 are present within volumes previously occupied by the sacrificial material layers 42. Generally, the backside recesses 43 can be formed by removing the sacrificial material layers 42 selective to the insulating layers 32 and the memory opening fill structures 58.
Referring to
In one embodiment, the at least one conductive material may include at least one metallic material, i.e., an electrically conductive material that includes at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recesses include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metallic nitride liner that includes a conductive metallic nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive fill material such as W, Co, Ru, Mo, Cu, or combinations thereof. In one embodiment, the at least one conductive material for filling the backside recesses may be a combination of titanium nitride layer and a tungsten fill material. Electrically conductive layers 46 may be formed in the backside recesses 43 by deposition of the at least one conductive material. A plurality of electrically conductive layers 46 may be formed in the plurality of backside recesses 43, and a continuous metallic material layer (not shown) may be formed on the sidewalls of each through-stack trench 79 and over the contact-level dielectric layer 80. Each of the electrically conductive layers may include a respective conductive metallic nitride liner and a respective conductive fill material. A backside cavity is present in the portion of each through-stack trench 79 that is not filled with the continuous metallic material layer.
Residual conductive material may be removed from inside the through-stack trenches 79. Specifically, the deposited metallic material of the continuous metallic material layer may be etched back from the sidewalls of each through-stack trench 79 and from above the contact-level dielectric layer 80, for example, by an anisotropic or isotropic etch. Each remaining portion of the deposited metallic material in the backside recesses 43 constitutes an electrically conductive layer 46. Sidewalls of the electrically conductive material layers 46 may be physically exposed to a respective through-stack trench 79.
Each electrically conductive layer 46 may be a conductive sheet including openings therein. A subset of the openings through each electrically conductive layer 46 may be filled with memory opening fill structures 58. A second subset of the openings through each electrically conductive layer 46 may be filled with the support pillar structures 20. A subset of the electrically conductive layers 46 may comprise word lines for the memory elements. The underlying semiconductor devices 720 may comprise word line switch devices configured to control a bias voltage to respective word lines, and/or bit line driver devices, such as sense amplifiers.
The lateral extents of the electrically conductive layers 46 decrease with a vertical distance from the at least one semiconductor material layer (112, 114, 116). The dielectric material portion 65 contacts stepped surfaces of the alternating stack (32, 46), and has a variable lateral extent that increases stepwise with a vertical distance from a horizontal plane including an interface between the alternating stack (32, 46) and the at least one semiconductor material layer (112, 114, 116).
Referring to
Referring to
In some embodiments, the blocking dielectric film 52 has a cylindrical configuration within the memory opening 49. In one embodiment, a first electric dipole interface EDI1 is present between the outer silicon oxide blocking dielectric layer 524 and the middle dielectric metal oxide blocking dielectric layer 523, the first electric dipole interface EDI1 having a dipole moment pointing from the outer silicon oxide blocking dielectric layer 524 toward the middle dielectric metal oxide blocking dielectric layer 523.
In one embodiment, the middle dielectric metal oxide blocking dielectric layer 523 has a higher atomic density of oxygen atoms than the outer silicon oxide blocking dielectric layer 524. In one embodiment, a surface portion of the middle dielectric metal oxide blocking dielectric layer 523 that is proximal to the outer silicon oxide blocking dielectric layer 524 comprises oxygen vacancies at a higher vacancy concentration than a surface portion of the outer silicon oxide blocking dielectric layer 524 that is proximal to the middle dielectric metal oxide blocking dielectric layer 523.
In one embodiment, the middle dielectric metal oxide blocking dielectric layer 523 consists essentially of aluminum oxide. In one embodiment, the middle dielectric metal oxide blocking dielectric layer 523 has a thickness that is less than one half of a thickness of the inner silicon oxide blocking dielectric layer 522, and is less than one half of a thickness of the outer silicon oxide blocking dielectric layer 524. In one embodiment, the outer dielectric metal oxide blocking dielectric layer 525 consists essentially of aluminum oxide.
In one embodiment, the vertical stack of memory elements comprises portions of a charge storage layer (e.g., the memory material layer 54) that vertically extends continuously through a plurality of electrically conductive layers 46 within the alternating stack (32, 46). In one embodiment, the inner silicon oxide blocking dielectric layer 522 is in contact with an outer sidewall of the charge storage layer.
In one embodiment, the blocking dielectric film 52 further comprises an inner dielectric metal oxide blocking dielectric layer 521 that contacts an inner sidewall of the inner silicon oxide blocking dielectric layer 522 and an outer sidewall of the charge storage layer. In one embodiment, a second electric dipole interface EDI2 is present between the inner silicon oxide blocking dielectric layer 522 and the first electric dipole interface EDI1, the second electric dipole interface EDI2 having a dipole moment pointing from the inner silicon oxide blocking dielectric layer 522 toward the first electric dipole interface EDI1. In one embodiment, the inner dielectric metal oxide blocking dielectric layer 521 consists essentially of aluminum oxide.
Comparison of the band diagrams of
According to an aspect of the present disclosure, when a dielectric metal oxide material (such as aluminum oxide) and a silicon oxide material come into contact with each other, oxygen ion may move from the dielectric metal oxide material into the silicon oxide material due to the differences in the oxygen atomic density in the two dielectric materials. Negative charges may accumulate on the silicon oxide side of the interface, and positive charges may accumulate on the dielectric metal oxide material of the interface, thereby forming dipole moments. By inserting a layer of the dielectric metal oxide material (such as the middle dielectric metal oxide blocking dielectric layer 523 and/or the inner dielectric metal oxide blocking dielectric layer 521) between a silicon oxide layer (such as the outer silicon oxide blocking dielectric layer 524 and/or the inner silicon oxide blocking dielectric layer 522) and a charge storage layer (such as a silicon nitride layer), charge pairs are formed at an interface between the layer of the dielectric metal oxide material and the silicon oxide layer. The negative charges in a surface region of the silicon oxide layer locally raise the conduction band of a region of the silicon oxide layer proximate to the interface, and the positive charges in a surface region of the layer of the dielectric metal oxide locally lower the conduction band in the layer of the dielectric metal oxide proximate to the interface. This local band offset reduces electron tunneling between the charge storage layer and the electrically conductive layers 46 during the programming operations, and thus, improves programming efficiency of the device.
Generally, as a charge storage layer becomes thinner, the efficiency of electron capture during a programming operation decreases, and the program slope during a programming operation degrades. However, the range of threshold voltage distribution decreases as the effect of nearest-word-line interference decreases, and the programming voltage window for a programming operation increases. Further, fresh data retention time increases as a thinner charge storage layer decreases electron lateral diffusion through traps.
Given the above considerations, the introduction of one or both electric dipole interfaces (EDI1, EDI2) of the embodiments of present disclosure, especially when combined with reduction in the thickness of a charge storage layer, is expected to reduce the threshold voltage distribution and to increase fresh date retention without degrading the program slope.
Furthermore, the device of the second embodiment is configured to improve the fresh data retention and fresh PD budget (e.g., threshold voltage distribution width). Without wishing to be bound by a particular theory, it is believed that the structure of the second embodiment reduces undesired aluminum diffusion and electron trap site generation, which decreases electron lateral diffusion via these traps, while maintaining the advantages of the combination of dipole and thinner charger storage layer. Furthermore, the device of the second embodiment may also improve erase saturation improvement.
Referring to
Referring to
At least one conductive material can be deposited in each of the via cavities, and excess portions of the at least one conductive material can be removed from above the horizontal plane including the top surface of the contact-level dielectric layer 80. Each remaining portion of the at least one conductive material constitutes a via structure (88, 86, 84). The via structures (8886, 84) comprise drain contact via structures 88 formed in the drain contact via cavities and contacting a top surface of a respective one of the drain regions 63. Thus, the drain contact via structures 88 vertically extend through the contact-level dielectric layer 80 and contact an end surface of a respective one of the memory opening fill structures 58. The via structures (88, 86, 84) further comprise layer contact via structures 86 formed in the layer contact via cavities and contacting a top surface of a respective one of the electrically conductive layers 46. The via structures (88, 86, 84) further comprise connection via structures 84 formed in the connection via cavities and extending into the source-level material layers (112, 114, 116). The connection via structures 84 are also referred to as through-memory-level connection via structures. Distal end surfaces of the drain contact via structures 88, distal end surfaces of the layer contact via structures 86, and distal end surfaces of the connection via structures 84 can be located within a same horizontal plane, such as a horizontal plane including the top surface of the contact-level dielectric layer 80.
A via-level dielectric layer 190 is formed over the contact-level dielectric layer 80. Various connection via structures (198, 196, 194) can be formed through the via-level dielectric layer 190. For example, bit line connection via structures 198 can be formed on the drain contact via structures 88, word line connection via structures 196 can be formed on the layer contact via structures 86, and peripheral extension via structures 194 can be formed on the connection via structures 84.
A first line-level dielectric layer 90 is deposited over the via-level dielectric layer 190. Various metal line structures (98, 96, 94) are formed in the first line-level dielectric layer 90. The metal line structures (98, 96, 94) are herein referred to as first line level metal interconnect structures. The various metal line structures (98, 96, 94) include bit lines 98 that are electrically connected to a respective plurality of the drain contact via structures 88 (for example, through the bit line connection via structures 198), a word-line-connection metal interconnect lines 96 that are electrically connected to a respective one of the layer contact via structures 86 (for example, through a word line connection via structure 196), and peripheral metal interconnect lines 94 that are electrically connected to a respective one of the connection via structures 94 (for example, through a peripheral extension via structure 194).
The bit lines 98 are electrically connected to upper ends of a respective subset of the vertical semiconductor channels 60 in the memory opening fill structures 58 in the memory array region 100. In one embodiment, the memory opening fill structures 58 are arranged in rows that extend along the first horizontal direction hd1, and the bit lines 98 laterally extend along the second horizontal direction hd2.
Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
