Information
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Patent Application
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20230301105
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Publication Number
20230301105
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Date Filed
May 24, 2023a year ago
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Date Published
September 21, 20239 months ago
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Inventors
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Original Assignees
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CPC
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International Classifications
- H10B43/27
- H01L21/768
- H01L23/522
- H01L21/28
- H10B43/35
- H10B43/40
Abstract
Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a TSC. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack. The TSC extends vertically through the staircase structure of the memory stack. The TSC includes a conductor layer and a spacer circumscribing the conductor layer.
Claims
- 1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers, wherein the memory stack comprises stairs in a staircase region; anda through stair contact (TSC) extending through the memory stack in the staircase region, wherein the TSC comprises a first conductor layer and a first spacer circumscribing the first conductor layer, and the first conductor layer of the TSC is insulated from the conductive layers of the memory stack by the first spacer.
- 2. The 3D memory device of claim 1, wherein the first spacer comprises a dielectric material.
- 3. The 3D memory device of claim 1, further comprising a channel structure extending through the memory stack in a core array region adjacent to the staircase region.
- 4. The 3D memory device of claim 3, wherein the TSC extends vertically through a smaller number of the conductive layers and dielectric layers of the memory stack than the channel structure.
- 5. The 3D memory device of claim 1, further comprising a first substrate on which the memory stack is formed.
- 6. The 3D memory device of claim 5, wherein the first substrate comprises silicon, and the TSC is in contact with the first substrate.
- 7. The 3D memory device of claim 1, further comprising a peripheral contact outside of the memory stack, wherein the peripheral contact comprises a second conductor layer and a second spacer circumscribing the second conductor layer.
- 8. The 3D memory device of claim 1, further comprising a word line contact in contact with one of the conductive layers of the memory stack in the staircase region.
- 9. The 3D memory device of claim 8, wherein a cross-section of the word line contact and a cross-section of the TSC have a same shape.
- 10. The 3D memory device of claim 1, wherein a cross-section of the TSC has a circular shape.
- 11. The 3D memory device of claim 1, further comprising a peripheral device above or below the memory stack.
- 12. The 3D memory device of claim 11, further comprising a second substrate on which the peripheral device is formed.
- 13. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers;a channel structure extending through the memory stack in a first region; anda through stair contact (TSC) extending through the memory stack in a second region different from the first region, wherein the TSC extends through a smaller number of the conductive layers and dielectric layers of the memory stack than the channel structure, and the TSC comprises a conductor layer and a spacer laterally surrounding the conductor layer.
- 14. The 3D memory device of claim 13, further comprising a word line contact in contact with one of the conductive layers of the memory stack in the first region.
- 15. The 3D memory device of claim 14, wherein a lateral dimension of the word line contact is less than a lateral dimension of the conductor layer of the TSC.
- 16. The 3D memory device of claim 14, wherein the word line contact and the conductor layer of the TSC comprise a same conductive material.
- 17. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers, wherein the memory stack comprises stairs in a staircase region;a word line contact in contact with one of the conductive layers of the memory stack in the staircase region; anda through stair contact (TSC) extending through the memory stack in the staircase region, wherein the TSC and the word line contact each comprise a conductor layer having a same material.
- 18. The 3D memory device of claim 17, wherein the TSC further comprises a spacer circumscribing the conductor layer, and the conductor layer of the TSC is insulated from the conductive layers of the memory stack by the spacer.
- 19. The 3D memory device of claim 17, further comprising a channel structure extending through the memory stack in a core array region adjacent to the staircase region.
- 20. The 3D memory device of claim 17, further comprising a substrate on which the memory stack is formed, and the TSC is in contact with the substrate.
Continuations (3)
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Number |
Date |
Country |
Parent |
17097635 |
Nov 2020 |
US |
Child |
18201660 |
|
US |
Parent |
16292268 |
Mar 2019 |
US |
Child |
17097635 |
|
US |
Parent |
PCT/CN2019/070009 |
Jan 2019 |
WO |
Child |
16292268 |
|
US |