Patent Application
20140266286
The present disclosure is generally related to through-substrate via in semiconductor devices.
Advances in technology have resulted in smaller and more powerful computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular telephones and internet protocol (IP) telephones, can communicate voice and data packets over wireless networks. Further, many such wireless telephones include other types of devices that are incorporated therein. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such wireless telephones can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these wireless telephones can include significant computing capabilities.
A modern electrical system or device (e.g., a wireless telephone) may include a variety of electrical devices. The electrical devices may be arranged on different chips according to design, performance, and/or processing criteria. The chips may be stacked, bonded, and packaged in such a way that the electrical devices located on the chips are electrically connected and function together as a system.
To electrically connect the devices on the different chips, through-substrate via (TSV) technology may be used. TSVs may be formed in a silicon, or other substrate such as glass, chip with other integrated circuit (IC) devices using semiconductor processes (e.g., lithography, etching, deposition, and surface polish and planarization). The chips are then stacked and electrically connected through the TSVs. TSVs may also be formed on chips with no active devices, such as passive interposer chips, or passive interposer die.
To verify that the TSVs are properly fabricated, a continuity test may be performed. Typically, a single side of the chip is accessible for testing while the other side is used to support the chip. As a result, continuity testing may be postponed until stacking and bonding has been performed.
This disclosure presents particular embodiments of TSVs with a fuse structure. When only a single side of a chip is accessible for testing while the other side is used to support the chip, directly testing continuity from one side of the chip to the other is difficult before stacking and bonding is performed. Use of the fuse structure may solve difficulties of performing a continuity test to detect defects of the TSVs.
In a particular embodiment, a device includes a conductive via to provide an electrical path through a substrate. The device further includes a conductive element. The device further includes a fuse coupled to the conductive via and coupled to the conductive element to provide a conductive path between the conductive via and the conductive element. The conductive path enables testing of the continuity of the conductive via. The fuse is configured to be disabled after the testing of the continuity of the conductive via.
In another particular embodiment, a device includes means for establishing a first electrical path through a substrate. The device further includes means for establishing a second electrical path. The device further includes means for establishing a permanently severable conductive path between the first electrical path and the second electrical path. The permanently severable conductive path enables testing of the continuity of the first electrical path through the substrate. The permanently severable conductive path may be severed after the testing of the continuity of the first electrical path.
In another particular embodiment, a method includes testing continuity of at least a portion of a conductive via and a conductive element through a fuse that provides a conductive path between the conductive via and the conductive element. The method further includes disabling the fuse after testing the continuity.
In another particular embodiment, a non-transitory computer-readable medium includes instructions that, when executed by a processor, cause the processor to perform operations including initiating testing continuity of at least a portion of a conductive via and a conductive element through a fuse. The fuse provides a conductive path between the conductive via and the conductive element. The operations further include initiating disabling the fuse after testing the continuity.
In another particular embodiment, a method includes receiving a data file including design information corresponding to a semiconductor device. The method further includes fabricating the semiconductor device according to the design information. The semiconductor device includes a conductive via to provide an electrical path through a substrate, a conductive element, and a fuse coupled to the conductive via and coupled to the conductive element to provide a conductive path between the conductive via and the conductive element.
One particular advantage provided by at least one of the disclosed embodiments is that, when no appropriate device is available to electrically connect with the TSVs to constitute a continuous conductive path, a continuity test can still be applied to detect defects of the TSVs through a fuse which is formed during fabrication of the TSVs and which may be disabled after the continuity test. For example, when only one side of a TSV is accessible for continuity testing, a conductive path may be formed through the TSV, a fuse, and a second conductive element that is accessible for testing, where the fuse may later be deactivated.
Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.
The present disclosure describes particular embodiments in specific contexts, such as designs of through-substrate vias (TSVs) with a fuse structure and methods of making and testing the TSV with the fuse structure. However, features, methods, structures or characteristics described according to the particular embodiments may also be combined in other suitable manners to form one or more other embodiments. In addition, the drawings illustrate relative relationships between the features, methods, structures, or characteristics, and thus may not be drawn in scale.
Referring to
The semiconductor device 100 may include conductive elements 111, 113. In a particular embodiment the conductive elements 111, 113 are conductive vias. For example, the conductive elements 111, 113 may be TSVs or TGVs. Thus, as illustrated by
Each of the conductive vias 110, 112 may be paired with one of the conductive elements 111, 113. Each via-element pair 110, 111 and 112, 113 may be coupled through a fuse 120, 121 that, when intact, provides a conductive path between the conductive vias 110, 112 and the conductive elements 111, 113. For example, referring to
The conductive via 110, the fuse 120, and the conductive element 111 may form a second conductive path 140 and a third conductive path 141. The second conductive path 140 may include a first end and a second end, where both the first end and the second end are accessible from one side of the semiconductor device 100. For example, the ends of the second conductive path 140 may be accessible from a bottom side 108 of the semiconductor device 100. As an additional example, ends of the third electrical path 141 may be accessible from a top side 106 of the semiconductor device 100.
Alternatively, one end of the second conductive path 140 may be accessible from the bottom side 108 and the other end of the second conductive path 140 may be attached to a reference voltage source (not shown), a reference current source (not shown), or a reference heat source (now shown). Similarly, one end of the third conductive path 141 may be accessible from the top side 106 and the other end of the third conductive path 141 may be attached to the reference voltage source, the reference current source, or the reference heat source.
In operation, the second conductive path 140 and the third conductive path 141 may enable testing of connectivity of the conductive via 110. For example, the testing may include applying a voltage, an electrical current, or heat to one end of the second conductive path 140. The voltage, the electrical current, or the heat may be applied by coupling a voltage source, an electrical current source, or a heat source to the conductive vias 110, 112 or to the conductive elements 111, 113. The testing may further include sensing the voltage, the electrical current, or the heat at the other end of the second conductive path 140. Because the fuse 120 forms a conductive path between the conductive via 110 and the conductive element 111, the fuse 120 enables sensing a voltage, an electrical current, or heat applied to one end of the second conductive path 140 from the other end of the second conductive path 140. Similarly, the fuse 120 enables sensing a voltage, an electrical current, or heat applied to one end of the third conductive path 141 from the other end of the third conductive path 141.
When the conductive vias 110, 112 are formed, a fabrication process may cause defects (e.g., openings or voids) in the conductive vias 110, 112. For example, the conductive via 112 is shown in
After the continuity tests are performed, the fuses 120, 121 can be disabled (e.g., blown), such as by use of a laser beam 160 or an electrical current. For example, the fuse 121 may be irradiated by the laser beam 160 and may become non-conductive (e.g., due to mechanical failure or ablation of a portion of the fuse 121) as a result of the irradiation. As another example, a large electrical current may be passed through the fuse 121, which may cause the fuse 121 to become non-conductive, such as due to failure of a portion of the fuse 121 due to resistive heating of the portion in response to the electrical current. Disabling the fuses 120, 121 prevents or at least inhibits conduction through the fuses 120, 121 during the operation of the semiconductor device.
In the case that only one side of the device 100 may be accessed (e.g., the other side of the device may be coupled to a support mechanism during a manufacturing process) testing continuity of the electrical paths through the substrate 105 may be difficult. Further, when the semiconductor device 100 is an interposer die, continuity testing before assembling the semiconductor device 100 with one or more other devices (e.g., devices that are intended to be used during normal device operation) may identify problems early in a manufacturing process. However, when there are no operational devices on the substrate 105 or on the device layer 104 continuity testing may be difficult. The fuses 120, 121 may facilitate continuity testing of the conductive vias 110, 112 when only one side of the semiconductor device 100 is accessible at a time, when no operational devices are coupled to the semiconductor device 100, or both. The fuses 120, 121, when intact, may connect the conductive vias 110, 112 respectively to the conductive elements 111, 113. When only the bottom side 108 of the semiconductor device 100 is accessible for testing, the fuses 120, 121, when intact, can be used to provide a conductive path (e.g., the second conductive path 140) to test continuity of lower portions of the conductive vias 110, 112. When the semiconductor device 100 is inverted and only the top side 106 of the semiconductor device 100 is accessible for testing, the fuses 120, 121, when intact, may be used to provide a conductive path (e.g., the third conductive path 141) to test continuity of upper portions of the conductive vias 110, 112. Thus, end-to-end continuity of the conductive vias 110, 112 may be tested in a stepwise manner as the top side 106 and the bottom side 108 become available at different times during the manufacturing process.
While the embodiment shown in
Referring to
To illustrate, continuity testing may be performed from the ground contact 232 to the first conductive via 202, from the ground contact 232 to the second conductive via 212, and from the ground contact 232 to the third conductive via 222. Alternatively, continuity testing may be performed between two or more of the conductive vias 202, 212, 222, such as to test continuity of a conductive path that extends from a first test probe in contact with the first conductive via 202, through the first fuse 204, through the conductive element 230, through the third fuse 224, and through the third conductive via 222 to a second test probe. Continuity may be tested by applying an electrical current, a voltage, or heat at one test probe and monitoring a resulting condition (e.g., current, voltage, or temperature change) at another test probe. The fuses 204, 214, and 224 may be disabled after the testing and prior to normal device operation.
Testing the continuity of the vias 202, 212, 222 as described above may be accomplished from a top side of the device 200. Alternatively or in addition, testing the continuity of the vias 202, 212, 222 may be accomplished from a bottom side of the device 200. Alternatively, end-to-end continuity of the conductive vias 202, 212, 222 may be tested in a stepwise manner as the top side and the bottom side of the device 200 become available at different times during the manufacturing process.
Referring to
Testing continuity of the portion of the conductive via may include, at 304, coupling an electric current source, a voltage source, or a heat source to the conductive via or the conductive element. For example, the electric current source, the voltage source, or the heat source may be coupled to the conductive vias 110, 112 of
The method 300 may include, at 310, disabling the fuse after testing the continuity. For example, referring to
The method 300 of
Referring to
The foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g. RTL, GDSII, GERBER, etc.) stored on computer-readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor die and packaged into a semiconductor chip. The chips are then employed in devices described above.
In a particular embodiment, the library file 512 includes at least one data file including the transformed design information. For example, the library file 512 may include a library of semiconductor devices including a device that includes a TSV continuity testing fuse structure (e.g., the conductive vias 110, 112 of
The library file 512 may be used in conjunction with the EDA tool 520 at a design computer 514 including a processor 516, such as one or more processing cores, coupled to a memory 518. The EDA tool 520 may be stored as processor executable instructions at the memory 518 to enable a user of the design computer 514 to design a circuit including a TSV continuity testing fuse structure (e.g., the conductive vias 110, 112 of
The design computer 514 may be configured to transform the design information, including the circuit design information 522, to comply with a file format. To illustrate, the file formation may include a database binary file format representing planar geometric shapes, text labels, and other information about a circuit layout in a hierarchical format, such as a Graphic Data System (GDSII) file format. The design computer 514 may be configured to generate a data file including the transformed design information, such as a GDSII file 526 that includes information describing a TSV continuity testing fuse structure (e.g., the conductive vias 110, 112 of
The GDSII file 526 may be received at a fabrication process 528 to manufacture a TSV continuity testing fuse structure (e.g., the conductive vias 110, 112 of
The wafers 534 may be tested by a testing computer 570. The testing computer 570 includes a processor 571 and a memory 572. The memory 572 may include instructions, executable by the processor 571, to initiate performance of the operations of the method 300 of
The die 536 may be provided to a packaging process 538 where the die 536 is incorporated into a representative package 540. For example, the package 540 may include the single die 536 or multiple dies, such as a system-in-package (SiP) arrangement. The package 540 may be configured to conform to one or more standards or specifications, such as Joint Electron Device Engineering Council (JEDEC) standards.
Information regarding the package 540 may be distributed to various product designers, such as via a component library stored at a computer 546. The computer 546 may include a processor 548, such as one or more processing cores, coupled to a memory 550. A printed circuit board (PCB) tool may be stored as processor executable instructions at the memory 550 to process PCB design information 542 received from a user of the computer 546 via a user interface 544. The PCB design information 542 may include physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device corresponding to the package 540 including a TSV continuity testing fuse structure (e.g., the conductive vias 110, 112 of
The computer 546 may be configured to transform the PCB design information 542 to generate a data file, such as a GERBER file 552 with data that includes physical positioning information of a packaged semiconductor device on a circuit board, as well as layout of electrical connections such as traces and vias, where the packaged semiconductor device corresponds to the package 540 including a TSV continuity testing fuse structure (e.g., the conductive vias 110, 112 of
The GERBER file 552 may be received at a board assembly process 554 and used to create PCBs, such as a representative PCB 556, manufactured in accordance with the design information stored within the GERBER file 552. For example, the GERBER file 552 may be uploaded to one or more machines to perform various steps of a PCB production process. The PCB 556 may be populated with electronic components including the package 540 to form a representative printed circuit assembly (PCA) 558.
The PCA 558 may be received at a product manufacture process 560 and integrated into one or more electronic devices, such as a first representative electronic device 562 and a second representative electronic device 564. As an illustrative, non-limiting example, the first representative electronic device 562, the second representative electronic device 564, or both, may be selected from the group of a set-top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which a TSV continuity testing fuse structure (e.g., the conductive vias 110, 112 of
A device that includes a TSV continuity testing fuse structure (e.g., the conductive vias 110, 112 of
In conjunction with the described embodiments, an apparatus includes means for establishing a first electrical path through a substrate. For example, the means for establishing a first electrical path may include the conductive vias 110, 112 of
The apparatus may also include means for establishing a second electrical path. For example, the means for establishing a first electrical path may include the conductive elements 111, 113 of
The apparatus may further include means for establishing a permanently severable conductive path between the first electrical path and the second electrical path. For example, the means for establishing a permanently severable conductive path may include the fuses 120, 121 of
Those of skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software executed by a processor, or combinations of both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or processor executable instructions depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of non-transient storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.
The previous description of the disclosed embodiments is provided to enable a person skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope possible consistent with the principles and novel features as defined by the following claims.
