THROUGH VIAS OF SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THEREOF

Abstract

A semiconductor structure includes a semiconductor substrate and an interconnect structure on the semiconductor structure. The interconnect structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a fourth layer over the third layer. A first through via extends through the semiconductor substrate, the first layer, and the second layer. A second through via extends through the third layer and the fourth layer. A bottom surface of the second through via contacts a top surface of the first through via.

Description

Claims

1. A method of forming a semiconductor structure, the method comprising: forming a first portion of an interconnect structure over a substrate, the first portion of the interconnect structure comprising a first metallization layer over the substrate, and a second metallization layer over the first metallization layer;forming a first through via through the first portion of the interconnect structure;forming a second portion of the interconnect structure over the first portion of the interconnect structure, the second portion of the interconnect structure comprising a third metallization layer over the second metallization layer and a fourth metallization layer over the third metallization layer; andforming a second through via through the second portion of the interconnect structure, the second through via contacting the first through via.

2. The method of claim of claim 1, wherein the first through via extends into the substrate, and further comprising: thinning the substrate to expose the first through via; andforming an external contact on the first through via.

3. The method of claim 1, further comprising: forming a redistribution structure over the second portion of the interconnect structure, the redistribution structure comprising a first redistribution layer over the fourth metallization layer and a second redistribution layer over the first redistribution layer; andforming a third through via through the first redistribution layer and the second redistribution layer, the third through via overlying and electrically coupled to the second through via.

4. The method of claim 3, wherein a width of the third through via at an upper surface of the third through via is in a range between 0.2 µm to 3 µm, and wherein a width of the third through via at a lower surface of the third through via is in a range between 0.1 µm to 2.5 µm.

5. The method of claim 3, further comprising: forming a third portion of the interconnect structure over the second portion of the interconnect structure, the third portion of the interconnect structure comprising a fifth metallization layer over the fourth metallization layer and a sixth metallization layer over the fifth metallization layer; andforming a fourth through via through the third portion of the interconnect structure, the fourth through via contacting the second through via, the third through via contacting the fourth through via.

6. The method of claim 3, further comprising forming a first conductive connector on the third through via.

7. The method of claim 6, further comprising forming a second conductive connector on the first through via, wherein the first conductive connector is electrically coupled to the second conductive connector.

8. The method of claim 1, wherein the first through via and the second through via have a width in a range of 0.2 µm to 3 µm.

9. The method of claim 1, wherein a keep-out zone surrounding the first through via, the second through via, and the third through via in a top view is free of other conductive features, the keep-out zone extending to a distance from outer sidewalls of the first through via in a range of 0.2 µm to 5 µm.

10. A method of forming a semiconductor structure, the method comprising: forming a transistor on a substrate;forming a first dielectric layer over the transistor and the substrate;forming a first conductive via extending through the first dielectric layer and into the substrate;forming one or more a first metallization layers over the first dielectric layer;forming a second conductive via extending through the one or more a first metallization layers, the second conductive via being electrically coupled to the first conductive via;forming a redistribution structure over the one or more first metallization layers, the redistribution structure comprising a first redistribution layer and a second redistribution layer; andforming a third conductive via extending through the first redistribution layer and the second redistribution layer, a bottom surface of the third through via contacting a top surface of the second through via.

11. The method of claim 10, further comprising: forming one or more second metallization layers over the one or more first metallization layers; andforming a fourth conductive via extending through the one or more second metallization layers, wherein a bottom surface of the fourth through via contacts a top surface of the first conductive via, wherein a bottom surface of the second conductive via contacts a top surface of the fourth conductive via.

12. The method of claim 10, further comprising thinning the substrate to expose an exposed surface of the first conductive via.

13. The method of claim 12, further comprising forming a first external connector on the exposed surface of the first conductive via.

14. The method of claim 13, further comprising forming a second external connector on the third conductive via.

15. The method of claim 10, wherein the first conductive via, the second conductive via, and the third conductive via have a width in a range of 0.2 µm to 3 µm.

16. The method of claim 10, wherein a keep-out zone surrounding the third conductive via is free of other conductive features, the keep-out zone extending to a distance from outer sidewalls of the third conductive via in a range of 0.2 µm to 5 µm.

17. A semiconductor structure, comprising: a semiconductor substrate, the semiconductor substrate having a first side and a second side opposite the first side;an active device on the first side of the semiconductor substrate;an interconnect structure on the semiconductor substrate, the interconnect structure being over the active device, the interconnect structure comprising a plurality of metallization layers;a first through via extending through at least one metallization layer of the plurality of metallization layers and into the semiconductor substrate; anda second through via in the interconnect structure, the second through via extending through two or more metallization layers of the plurality of metallization layers, a bottom surface of the second through via contacting a top surface of the first through via.

18. The semiconductor structure of claim 17, wherein an upper surface of the first through via has a first width in a range of 0.2 µm to 3 µm.

19. The semiconductor structure of claim 18, wherein a lower surface of the first through via has a second width in a range of 0.1 µm to 2.5 µm.

20. The semiconductor structure of claim 17, wherein a keep-out zone surrounding the third through via is free of other conductive features, the keep-out zone extending to a distance from outer sidewalls of the third through via in a range of 0.2 µm to 5 µm.