Patent Application
20170117027
Field of the Disclosure
Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a spin-orbit torque magnetoresistive random access memory (SOT-MRAM) cell and chip architecture.
Description of the Related Art
The heart of a computer is a magnetic recording device which typically may include a rotating magnetic media or a solid state media device. A number of different memory technologies exist today for storing information for use in a computing system. These different memory technologies may, in general, be split into two major categories: volatile memory and non-volatile memory. Volatile memory may generally refer to types of computer memory that require power to retain stored data. Non-volatile memory, on the other hand, may generally refer to types of computer memory that do not require power in order to retain stored data. Examples of volatile memory may include certain types of random access memory (RAM), such as dynamic RAM (DRAM) and static RAM (SRAM). Examples of non-volatile memory may include read-only memory (ROM), magnetoresistive RAM (MRAM), and flash memory, such as NOR and NAND flash, etc.
In recent years there has been a demand for higher density devices, which maintain a relatively low cost per bit, for use in high capacity storage and memory applications. Today the memory technologies that generally dominate the computing industry are DRAM and NAND flash; however these memory technologies may not be able to address the current and future capacity demands of next generation computing systems.
Recently, a number of emerging technologies have drawn increasing attention as potential contenders for next generation memory. One such memory technology is magnetoresistive random access memory (MRAM). MRAM offers fast access time, nearly infinite read/write endurance, radiation hardness, and high storage density. Unlike conventional RAM chip technologies, MRAM data is not stored as an electric charge, but instead stores data bits using the magnetic polarization state of magnetic elements. The elements are formed from two magnetically polarized layers, each of which can maintain a magnetic polarization field, separated by a thin insulating layer, which together form a magnetic tunnel junction (MTJ) structure. MRAM cells including MTJ memory elements can be designed for in-plane or perpendicular magnetization of the MTJ layer structure with respect to the film surface. One of the two layers (referred to as a fixed or reference layer) has its magnetization fixed and set to a particular polarity, for example by coupling the layer to an antiferromagnet; the polarization of the second layer (referred to as a free layer) is free to rotate under the influence of an external writing mechanism such as a strong magnetic field or a spin polarized electric current (which is used in a form of MRAM know as spin-torque transfer or STT-MRAM).
However, the MTJ memory elements in STT-MRAM devices suffer from wear-effects due to driving a sufficient amount of current for switching through the MTJ, including through the barrier layer. Typically, a large amount of current is required for switching the state of the cell. Over time, the barrier layer breaks down due to the large amount of current, rendering the MTJ useless. Additionally, in STT-MRAM devices, it can be difficult to isolate a single MTJ element without disturbing neighboring MTJ elements, and a large transistor, such as a complementary metal oxide semiconductor (CMOS) transistor, may be necessary in the device in order to select an individual MTJ element.
Therefore, there is a need in the art for an improved MRAM device.
Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM cell and chip architecture. The SOT-MRAM chip architecture includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells. Each memory cell of the plurality of memory cells includes both a MTJ and a selector element. These SOT-MRAM cells eliminate the need to pass large currents through the barrier layer of the MTJ and the selector element eliminates the large transistors usually required for selecting a single memory cell without disturbing neighboring memory cells.
In one embodiment, a memory cell includes a MTJ and a selector element disposed on the MTJ.
In another embodiment, a memory cell array includes a plurality of first leads, a plurality of second leads, and a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads. Each memory cell of the plurality of memory cells includes a MTJ and a selector element disposed on the MTJ.
In another embodiment, a SOT-MRAM includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads. Each memory cell of the plurality of memory cells includes a MTJ and a selector element disposed on the MTJ.
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.
In the following, reference is made to embodiments of the disclosure. However, it should be understood that the disclosure is not limited to specific described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the disclosure. Furthermore, although embodiments of the disclosure may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the disclosure. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the disclosure” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM cell and chip architecture. The SOT-MRAM chip architecture includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells. Each memory cell of the plurality of memory cells includes a MTJ and a selector element. These SOT-MRAM cells eliminate the need to pass large currents through the barrier layer of the MTJ and the selector element eliminates the large transistors usually required for selecting a single memory cell without disturbing neighboring memory cells.
A selector element 312 may be disposed on and in contact with the MTJ 310. The selector element 312 may be a diode or another similar nonlinear device that has asymmetric conductance (i.e., low resistance to current in one direction while high resistance in the other). In one embodiment, the selector 312 is a p-n junction semiconductor diode. As shown in
During operation, writing can be done by a half-select mechanism which includes the combination of flowing a current along the second lead 106 and applying a voltage to the first lead 104, as shown in
In another embodiment, the barrier layer 304 resistance can be made low enough that the current across the MTJ of a particular memory cell 102 is half the current that would cause the memory cell 102 to switch. Here, a combination of SOT and direct spin torque transfer from the current selects the particular memory cell 102 for writing process.
Conventionally, a plurality of transistors, such as CMOS transistors, are electrically coupled to the second lead in order to select a particular memory cell for reading process. Since a current is flowing along the second lead 106, the transistors may be shorted together, resulting in sneak paths to other memory cells and in degraded performance. In order to reduce or eliminate sneak paths, the CMOS transistors are replaced by the selector element 312 in each memory cell 102. During reading operation, the second lead 106 may be grounded or biased, and a voltage is applied to the first lead 104, as shown in
In summary, a SOT-MRAM cell and chip architecture including a memory array is disclosed. The memory array includes a plurality of first leads, a plurality of second leads, and a plurality of memory cells. Each memory cell includes a MTJ and a selector element. The second leads may be made of a material having large spin-orbit coupling strength, which generates SOT when a current is flowing along the second lead. The MTJ may include a free layer disposed on and in contact with the second lead. Since the free layer is disposed at the bottom of the MTJ, the free layer is protected from process damage. The selector element in each memory cell may be utilized in order to eliminate the use of large transistors for selecting memory cells for read process. The selector can also prevent sneak paths which lead to improvements in performance of the SOT-MRAM cell and chip architecture.
While the foregoing is directed to embodiments of the disclosure, other and further embodiments may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
