Patent Application
20240055314
Embodiments of the subject matter described herein relate to field-effect transistors and methods of fabrication of such transistors.
Transistor-based circuits are often used for analog signal processing applications including amplification of radio and microwave-frequency (RFMW) signals and for power-switching. Advanced transistor designs and high-performance materials such as III-V semiconductors have been used to achieve increased power densities while providing acceptable thermal performance and voltage-induced breakdown characteristics. However, highly-scaled devices may be more susceptible to leakage, breakdown, and other problems. Transistors based on Gallium Nitride (GaN) and/or other compound semiconductors are often used in applications where highly-scaled silicon transistors cannot provide adequate switching speeds or power handling capabilities.
In an example embodiment, a transistor device includes a portion of an electrically-insulating semiconductor substrate having a top surface and a bottom surface; a first current terminal; a second current terminal; a channel region formed above the top surface of the semiconductor substrate that is configured to provide an electrically conductive path between the first current terminal and the second current terminal; an elongated gate electrode disposed above the channel region that extends laterally from a first end of the gate electrode to a second end of the gate electrode in a first direction that is parallel to the top surface of the semiconductor substrate; and a first elongated cooling trench coupled to the first current terminal that extends laterally from a first end to a second end of the first elongated cooling trench along the first direction and extends vertically from the first current terminal and through the top surface into the semiconductor substrate. The first elongated cooling trench is filled throughout with a thermally-conductive material configured to dissipate heat from the channel region into the semiconductor substrate.
In another example embodiment, a method of fabricating a transistor includes
The present disclosure is illustrated by way of examples, embodiments, and the like and is not limited by the accompanying figures, in which like reference numbers indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. The figures along with the detailed description are incorporated and form part of the specification and serve to further illustrate examples, embodiments and the like, and explain various principles and advantages, in accordance with the present disclosure, wherein:
The following detailed description provides examples for the purposes of understanding and is not intended to limit the invention or the application and uses of the same. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in the figures may be exaggerated relative to other elements or regions to help improve understanding of embodiments of the invention.
The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. As used herein the terms “substantial” and “substantially” mean sufficient to accomplish the stated purpose in a practical manner and that minor imperfections, if any, are not significant for the stated purpose.
Directional references such as “top,” “bottom,” “left,” “right,” “above,” “below,” and so forth, unless otherwise stated, are not intended to require any preferred orientation, and are made with reference to the orientation of the corresponding figure or figures for purposes of illustration.
It will be appreciated that the steps of various processes described herein are non-limiting examples of suitable processes according to embodiments and are for the purposes of illustration. Systems and devices according to embodiments herein may use any suitable processes including those that omit steps described herein, perform those steps and similar steps in different orders, and the like. It will also be appreciated that well-known steps or other well-known process features may be omitted for clarity.
The gate electrode 140 contacts the channel region 110 through an aperture in the dielectric material 115. As shown, the gate electrode 140 may have a first portion 142 that contacts the channel region 110 within the aperture and optionally may have a second portion 143 that overhangs the dielectric material 115. Although the gate electrode 140 is depicted as having vertical sidewalls, it will be understood that the gate electrode 140 and similar structures herein may have any suitable geometry. For instance, the first portion 142 of the gate electrode 140 may have sidewalls that are curved or slanted. Similarly, the second portion 143 of the gate electrode 140 may have sidewalls that are curved or slanted and the top of the gate electrode 140 (farthest from the channel region 110) may have any suitable geometry.
It will be appreciated that the first current terminal 120 may be operated, for example, as a source terminal of the transistor 100 and the second current terminal 130 may be operated, for example, as a drain terminal of the transistor 100. It also be understood that the gate electrode 140 is suitable for use as a gate electrode of the transistor 100 such that, when a suitable bias voltage is applied to the gate electrode 140, the channel region 110 is configured to provide an electrically conductive path between the first current terminal 120 and the second current terminal 130. The backside of the substrate 102 can be electrically conductive and, as shown, may include a backside metallization layer 190 which can be bonded to a heat sink. In some applications the backside of the substrate 102 may also be connected to the source or drain terminal of transistors using through-wafer vias.
The transistor 100 above (and transistors according to embodiments herein) may represent transistors implemented using various transistor technologies. For instance, example transistors described according to embodiments herein may be metal-MOSFETs or MISFETs fabricated on a silicon substrate or any other suitable semiconductor substrate. For instance, the transistor 100 may be a III-V compound semiconductor-based high electron-mobility transistor (“HEMT”), otherwise known as a heterostructure field effect transistor (“HFET”). In such transistors the effective semiconductor channel may be a 2D electron gas (“2DEG”) formed at a semiconductor heterojunction disposed with the channel region 110 according to known techniques. Along these lines, the transistor 100 may be a gallium-nitride (GaN) based HEMT. In some such embodiments, a 2DEG is formed at an interface between a GaN layer and an aluminum doped layer with a stochiometric composition described by the chemical formula AlxGa1-xN. In such embodiments it will be understood that the effective channel may be buried within the channel region 110 and may not extend to the top surface 112 of the substrate above the channel region 110. In some embodiments, the dielectric material 115 may be a material that provides surface passivation for the channel region 110. For instance, the dielectric material 115 may be a silicon nitride passivation layer over a GaN-based heterostructure. It will be further understood that, in embodiments herein where a channel region such as the channel region 110 is formed by a semiconductor heterostructure (as illustrated in
It will be understood that the example transistor 100 as shown in
HEMTs and similar transistors with structures similar to the transistor 100 with a channel similar to the channel region 110 as depicted in
In some transistors the source or drain may be coupled to a conductive layer such as the backside metallization layer 190 shown in
Accordingly,
Analogously to the transistor 100, the transistor 200 is formed on a substrate 202 (e.g., a semiconductor substrate 102) with a channel region 210 (e.g., a channel region 110) having a top surface 212, a source terminal 220 (e.g., a first current terminal 120) with a contact 225 (e.g., a contact 125) and a drain terminal 230 (e.g., a second current terminal 130) with a contact 235 (e.g., a contact 135), as well as a gate electrode 240 (e.g., a gate electrode 140) and a dielectric material 215 (e.g., a dielectric material 115) over the channel region 210. As shown, the gate electrode 240 has a first portion 242 in direct contact with the top surface 212 of the channel region 210 and a second portion 243 that is wider than first portion 242 and contacts the dielectric material 215. However, it will be understood that, in one or more embodiments, the gate electrode 240 has different shapes. It will be further understood that, in one or more embodiments (e.g., embodiments in which the example transistor 200 is a HEMT with an insulating barrier layer (e.g., a barrier layer 110c) underneath the gate electrode 240, the dielectric material 215 is absent.
As shown in
In one or more alternate embodiments, the cooling trenches 250 are thermally, but not electrically coupled to the source and drain terminals. In one or more such embodiments, when the transistor is in an cony state, less than 10% of the current flowing from source to drain passes through the cooling trenches 250. In one or more such embodiments, when the transistor is in an cony state, less than 5% of the current flowing from source to drain passes through the cooling trenches 250. In one or more such embodiments, when the transistor is in an cony state, less than 1% of the current flowing from source to drain passes through the cooling trenches 250.
In one or more embodiments, at least one cooling trench 250 is lined with an electrically insulating material to electrically isolate them from the current terminals (the source terminal 220 and the drain terminal 230), and/or the channel region. In one or more embodiments the interface between at least one cooling trench 250 and the surrounding semiconductor material is characterized by a high Schottky barrier such that no Ohmic contact is formed between the material of the trench and the semiconductor material. In one or more embodiments, at least one cooling trench 250 contains multiple metal layers in contact which each other. For example, a thin layer of a first metal with a relatively high work function (e.g., platinum) may be used near the top surface 212, and a second metal with a lower work function and high thermal conductivity (e.g., gold) may be used beneath the first layer.
It will be appreciated that the cooling trenches 250 are not shown to scale in
Furthermore, it will be understood that arrangements of cooling trenches 250 other than those depicted may be used in or more embodiments. For example, a series of cooling trenches 250 may be used on either side of the gate electrode 240 and these trenches may be arranged along a single line or arranged in a staggered fashion. Similarly, in one or more embodiments cooling trenches 250 are present on both sides of the gate electrode 240 and the cooling trenches 250 on each side of the gate electrode 240 are arranged symmetrically or asymmetrically with respect to the gate electrode 240.
In one or more embodiments, at least one cooling trench 250 has an aspect ratio (i.e., a ratio of the length along the direction indicated by the arrow 292 to the width along the direction indicated by the arrow 291) much greater than one (e.g., 5, 10, 20, or larger). In one or more embodiments, at least one cooling trench 250 is as long as an adjacent gate electrode 240 or longer. In one or more embodiments, multiple cooling trenches 250 are present adjacent to a gate 240 (i.e., multiple cooling trenches 250 are disposed along the direction 292 with gaps in between them where no cooling trench is present). In one or more such embodiments, one or more cooling trenches have a dimension along the direction 292 of at least 1 μm. In one or more such embodiments, one or more cooling trenches have a dimension along the direction 292 of at least 2 μm. In one or more such embodiments, one or more cooling trenches have a dimension along the direction 292 of at least 5 μm. In one or more such embodiments, one or more cooling trenches have a dimension along the direction 292 of at least 10 μm. In one or more such embodiments, one or more cooling trenches have a dimension along the direction 292 of at least 20 μm. It will be appreciated that, in the transistor 200, as pictured in
It will be understood that transistors according to embodiments herein are not limited to only the features shown and may have additional features, including additional dielectric layers and electrical interconnects. In addition, in or more or more embodiments, a transistor includes one or more field plate electrodes including, but not limited to a gate-connected field plate, a source-connected field plate, or the like.
As shown, the example process 300 includes steps 310, 320, 330, 340, 350, 360, 370, and 380. These steps are depicted in
At step 310, a semiconductor substrate (e.g., the substrate 202) is provided with a region suitable for use as a channel region at the top surface (e.g., a semiconductor heterostructure such as a channel region 110 or channel region 210). The dielectric material 215 is also present above the channel region 210. A masking material 312 (e.g., photoresist, dielectric material, or a conductive material) is patterned above the dielectric material 215 and the channel region 210, using any suitable process including well-known semiconductor lithography techniques as nonlimiting examples.
At step 320, an open cavity 321 is etched through the dielectric material 215, the channel region 210, and through a portion of the substrate 202 as shown using any suitably anisotropic etching process, including one or more dry plasma etching processes and/or one or more wet chemical etching processes that can be chosen based in part on the composition and microstructure of the dielectric material 215, the channel region 210, and the substrate 202.
At step 330, the masking material 312 is stripped away and a suitably conductive material 334 is deposited above the entire device area of the substrate 202, filling the cavity 321 formed at step 320, as shown. The conductive material 334 is thermally conductive and in one or more embodiments, the conductive material 334 is electrically conductive, highly resistive, semiconductive, or electrically nonconductive. In or more embodiments, as shown (e.g., in a HEMT such as the transistor 200 with a heterostructure-based channel region 210, the conductive material 334 is both thermally and electrically conductive and configured such that current applied to the contact 225 (see
At step 340, the conductive material 334 has been selectively removed from above the dielectric material 215, leaving only the cooling trench 250 filled with the conductive material 334 as shown. The conductive material 334 can be removed using any suitable processes including, as nonlimiting examples, sputter etching, reactive ion etching, wet chemical etching, chemical mechanical polishing (CMP), and the like; and any suitable combination of two or more such processes.
At step 350, a masking material 352 (e.g., photoresist) is formed and patterned above the substrate 202. The dielectric material 215 is removed from areas that are not protected by the masking material 352 and then an electrically conductive material 354 is deposited over the entire device area, as shown. A portion of the conductive material 354 that is deposited over the cooling trench 250 forms the contact 225. As shown, the masking material 352 may have angled sidewalls to facilitate patterning the conductive material 354 using a lift-off process. The residual masking material 352 is stripped, removing any of the undesired conductive material 354, leaving the conductive material 354 behind in the cooling trench 250.
At step 360, a masking material 362 (e.g., photoresist) is patterned above the substrate 202 to leave an opening 363 through which the dielectric material 215 is removed using any suitable process, including as nonlimiting examples a sputter etching process, a reactive ion etching process, and a wet chemical etching process. In some embodiments, a wet chemical etching process is used to avoid damage to the underlying channel region 210.
At step 370, a masking material 372 (e.g., photoresist) is formed and patterned above the substrate 202 and an electrically conductive material 374 is deposited over the masking material 372. As shown, the masking material 372 may have angled sidewalls to facilitate patterning the conductive material 374 using a lift-off process. The residual masking material 372 is stripped, removing any of the undesired conductive material 374, leaving the electrically conductive material 374 behind to form the gate electrode 240.
Finally, at step 380, In one or more embodiments in which a gate electrode lacks the T-shaped profile of the gate electrode 240, the gate electrode can be formed by depositing conductive material such as the conductive material 374 over the masking material 362 at step 370 and step 380 is omitted.
It will be understood, that, in one or more embodiments, the positioning of a cooling trench may vary from the positioning of the cooling trench 250 in
It will be understood that, although the patterning of various layers (e.g., the conductive material 334, the electrically conductive material 354, and the electrically conductive material 374) may be described according to an additive process such as lift-off, that any suitable processes may be used, including, but not limited to processes in which a conductive material is first deposited over an entire area and then patterned substantively through a masking material using an etch process or any other suitable process.
As indicated above, modifying a transistor such as the example transistor 100 to include one or more cooling trenches according to embodiments herein can be used to reduce current induced heating in gallium nitride HEMTs and related device. For instance, combined electrical and thermal simulations have shown that the peak temperature in the channel region of a particular gallium nitride HEMT design can be reduced from approximately 260° C. to less than 200° C. when a tungsten-filled cooling trench (e.g., a cooling trench 250) is added beneath the source terminal (e.g., the source terminal 220. Such improvements in thermal characteristics can enable increased density in multi-transistor integrated circuits, improved device reliability, and other benefits. For example, in a simulated gallium nitride HEMT with a single source side cooling trench, breakdown voltage increased by up to ˜35% with increasing depth of the cooling trench from 0 (no trench) to 5 μm and gate leakage current was reduced at the expense of a moderate increase in drain-to-source capacitance (less than ˜10%). Addition of a drain-side cooling trench can produce additional heat transfer improvements but may also tend to counter-act some of the performance benefits seen in the device with a source-side cooling trench only. However, performance tradeoffs can be optimized by using a comparatively deep cooling trench on the source side and a shallower cooling trench on the drain side.
In examples herein, the thermal performance of cooling trenches with a depth of 500 nm were simulated. In general, for HEMT devices with cooling trenches according to embodiment it is desirable for a cooling trench to extend at least far enough into a substrate to contact a nucleation layer of a heterostructure such as the nucleation layer 110a of the heterostructure 110.
Features of embodiments may be understood by way of one or more of the following examples:
The first elongated cooling trench is coupled to the first current terminal and extends laterally from a first end to a second end of the first elongated cooling trench along the first direction and extends vertically from the first current terminal and through the top surface into the semiconductor substrate. The first elongated cooling trench is filled throughout with a thermally-conductive material configured to dissipate heat from the channel region into the semiconductor substrate.
The preceding detailed description and examples are merely illustrative in nature and are not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.
It should be understood that this invention is not limited in its application to the details of construction and the arrangement of components set forth in the preceding description or illustrated in the accompanying drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Unless specified or limited otherwise, the terms “mounted,” “connected,” “supported,” and “coupled” and variations thereof are used broadly and encompass both direct and indirect mountings, connections, supports, and couplings. Further, “connected” and “coupled” are not restricted to physical or mechanical connections or couplings.
The preceding discussion is presented to enable a person skilled in the art to make and use embodiments of the invention. Various modifications to the illustrated embodiments will be readily apparent to those skilled in the art, and the generic principles herein can be applied to other embodiments and applications without departing from embodiments of the invention. Thus, embodiments of the invention are not intended to be limited to embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein. The preceding detailed description is to be read with reference to the figures, in which like elements in different figures have like reference numerals. The Figures, which are not necessarily to scale, depict selected embodiments and are not intended to limit the scope of embodiments of the invention. Skilled artisans will recognize the examples provided herein have many useful alternatives and fall within the scope of embodiments of the invention.
The connecting lines shown in the various figures contained herein are intended to represent example functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in one or more embodiments of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms “first,” “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.
The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one example arrangement of elements, additional intervening elements, devices, features, or components may be present in one or more embodiments of the depicted subject matter.
