Patent Application
20160104782
1. Field of the Invention
The present disclosure relates to a transistor structure and a method of manufacturing the same; in particular, to a transistor structure whose bit line junction includes a uniform region having a substantially uniform dopant concentration, and a method of manufacturing the same.
2. Description of Related Art
Conventional dynamic random access memories (DRAM) use a capacitor to store each bit of information. The capacitor can be charged or discharged to represent either of the two values of a bit, nominally 0 or 1. A bit line is electrically connected to the capacitor through a field effect transistor to read and write data stored in the capacitor. The field effect transistor controls access of the bit line to the capacitor by allowing or disallowing current to flow through a channel therebetween. Specifically, the bit line is connected to a source region of the transistor, the capacitor is in connection with a drain region of the transistor, and a gate is positioned between the source and the drain regions. A word line is connected to the gate to control the voltage thereat, thereby controlling electrical connection between the bit line and the capacitor by allowing or disallowing flow of current through the channel between the source and the drain regions.
In order to achieve higher unit density, the abovementioned electronic units are positioned more compactly. This creates problems of interference between neighboring units. For example, a signal sent through a word line to one gate may affect the voltage at a neighboring gate. This problem is aggravated if the region between neighboring gates has inadequate dopant concentration.
Conventionally, the source and the drain regions are implanted once with dopant of high dosage, and then the boundary between the drain region and the channel controlled by the gate is implanted with dopant of low dosage to reduce the effect of hot carrier and leakage thereat (i.e. to form lightly doped drains). The high dosage implant at the source region is necessary for achieving electrical connection between the bit line and the channel controlled by the gate. However, if the source region is arranged between two closely placed gates, then problems of word line coupling may arise if the dopant concentration at the source region is too high; and problems of word line disturb, in addition to problems of insufficient electrical conductivity between the bit line and the channel, may arise if the dopant concentration at the source region is too low. Therefore, a preferred dopant concentration is desired throughout the entire source region. However, a single implant of high dosage results in an uneven distribution of dopant concentration within the source region, resulting in preferred concentrations at some portions but overly high or overly low concentrations at others. Thus, a method of producing within the source region a uniform region having a substantially uniform dopant concentration, while producing a relatively lightly doped drain region for reducing leakages, is desired.
The object of the present disclosure is to provide: a transistor structure comprising two gates, a bit line junction (including a source region) therebetween which has a region of substantially uniform dopant concentration so as to reduce word line disturb and word line coupling between the two gates, and two cell side junctions (including drain regions) having a lower dopant concentration than that of the bit line junction so as to reduce gate induced drain leakage; and a method of manufacturing said transistor structure.
In order to achieve the aforementioned objects, a transistor structure of the present disclosure is formed on a substrate and comprises: a bit line junction, two cell side junctions, and two trenches each having a dielectric layer and a gate disposed therein. The bit line junction includes a uniform region formed by implanting dopant of light dosage into the substrate at least two times. The two cell side junctions are arranged respectively on two sides of the bit line junction and each include a drain region formed by implanting dopant of light dosage into the substrate one time. Each of the two trenches is formed on the substrate and arranged between the bit line junction and the respective cell side junction, and has a dielectric layer disposed therein. A gate is disposed on the respective dielectric layer of each of the trenches. Specifically, the uniform region of the bit line junction has a substantially uniform dopant concentration which is higher than the dopant concentration of the portion of the bit line junction thereunder and higher than the dopant concentration of the drain regions. The depth of the uniform region ranges from above the top of each of the gates to below the top of each of the gates
The transistor structure is preferably configured to be in connection with a bit line, two word lines and two capacitors. The bit line is connected to the bit line junction. The two word lines are respectively connected to the two gates. The two capacitors are respectively arranged adjacent to the two cell side junctions.
In order to achieve the aforementioned objects, a method of manufacturing a transistor structure according to the present disclosure comprises: forming two trenches on a substrate, wherein a bit line junction is defined between the two trenches, and two cell side junctions are defined respectively at the sides of the trenches opposite the bit line junction; disposing a dielectric layer in each of the two trenches; disposing conductive material on each of the dielectric layers to form a gate in each of the two trenches; implanting dopant of light dosage into the substrate at the bit line junction and the two cell side junctions; and then implanting dopant of light dosage into the bit line junction an additional time, forming within the bit line junction a uniform region having a substantially uniform dopant concentration, wherein the depth of the uniform region ranges from above the top of each of the gates to below the top of each of the gates.
Thereafter, the following steps are preferably included: connecting a bit line to the bit line junction, connecting two word lines respectively to the two gates, and forming two capacitors respectively adjacent to the two cell side junctions.
In order to further the understanding regarding the present disclosure, the following embodiments are provided along with illustrations to facilitate the teaching of the present disclosure.
The aforementioned illustrations and following detailed descriptions are exemplary for the purpose of further explaining the scope of the present disclosure. Other objectives and advantages related to the present disclosure will be illustrated in the subsequent descriptions and appended drawings.
Referring to
Then in step S7, the bit line junction 3 and the cell side junctions 4 are implanted with dopant of light dosage. For this particular embodiment, the implanted dosage is phosphorus at 1.9e13 dopant atoms/cm3, and the implant energy is 25 KeV; but the present disclosure is not limited thereto.
Then in step S9, the bit line junction 3 is implanted an additional time. For this particular embodiment, the implanted dosage is phosphorus at 5e12 to 5e13 dopant atoms/cm3, and the implant energy is 35 KeV; but the present disclosure is not limited thereto.
Referring to
The cell side junctions 4 are each implanted once only, forming thereat a drain region 41 having a relatively low dopant concentration for reducing gate induced drain leakages.
The different energies of the two implants at the bit line junction 3 results in different implant depths thereof, as shown by the curve of the first implant C1 and the curve of the second implant C2. Of particular note, the curve of the first implant C1 and the curve of the second implant C2 are relatively narrow, and the curve of the sum of both implants C3 is relatively wide. Specifically, from depth X to depth Y, the slope of the curve of the first implant C1 is negative, the slope of the curve of the second implant C2 is positive, and at any depth between X and Y the magnitude of the slope of the curve of the first implant C1 is smaller than the magnitude of the slope of the curve of the second implant C2. Therefore, at any depth between X and Y, the slope of the curve of the sum of both implants C3 is positive but smaller in magnitude than the slope of the curve of the second implant C2. Similarly, at any depth between Y and Z, the slope of the curve of the sum of both implants C3 is negative but smaller in magnitude than the slope of the curve of the first implant C1. In other words, by implanting dopants at differing depths, a dopant concentration curve having slopes of relatively small magnitude across a wider range of depth is obtained. Namely, a region of substantially uniform dopant concentration is formed, as shown by a uniform region 32 in
Specifically, the depth of the uniform region 32 ranges from above the top of each of the gates 22 to below the top of each of the gates 22. The uniform region 32 serves as a source region which has a substantially uniform dopant concentration, such that neither overly high nor overly low dopant concentration exist at any depth thereof, thereby reducing both word line coupling and word line disturb between the two gates 22. Preferably, the width of the uniform region 32 ranges from a boundary between the bit line junction 3 and one of the trenches 2 to a boundary between the bit line junction 3 and another one of the trenches 2.
The region of the bit line junction 3 under the uniform region 32 is part of a channel controlled by the respective gate 22 for allowing or disallowing current to flow between the uniform region 32 and the respective cell side junction 4. Consequently, the region of the bit line junction 3 under the uniform region 32 is more lightly doped than the uniform region 32 is.
Referring to
Additionally, a bit line BL, word lines WL, and capacitors CU may be connected to the bit line junction 3, the gates 22, and the cell side junctions 4, respectively. However, the present disclosure is not limited thereto.
Referring to
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Referring to
The descriptions illustrated supra set forth simply the preferred embodiments of the present disclosure; however, the characteristics of the present disclosure are by no means restricted thereto. All changes, alterations, or modifications conveniently considered by those skilled in the art are deemed to be encompassed within the scope of the present disclosure delineated by the following claims.
