Patent Application
20180226292
The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures with trench isolation and methods for making a structure with trench isolation.
Complementary-metal-oxide-semiconductor (CMOS) processes may be used to build a combination of p-type field-effect transistors (pFETs) and n-type field-effect transistors (nFETs) that are coupled to implement logic gates and other types of integrated circuits, such as switches. Field-effect transistors generally include a device body, a source, a drain, and a gate electrode associated with a channel that is formed in the device body. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in an inversion or depletion layer as the channel in the device body between the source and drain to produce a device output current.
Bipolar junction transistors are three-terminal electronic devices that include an emitter, a collector, and an intrinsic base arranged between the emitter and collector. A heterojunction bipolar transistor is a type of bipolar junction transistor in which two or more of the emitter, intrinsic base, and/or collector are composed of semiconductor materials with unequal band gaps, which creates heterojunctions instead of homojunctions. For example, the collector and/or emitter of a heterojunction bipolar transistor may be composed of silicon, and the base of a heterojunction bipolar transistor may be composed of a narrower band gap material, such as silicon silicon-germanium. In operation, the base-emitter junction is forward biased and the base-collector junction is reverse biased. The collector-emitter current may be controlled by the base-emitter voltage.
Active regions for building transistors may be defined using trench isolation. The trench isolation process generally includes etching a pattern of trenches in the semiconductor substrate, filling the trenches with one or more dielectric layers, and removing the excess dielectric material using chemical-mechanical planarization. The resultant isolation structures formed in the trenches provide electrical isolation between different active regions in which devices, such as field-effect transistors or bipolar junction transistors, are formed.
Improved structures with trench isolation and methods for making a structure with trench isolation are needed.
In an embodiment of the invention, a method includes forming, by front-end-of-line processing, a transistor on a first surface of a semiconductor substrate. The method further includes forming a barrier layer on the transistor and the first surface of the semiconductor substrate. After the transistor and the barrier layer are formed, a trench is etched from a second surface of the semiconductor substrate that is opposite from the first surface of the semiconductor substrate. The trench, which is used to form an isolation region, may terminate on a dielectric layer associated with the transistor or may terminate on the barrier layer.
In an embodiment of the invention, a structure includes a semiconductor substrate having a first surface and a second surface that is opposite from the first surface of the substrate, and a transistor on the first surface of a semiconductor substrate. The transistor includes a dielectric layer. A barrier layer is located on the transistor and the first surface of the semiconductor substrate. An isolation region includes a trench extending from the second surface of the semiconductor substrate through the semiconductor substrate to terminate on the dielectric layer of the transistor or on the barrier layer
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
With reference to
Device structures 20, 22, 24 are formed at and on a front side surface 13 of the device layer 12 of the semiconductor substrate 10 by FEOL processing. The device structure 20 may be a passive device, which may have the representative form of a resistor. The device structure 22 may be a field-effect transistor that includes a gate electrode 21 and a gate dielectric layer 23 comprised of an electrical insulator, such as silicon dioxide (SiO2), deposited by chemical vapor deposition (CVD). The device structure 22 may include additional features that are characteristic of a field-effect transistor. The device structure 24 may be a bipolar junction transistor or a heterojunction bipolar transistor that includes a base dielectric layer 25 comprised of a dielectric material, such as silicon dioxide (SiO2), deposited by CVD. The base dielectric layer 25 may function as a protect layer to cover the device structure 22 during the fabrication of device structure 24. The device structure 24 may include an emitter 27, a base 29, and a collector 33 in the device layer 12 with a structural arrangement that is characteristic of a bipolar junction transistor or a heterojunction bipolar transistor. The device structure 24 may include additional features that are characteristic of a bipolar junction transistor or a heterojunction bipolar transistor.
A barrier layer 26 may be deposited that follows the contours of the surfaces of the device structures 20, 22, 24. The barrier layer 26 may be composed of a dielectric material, such as silicon nitride (Si3N4), deposited by CVD. An interlayer dielectric layer 31, such as an electrical insulator like silicon dioxide (SiO2), may be deposited by CVD and planarized using chemical mechanical polishing (CMP). Contacts 28 may be formed in the interlayer dielectric layer 31 by middle-of-line (MOL) processing to provide a local interconnect structure. The contacts 28, which may be comprised of tungsten (W), penetrate through the barrier layer 26 for connection with portions of the device structures 20, 22, 24.
With reference to
A resist layer 34 is formed on the dielectric layer 32 and patterned. Specifically, the resist layer 34 may be composed of an organic photoresist that is applied by spin-coating, pre-baked, exposed to a pattern of radiation from an exposure source projected through a photomask, baked after exposure, and developed with a chemical developer to form openings situated at the intended locations at which trenches are to be formed, as described hereinafter.
With reference to
The etching process removing the device layer 12 is selected to remove the device layer 12 selective to dielectric materials and, in particular to the gate dielectric layer 23, the base dielectric layer 25 and the barrier layer 26, each of which may operate as an etch stop for the process forming the trenches 38. As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process. A discrete etch stop layer is not required in the structure to form the trenches 38, which penetrate through the device layer 12 but not into the interlayer dielectric layer 31 or into device structures 20, 22, 24.
With reference to
In an alternative embodiment, the dielectric material constituting the dielectric layer 42 may be selected to include internal stress that can be transferred to one or more of the device structures 20, 22, 24. For example, the dielectric material may be constituted by silicon nitride (Si3N4) deposited by plasma-enhanced chemical vapor deposition (PECVD), either with or without a passivation layer of, for example, silicon dioxide (SiO2) initially formed on the surfaces surrounding the trenches 38. The deposition conditions (e.g., gas flow rates, chamber pressure, RF power exciting the plasma, etc.) can be selected to form silicon nitride under a state of either compressive stress or tensile stress.
With reference to
In accordance with the embodiments of the invention, the trench isolation regions 41 are formed from the back side surface 15 in association with a layer transfer process and after the device structures 20, 22, 24 are formed at the front side in an isolation last process. This eliminates the need to form trench isolation regions in a conventional manner before the device structures 20, 22, 24 are formed by front-end-of-line processing and from the front side surface 13 of the semiconductor substrate 10. The trench isolation regions 41 are also formed without the need for a placeholder dielectric layer to operate as an etch stop when the trenches 38 are etched from the back side.
For the device structure 22 that is a field-effect transistor or a switch field-effect transistor with electrode fingers, the layer transfer-based process substantially lowers the cost associated with the formation of conventional trench isolation, eliminates slip-inducing anneals associated with the formation of conventional trench isolation, and eliminate corners at the trench isolation/gate electrode interface. The results may be enhancements in reliability, harmonic distortion, and switch breakdown voltage. In embodiments, the trench isolation regions 41 may incorporate a tunable amount of final stress absent high temperature anneals.
For the device structure 24 that has the construction of a bipolar junction transistor or heterojunction bipolar transistor, the layer transfer-based process eliminates device region to trench isolation edge facets in the base layer, which may reduce the collector-base capacitance (Ccb). The reduction in Ccb improves the performance of the device structure 22 by improving figures of merit, such as cut-off frequency (fT) and maximum oscillation frequency (fmax).
With reference to
Trench 38 and trenches 48, 50 are formed that extend through the dielectric layer 32, the BOX layer 14, and the device layer 12 at the location of the openings in the resist layer 34. To that end, the patterned resist layer 34 is used as an etch mask for a dry etching process, such as a reactive-ion etching (RIE), that removes unmasked portions of the dielectric layer 32, the BOX layer 14, and the device layer 12 to form the trench 38 and the trenches 48, 50. The etching process may be conducted in a single etching step with a given etch chemistry or in multiple etching steps with different etch chemistries.
Dimensionally, the trenches 48 have a larger height-to-width ratio than the height-to-width ratio of the trenches 38. The trench 50 has a height-to-width ratio that is between the height-to-width ratio of the trenches 48 and the height-to-width ratio of the trench 38. The resist layer 34 is stripped after the trenches 38, 48, 50 are formed.
With reference to
Because of their larger height-to-width ratio, the trenches 48 are not filled by the solid dielectric material of the dielectric layer 42, but are instead pinched off to close the trenches 48 at or near their respective entrances. The closed trenches 48 define air gaps that may be characterized by an effective permittivity or dielectric constant of near unity (vacuum permittivity). The closed trenches 48 may be filled by air at or near atmospheric pressure, may be filled by another gas at or near atmospheric pressure, or may contain air or another gas at a sub-atmospheric pressure (e.g., a partial vacuum). The air gaps defined by the closed trenches 48 are partially located in the BOX layer 14 and partially located in the device layer 12.
Processing continues as described in the context of
With reference to
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
References herein to terms such as “vertical”, “horizontal”, “lateral”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. Terms such as “horizontal” and “lateral” refer to a direction in a plane parallel to a top surface of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. Terms such as “vertical” and “normal” refer to a direction perpendicular to the “horizontal” and “lateral” direction. Terms such as “above” and “below” indicate positioning of elements or structures relative to each other and/or to the top surface of the semiconductor substrate as opposed to relative elevation.
A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
