Claims
- 1. A patterned substrate for integrated circuits, comprising:
- a substrate with a trench, said substrate having a top surface, said trench extending to at least a first point below said top surface of said substrate;
- an insulator layer positioned on sidewalls of said trench, said insulator layer extending from said first point up said sidewalls of said trench to a second point above said first point and below said top surface of said substrate, said insulator layer including a dopant; and
- a masking material positioned in said trench adjacent said insulator layer, said masking material extending from at or below said first point to a third point between said first point and said second point.
- 2. The patterned substrate of claim 1 wherein said dopant is selected from the group consisting of arsenic, phosphorous, boron, indium and antimony.
CROSS-REFERENCE TO RELATED APPLICATIONS
This patent application is related to the two concurrently filed patent applications having U.S. Ser. Nos. 08/865,260 and 08/865,258, and bearing the titles of "VAPOR PHASE ETCHING OF OXIDE MASKED BY RESIST OR MASKING MATERIAL" and "OXIDE LAYER PATTERNED BY VAPOR PHASE ETCHING", respectively, and the complete contents of these two concurrently filed applications is herein incorporated by reference.
US Referenced Citations (19)
Foreign Referenced Citations (3)
Number |
Date |
Country |
63-17553 |
Jan 1988 |
JPX |
63-36560 |
Feb 1988 |
JPX |
1-253956 |
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JPX |
Non-Patent Literature Citations (1)
Entry |
T.K. Whidden et al.; Catalyzed HF Vapor Etching of Silicon Dioxide for Micro-and Nanolithographic Masks; J. Electrochem. Soc., vol. 142, No. 4, Apr. 1995; pp. 1199-1205. |