Use of Scanning Theme Implanters and Annealers for Selective Implantation and Annealing

Information

  • Patent Application
  • 20070281450
  • Publication Number
    20070281450
  • Date Filed
    May 30, 2006
    18 years ago
  • Date Published
    December 06, 2007
    16 years ago
Abstract
A method and system for integrated circuit (IC) processing combines an ion implantation tool and a laser anneal tool in a single unit with a shared precision X-Y scanner. A semiconductor wafer is loaded onto a the X-Y table of the scanner. Data defining the desired ion implantation is used to first customize circuit areas on the semiconductor wafer by gating ON and OFF the ion beam while semiconductor wafer is scanned. Any inadvertent ion beam interruptions are noted by storing the locations of the interruptions. The wafer is then reprocessed to correct faults caused by the interruptions. The laser anneal tool positions the laser beam over the semiconductor wafer it is then scanned while gating the laser beam ON and OFF to custom anneal the wafer devices. Again, any inadvertent laser beam interruptions are detected and the locations of the interruptions are stored for reprocessing to correct faults.
Description

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:



FIG. 1 is a schematic diagram of an exemplary ion implanter suitable for use with embodiments of the present invention;



FIG. 2 is a schematic diagram of components in a laser annealing device suitable for use in embodiments of the present invention;



FIG. 3 is a schematic diagram of a single tool for implantation and laser annealing according to embodiments of the present invention; and



FIG. 4 is a flow diagram of method steps in embodiments of the present invention.





DETAILED DESCRIPTION OF THE INVENTION

In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits may be shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning timing, data formats within communication protocols, and the like have been omitted in as much as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art.


Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.



FIG. 1 illustrates elements of an ion implantation tool 100. An exemplary substrate 103 is positioned on an scanning device used to move the substrate 103 in a single plane with high precision. A bias voltage 104 may be applied to the substrate 103 to enhance the implantation process. A source of ions 106 are charged in unit 107 by voltage 105. The charged ions 109 are directed through an aperture 108. Separation magnets 101 are used to separate the ion stream 109 into a beam 102 of desired ions to be implanted and rejected beams 110 and 111 having ions not desired for implantation. The desired ions are attracted to the charged substrate 103. The potential differences between 104 and 105 serve to accelerate the ion beam 109 to increase its effectiveness. Ion beam 102 contains the specific ions that are desired in selected areas on substrate 103. The ion beam may be gated ON and OFF as the substrate 103 is scanned to implant desired areas.



FIG. 2 illustrates elements of a laser anneal tool 200. Laser 201 is the source of laser beam 204. Aperture 202 is used to shape the laser beam 204 and attenuator 203 serves to modulate its amplitude. Mirror 205 is used to re-direct laser beam 104 through lens system 206 which further focuses beam 204 into beam 208. Mirror 207 re-directs laser beam 204 to laser beam 208 that impinges on exemplary substrate 103 at an incident angle. Laser beam 209 is a reflected portion of laser beam 208 that is used to measure the laser beam power in power meter 210. Pyrometer 213 is used to measure the surface temperature of the substrate 103. Substrate or wafer 103 is scanned by laser beam 208 by moving table 212 with scanner 211.



FIG. 3 illustrates a combination tool 300 according to embodiments of the present invention. Combination tool 300 integrates elements of an ion implantation tool (e.g., 100) with elements of a laser anneal tool (e.g., 200). An exemplary loading station has a cartridge 302 of wafers (e.g., 303) to be processed. A shuttle 304 is used to position a wafer (e.g., 303) for loading onto a scanner 320 that is used to position wafer 303 under either head 311 or 307 in the X 306 and Y 305 directions. Heads 307 and 311 may contain either elements of a laser anneal device or elements of an ion implantation device. In this embodiment, tool element 309 is shown in active position 310 and inactive position 312. Likewise, tool element 316 is shown in inactive position 301 and in transition position 308 to its active position over scanner 320. The common scanner 320 is used to scan exemplary wafer 303 under the ion implantation head or the laser anneal head. Once wafer 303 has been implanted and annealed, it is placed on shuttle 315 that moves wafer 303 to exit cartridge 314.



FIG. 4 is a flow diagram 400 illustrating method steps used in embodiments of the present invention. In step 401, an single IC processing tool is configured to include an ion implant device and a laser anneal device that may be selectively positioned over a common scanner. In step 402, a wafer is placed on the scanner and the ion implantation beam is positioned over the wafer. In step 403, the wafer is scanned while the ion beam is gated ON and OFF in response to device data describing device ion implantation levels and locations. In step 403, locations of any unintentional ion beam interruptions are detected and stored. In step 404, the wafer is reprocessed by locating the ion beam over the areas of unintentional ion beam interruption and gating the ion beam ON and OFF to correct any implantation defects. In step 405, the wafer is scanned while the laser beam is gated ON and OFF in response to device data describing device anneal levels and locations. In step 405, locations of any unintentional laser beam interruptions are detected and stored. In step 406, the wafer is reprocessed by locating the laser beam over the areas of unintentional laser beam interruption and gating the beam ON and OFF to correct any anneal defects.


Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims
  • 1. An integrated circuit (IC) processing line comprising: an integrated processing tool having an precision X-Y scanner with a moveable table for receiving a semiconductor wafer;a loader for loading the semiconductor wafer onto the precision X-Y scanner;an unloader for unloading the semiconductor wafer from the precision X-Y scanner;an ion implanting tool configured to be selectively positioned over the semiconductor wafer on the precision X-Y scanner; anda laser anneal tool configured to be selectively positioned over the semiconductor wafer on the precision X-Y scanner, wherein the semiconductor wafer is sequentially processed to selectively fabricate devices on the semiconductor wafer by first scanning the semiconductor wafer while gating ON and OFF an ion beam in the ion implantation tool and then scanning the semiconductor wafer while gating ON and OFF a laser beam in the laser anneal tool.
  • 2. The IC processing line of claim 1, wherein locations on the semiconductor wafer experiencing unintentional ion or laser beam interruption are detected and stored in a database.
  • 3. The IC processing line of claim 2, wherein the locations on the semiconductor wafer that experienced either unintentional ion beam or laser beam interruption are rescanned and reprocessed by selectively gating ON and OFF either the ion beam or the laser beam as applicable.
  • 4. A method for integrated circuit (IC) processing in a single integrated ion implantation and laser anneal tool comprising the step of: processing a semiconductor wafer in the single tool system by first scanning the semiconductor wafer under the ion implantation tool while gating an ion beam ON and OFF to selectively modify device areas on the semiconductor wafer; andprocessing the wafer in the single tool system by secondly scanning the semiconductor wafer under the laser anneal tool while gating a laser beam ON and OFF to selectively anneal device areas on the semiconductor wafer.
  • 5. The method of claim 4 further comprising detecting and storing locations on the semiconductor wafer of either unintentional ion beam or laser beam interruption.
  • 6. The method of claim 5 further comprising the steps of: rescanning to the locations on the semiconductor wafer of either unintentional ion beam or laser beam interruption; andreprocessing areas on the semiconductor wafer of unintentional beam interruption, by a selectively gating ON and OFF either the ion beam or the laser beam as applicable.
  • 7. The method of claim 4, wherein no photoresist layer is applied to the semiconductor wafer before a step of ion implantation or a step of laser annealing.