Patent Application
20230290706
The distribution of power consumption density across the area of an integrated circuit component having heterogeneous architectures (e.g., a combination of one or more different processor units (such as graphics processing units (GPU), compute-intensive “big core” central processor units (CPU), and low-power “small core” processor units) can vary based on the workload being performed by the respective processor units. The variations in power consumption density introduce thermal management challenges because excessive temperature can reduce lifetime and functionality of the integrated circuit component.
The variations in power consumption density across an integrated circuit component introduce technical challenges. In integrated circuit components with heterogeneous architectures (heterogeneous dies), different types of processor units (e.g., graphics processing unit (GPU), high performance central processing units (CPUs), and low-power CPUs) are integrated onto a single heterogenous die. During operation of the heterogenous die, the different processor unit types may be utilized to perform the work of the operation, and the work performed consumes power. Thus, the operational power consumption of a heterogeneous die can result in hotspots (areas of high temperature due to high power consumption levels) in different locations on the heterogeneous die. The hotspots are thermal management challenges because excessive temperature can reduce lifetime and functionality of the integrated circuit component.
The application of vapor chamber integrated heat spreaders (IHS) represents one technical solution to this technical challenge. However, the use of vapor chambers to cool heterogeneous dies can have drawbacks. A vapor chamber has a limit on an amount of power (referred to as a maximum power, Qmax) it can cool without failure. This failure mechanism is referred to as dry-out/dry-off. Typically, this maximum power, Qmax, is due to a phenomenon called a capillary limit, which is a limit on, or a maximum mass rate of, a liquid the wick can pull back to a hotspot using its capillary forces. The working fluid is generally selected to maximize Qmax.
To remove the requisite amount of heat at a hotspot to keep an integrated circuit component operating within its thermal limits, vapor chamber designs are faced with the competing demands of having a wick thick enough to allow enough working fluid to return to hotspot regions to allow for continued heat removal and having a thin vapor chamber to enable a low evaporative resistance. Additive processing approaches may enable the manufacture of thin vapor chambers that have a sufficiently low Reap, but such manufacturing approaches can add cost and thin vapor chambers may not address the need of having a sufficiently thick wick. The difficulty in satisfying these competing demands may cause a reduction in the maximum burst power levels that an integrated circuit component can operate at (such as the PL2 power level for some Intel® processors, described in more detail below) generation over generation, due to increasing power consumption densities.
Embodiments described herein provide a technical solution to these technical problems in the form of a surplus liquid reservoir that can be placed near a hotspot (specifically, next to a heat source that generates the hotspot) of a heterogenous die. The surplus liquid reservoir can be opportunistically sized and placed near the heat sources that generate the hotspots, to improve cooling capability with additional working fluid and vapor. Owing to the fast response times of vapor movement in a vapor chamber and the proximity of the vapor to the heat source, provided embodiments are well suited for burst (turbo) power scenarios.
Accordingly, embodiments provide a technically improved vapor chamber IHS. The addition of the surplus liquid, via the liquid reservoir, is a technical improvement to the vapor chamber IHS, as it increases the volume of working fluid that is available to the liquid channel IHS in the proximity of a heat source, thereby delaying or averting dryout/dry-off during high power consumption and increasing the thermal performance of the vapor chamber IHS. The embodiments described herein can have the further advantage of enabling or continuing the use of thin vapor chambers. Thinner vapor chambers may enable thinner computing system designs that have a more aesthetically pleasing industrial design.
In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding thereof. It may be evident, however, that the novel embodiments can be practiced without every one of these specific details. In other instances, well-known circuits, structures, and techniques may not have been shown in detail, to avoid obscuring an understanding of this description. Phrases such as “an embodiment,” “various embodiments,” “some embodiments,” and the like may include features, structures, or characteristics, but not every embodiment necessarily includes every feature, structure, or characteristic. The intention is to cover all modifications, equivalents, and alternatives within the scope of the claims.
Some embodiments may have some, all, or none of the features described for other embodiments. “First,” “second,” “third,” and the like describe a common object and indicate different instances of like objects being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally or spatially, in ranking, or any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and “coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
As used herein, the phrase “located on,” in the context of a first layer or first component located on a second layer or second component, refers to either the first layer or component being directly physically attached to the second layer or component (no layers or components between the first and second layers or components), or the first layer or component being physically attached to the second layer or component via one or more intervening layers or components. For example, with reference to
As used herein, the terms “processor unit”, “processing unit” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. A processor unit may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. As such, the processor unit can be referred to as an XPU (or xPU).
As used herein, the term “electronic component” can refer a battery, or a passive electronic component (e.g., a resistor, an inductor, and a capacitor).
An “integrated circuit component,” as used herein, can comprise at least one processor unit or at least one electronic component, or a combination of processor units and electronic components. Non-limiting examples of an integrated circuit component include a single monolithic integrated circuit die (shortened herein to “integrated circuit die” and “die” and described in more detail in connection with
As used herein, the phrase “thermally coupled” refers to components that are coupled to facilitate the transfer of heat between them. A thermal interface material (TIM) can be any suitable material to achieve thermal coupling, such as, a silver thermal compound, thermal grease, phase-change materials, indium foils or graphite sheets.
As used herein, the phrase “mechanically coupled” refers to components that are affixed or physically attached (as may be achieved by any combination of soldering, the use of adhesives, the use of fasteners, or the like) to each other, often, to achieve a resulting structure. In various embodiments, mechanically coupled can include releasably attached configurations, such as, those that require application of a torque exceeding a threshold torque to release them.
As may be appreciated by one with skill in the art, thermally coupled and mechanically coupled are not necessarily mutually exclusive, and a coupling between two components can facilitate more than one purpose.
In various processing units, a steady state power level, or power level one (PL1) of some Intel® processors, is a steady operating power level for a processor unit. In contrast, the aforementioned burst power level, or power level two (PL2) of some Intel® processors, represents a “turbo” mode, which is a power level above the PL1 that the processor unit can operate for a short, predefined, duration of time before needing to scale back to PL1.
Reference is now made to the drawings, which are not necessarily drawn to scale, but can be relied upon for general location and orientation purposes for one or more embodiments. As may be appreciated, certain terminology, such as “ceiling” and “floor”, as well as “upper,”, “uppermost”, “lower,” “above,” “below,” “bottom,” and “top” refer to directions based on viewing the Figures to which reference is made. Further, terms such as “front,” “back,” “rear,”, “side”, “vertical”, and “horizontal” may describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated Figures describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
In the drawings, similar or same numbers may be used to designate same or similar parts in different figures. The use of similar or same numbers in different figures does not mean all figures including similar or same numbers constitute a single or same embodiment. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
Although the images in
A reservoir leg 108 is configured to include a liquid reservoir of additional working fluid (referred to as a second working fluid) for use by the heat transfer portion 102. Accordingly, the reservoir leg 108 comprises a volume referred to as a reservoir portion 120, having therein a second wick material 122 that is in contact with the first wick material 106 and further having the second working fluid. The reservoir leg 108 is attached or mechanically coupled, on a first side 138 (e.g., a ceiling side), to bottom side 121, or an integrated circuit component-facing side, of the heat transfer portion 102 and extends generally perpendicular (downward on the page) from the heat transfer portion 102. The first wick material 106 and the second wick material 122 are in contact and thermally coupled. The first wick material 106 and the second wick material 122 may or may not be the same.
The first working fluid and the second working fluid are each a two-phase working fluid, the characteristics of which are further defined herein. The first working fluid and the second working fluid may or may not be the same. When the first working fluid and the second working fluid are not the same, they are miscible. The first working fluid and the second working fluid can comprise water, ammonia, methanol, refrigerants, ethanol, or any of the following fluids or mixture of fluids: sodium dodecyl (SDS), lauryl sulfate (SLS), water and alcohol (the alcohol percentage can range from 10-80%), water and pentane, methanol, ethanol, water and propylene glycol (the propylene glycol percentage can range from 15%-80%), ammonia, ethane, acetone, pentane, refrigerant R-141b (dichlorofluoroethane), refrigerant R-134a, or another fluid or fluid mixture suitable for the purpose described herein.
In operation, the heat transfer portion 102 is filled with a combination of the first working fluid held by the first wick material 106 and vapor (the gas state of the first working fluid) occupying the vapor channel 104. Heat from a heat source 156 causes the first working fluid in the first wick material 106 to vaporize. The vapor travels along the vapor channel 104, away from a hot spot to a cooler location in the heat transfer portion 102, where it condenses back into a liquid state and goes into the first wick material 106. The capillary force in the first wick material 106 pulls the liquid form of the first working fluid back to the area of the heat transfer portion 102 over the heat source 156, thus completing a vapor-liquid flow loop. There is a maximum capillary pressure (liquid flow rate) the first wick material 106 can provide, defined by its material and its porous structure. The power at which the rate of vaporization matches this maximum liquid flow rate is defined as Qmax and the phenomenon is referred to as the capillary limit. In various embodiments, the reservoir portion 120 provides surplus working fluid (in liquid state) pulled by the capillary action 160 into the heat transfer portion 102 at the site of the hot spot, to bolster the performance of the heat transfer portion 102.
The reservoir leg 108 has a leg height 110. In various embodiments, such as, when the reservoir leg 108 is used for structural support, the leg height 110 is predefined, generally, as a function of a target integrated circuit component (see, e.g.,
The wall is depicted with outside wall 114 and inside wall 116, which may or may not be equal. In this context, the inside wall 116 is configured to face a cavity 124 and be located next to a heat source 156, and the outside wall is furthest from the heat source 156 in the Figure. As used herein, a component being described as “next to” a second component can be physically touching the second component or not physically touching the second component, yet adjacent to, or proximate to, the second component.
The cavity 124 is created by the integration of one or more reservoir legs 108 and one or more support legs 152 (wherein support legs 152 are characterized as legs not comprising a reservoir) with the heat transfer portion 102.
In various embodiments, the reservoir portion 120 may have a wall thickness of about 10-20% of a width 112 of the reservoir leg 108. The second wick material 122 substantially fills the reservoir portion 120 and may occupy about 60-80% of a volume of the reservoir leg 108.
The first wick material 106 and the second wick material 122 can comprise sintered copper powder, copper fibers (which, in some embodiments, can be woven into forms such as a screen, mesh, or braids), or grooves integrated into a surface of the vapor chamber 104. The first wick material 106 and the second wick material 122 can comprise a pattern or a plurality of patterns. In some embodiments, the first wick material 106 and the second wick material 122 are different from each other. In other embodiments, the first wick material 106 and the second wick material 122 are the same.
With reference to
Although the wall 136 may have a wall thickness that is not necessarily uniform as one circumnavigates the wall, the wall 136 is continuous or uninterrupted radially, around its axis, substantially enclosing the volume 130 of the reservoir portion in the Z direction. The wall thickness may be subject to a minimum thickness that is a function of a first requirement to prevent leakage of the second working fluid. The minimum thickness may also be a function of a second requirement to support at least a portion of a load applied by the main heat transfer portion 102. The reservoir portion 136 is characterized by a wall height 132 that is the leg height 110 minus a floor thickness. The floor thickness may be in the range of 100 to 200 microns. The floor 118 may have a floor thickness substantially equal to the thickness of the wall. As used herein, “substantially” equal to means plus or minus two percent from the thickness of the wall.
The heat source 156 may be all or part of an integrated circuit component that can comprise a plurality of processor units. The apparatus 150 may further be part of a larger microelectronic assembly (see, e.g.,
In the example, the heat source 156 is a target for the reservoir leg 108, so the reservoir leg 108 is located next to the targeted heat source, heat source 156. It is important that a respective reservoir leg 108 be near the heat source 156 that is targeted for the respective reservoir leg, such that working fluid can efficiently flow into an evaporator region of the heat transfer portion 102 during high power transients or burst power by the heat source 156. Although the reservoir leg 108 is depicted as being located next to the heat source 156 and also at a peripheral edge of a die that the apparatus 150 may embody, in other embodiments, the reservoir leg 108 may be internal to an integrated circuit component. In various embodiments, the reservoir leg 108 is a first reservoir leg of multiple reservoir legs 108, the multiple reservoir legs are arranged around the heat source such that they are all located next to the heat source 156. In various embodiments, one or more reservoir legs 108 are substantially perpendicular and extending downward (with the orientation of downward as shown in the illustration) from the heat transfer portion 102.
Whereas
As shown in
In some embodiments, the reservoir portion 120 can be created by modifying an existing stability leg (e.g., stability leg 152) to thereby create a reservoir leg 108 with the reservoir portion 120 having the second wick material 122 and surplus working fluid (the second working fluid), and mechanically coupling the reservoir leg 108 to the main heat spreader portion 102 and/or to a substrate 158 using conventional sealant attach methods. In some embodiments, the reservoir portion 120 can be created by stamping a material into a shape that embodies both the reservoir leg 108 and the reservoir portion 120 and, in various embodiments, the same continuous piece of material may additionally embody a floor side of the heat transfer portion 102.
Each solution illustrated in
In practice, the surplus liquid reservoir feature disclosed herein is expected to enable the maximum operating power of integrated circuit components (e.g., PL2 levels) to increase by an amount of 10-15% for some integrated circuit component designs. For example,
Operation time=(Energysurplus)/(PL2−Qmax) Eq. 1
this amount of surplus energy can support the difference between the PL2 and the Qmax (241−200=41 W) for about 70 seconds, which is an objective improvement over existing vapor chamber IHS designs. Thus, as shown in
Described differently, the heat spreader apparatus 100 includes a primary heat transfer means configured to cool a heat source, the primary heat transfer means being thermally coupled to the heat source, plus a surplus heat transfer means configured to provide surplus liquid to the primary heat transfer means when operating above Qmax.
As those with skill in the art will appreciate, the embodiment depicted in
The die 502 may include one or more transistors (e.g., some of the transistors 640 of
The integrated circuit component 600 may include one or more device layers 604 disposed on the die substrate 602. The device layer 604 may include features of one or more transistors 640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 602. The transistors 640 may include, for example, one or more source and/or drain (S/D) regions 620, a gate 622 to control current flow between the S/D regions 620, and one or more S/D contacts 624 to route electrical signals to/from the S/D regions 620. The transistors 640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 640 are not limited to the type and configuration depicted in
Returning to
The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 640 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 602 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 602. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 602 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 602. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 620 may be formed within the die substrate 602 adjacent to the gate 622 of individual transistors 640. The S/D regions 620 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 602 to form the S/D regions 620. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 602 may follow the ion-implantation process. In the latter process, the die substrate 602 may first be etched to form recesses at the locations of the S/D regions 620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 620. In some implementations, the S/D regions 620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 620 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 620.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 640) of the device layer 604 through one or more interconnect layers disposed on the device layer 604 (illustrated in
The interconnect structures 628 may be arranged within the interconnect layers 606-610 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 628 depicted in
In some embodiments, the interconnect structures 628 may include lines 628a and/or vias 628b filled with an electrically conductive material such as a metal. The lines 628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 602 upon which the device layer 604 is formed. For example, the lines 628a may route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias 628b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate 602 upon which the device layer 604 is formed. In some embodiments, the vias 628b may electrically couple lines 628a of different interconnect layers 606-610 together.
The interconnect layers 606-610 may include a dielectric material 626 disposed between the interconnect structures 628, as shown in
A first interconnect layer 606 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 604. In some embodiments, the first interconnect layer 606 may include lines 628a and/or vias 628b, as shown. The lines 628a of the first interconnect layer 606 may be coupled with contacts (e.g., the S/D contacts 624) of the device layer 604. The vias 628b of the first interconnect layer 606 may be coupled with the lines 628a of a second interconnect layer 608.
The second interconnect layer 608 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 606. In some embodiments, the second interconnect layer 608 may include via 628b to couple the lines 628 of the second interconnect layer 608 with the lines 628a of a third interconnect layer 610. Although the lines 628a and the vias 628b are structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines 628a and the vias 628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
The third interconnect layer 610 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 608 according to similar techniques and configurations described in connection with the second interconnect layer 608 or the first interconnect layer 606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 619 in the integrated circuit component 600 (i.e., farther away from the device layer 604) may be thicker that the interconnect layers that are lower in the metallization stack 619, with lines 628a and vias 628b in the higher interconnect layers being thicker than those in the lower interconnect layers.
The integrated circuit component 600 may include a solder resist material 634 (e.g., polyimide or similar material) and one or more conductive contacts 636 formed on the interconnect layers 606-610. In
In some embodiments in which the integrated circuit component 600 (e.g., heat source 156) is a double-sided die, the integrated circuit component 600 may include another metallization stack (not shown) on the opposite side of the device layer(s) 604. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 606-610, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 604 and additional conductive contacts (not shown) on the opposite side of the integrated circuit component 600 from the conductive contacts 636.
In other embodiments in which the integrated circuit component 600 is a double-sided die, the integrated circuit component 600 may include one or more through silicon vias (TSVs) through the die substrate 602; these TSVs may make contact with the device layer(s) 604, and may provide conductive pathways between the device layer(s) 604 and additional conductive contacts (not shown) on the opposite side of the integrated circuit component 600 from the conductive contacts 636. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit component 600 from the conductive contacts 636 to the transistors 640 and any other components integrated into the die 600, and the metallization stack 619 can be used to route I/O signals from the conductive contacts 636 to transistors 640 and any other components integrated into the die 600.
Multiple integrated circuit components 600 may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).
In various embodiments, the integrated circuit components 600 are assembled into packaged integrated circuit components. A packaged integrated circuit component can comprise one or more of the aforementioned integrated circuit dies mounted on a package substrate. The package substrate facilitates connectivity between the integrated circuit component and a circuit board. Non-limiting examples of the packaging substrate include chip scale packages (CSP), flip chip CSP (FC-CSP), board on chip (BOC), package in package (PiP), system in package (SiP), RF module and LED package. The integrated circuit dies and package substrate are further encapsulated in a casing material, such as a metal, plastic, glass, or ceramic. In one example, a packaged integrated circuit component contains one or more processor units mounted on a package substrate with an exterior surface of the substrate comprising a solder ball grid array (BGA).
In various embodiments, the integrated circuit components 600 are assembled into microelectronic assemblies. Turning now to
In some embodiments, the above-described integrated circuit components 600, packaged integrated circuit components, and/or microelectronic assemblies 700 can be attached to a printed circuit board located in a computing device that comprises a housing that encloses the printed circuit board and the integrated circuit component. In some embodiments, the printed circuit board further has a second integrated circuit component attached thereto.
The circuit board 702 may be a motherboard, system board, mainboard, or the like. In some embodiments, the circuit board 702 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 702. In other embodiments, the circuit board 702 may be a non-PCB substrate.
The microelectronic assembly 700 illustrated in
The package-on-interposer structure 736 may include an integrated circuit component 720 coupled to an interposer 704 by coupling components 718. The coupling components 718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 716. Although a single integrated circuit component 720 is shown in
The integrated circuit component 720 may be a packaged integrated circuit component that includes one or more integrated circuit dies (e.g., the die 502 of
In embodiments where the integrated circuit component 720 comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).
In addition to comprising one or more processor units, the integrated circuit component 720 can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.
Generally, the interposer 704 may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer 704 may couple the integrated circuit component 720 to a set of ball grid array (BGA) conductive contacts of the coupling components 716 for coupling to the circuit board 702. In the embodiment illustrated in
In some embodiments, the interposer 704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 704 may include metal interconnects 708 and vias 710, including but not limited to through hole vias 710-1 (that extend from a first face 750 of the interposer 704 to a second face 754 of the interposer 704), blind vias 710-2 (that extend from the first or second faces 750 or 754 of the interposer 704 to an internal metal layer), and buried vias 710-3 (that connect internal metal layers).
In some embodiments, the interposer 704 can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer 704 comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer 704 to an opposing second face of the interposer 704.
The interposer 704 may further include embedded devices 714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 704. The package-on-interposer structure 736 may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board
The microelectronic assembly 700 may include an integrated circuit component 724 coupled to the first face 740 of the circuit board 702 by coupling components 722. The coupling components 722 may take the form of any of the embodiments discussed above with reference to the coupling components 716, and the integrated circuit component 724 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 720.
The microelectronic assembly 700 illustrated in
Additionally, in various embodiments, the electrical device 800 may not include one or more of the components illustrated in
Embodiments of the electrical device 800 may include one or more processor units 802, defined above. The electrical device 800 may include a memory 804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory 804 may include memory that is located on the same integrated circuit die as the processor unit 802. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).
In some embodiments, the electrical device 800 can comprise one or more processor units 802 that are heterogeneous or asymmetric to another processor unit 802 in the electrical device 800. There can be a variety of differences between the processing units 802 in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units 802 in the electrical device 800.
In some embodiments, the electrical device 800 may include a communication component 812 (e.g., one or more communication components). For example, the communication component 812 can manage wireless communications for the transfer of data to and from the electrical device 800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication component 812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra-mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication component 812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication component 812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 800 may include an antenna 822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication component 812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component 812 may include multiple communication components. For instance, a first communication component 812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 812 may be dedicated to wireless communications, and a second communication component 812 may be dedicated to wired communications.
The electrical device 800 may include battery/power circuitry 814. The battery/power circuitry 814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 800 to an energy source separate from the electrical device 800 (e.g., AC line power).
The electrical device 800 may include a display device 806 (or corresponding interface circuitry, as discussed above). The display device 806 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 800 may include an audio output device 808 (or corresponding interface circuitry, as discussed above). The audio output device 808 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.
The electrical device 800 may include an audio input device 824 (or corresponding interface circuitry, as discussed above). The audio input device 824 may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device 800 may include a Global Navigation Satellite System (GNSS) device 818 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 818 may be in communication with a satellite-based system and may determine a geolocation of the electrical device 800 based on information received from one or more GNSS satellites, as known in the art.
The electrical device 800 may include another output device 810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 800 may include another input device 820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 820 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.
The electrical device 800 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device 800 may be any other electronic device that processes data. In some embodiments, the electrical device 800 may comprise multiple discrete physical components. Given the range of devices that the electrical device 800 can be manifested as in various embodiments, in some embodiments, the electrical device 800 can be referred to as a computing device or a computing system.
As used in this application and the claims, items joined by the term “and/or” can mean any combination of the items. For example, the phrase “A and/or C” can mean A; C; or A and C. As used in this application and the claims, a list of items joined by the term “at least one of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B, and C. Moreover, as used in this application and the claims, a list of items joined by the term “one or more of” can mean any combination of the listed terms. For example, the phrase “one or more of A, B and C” can mean A; B; C; A and B; A and C; B and C; or A, B, and C.
As used in this application and the claims, the phrase “individual of” or “respective of” following by a list of items recited or stated as having a trait, feature, etc. means that all of the items in the list possess the stated or recited trait, feature, etc. For example, the phrase “individual of A, B, or C, comprise a sidewall” or “respective of A, B, or C, comprise a sidewall” means that A comprises a sidewall, B comprises sidewall, and C comprises a sidewall.
The disclosed methods, apparatuses, and systems are not to be construed as limiting in any way. Instead, the present disclosure is directed toward all novel and nonobvious features and aspects of the various disclosed embodiments, alone and in various combinations and sub combinations with one another. The disclosed methods, apparatuses, and systems are not limited to any specific aspect or feature or combination thereof, nor do the disclosed embodiments require that any one or more specific advantages be present, or problems be solved.
Theories of operation, scientific principles, or other theoretical descriptions presented herein in reference to the apparatuses or methods of this disclosure have been provided for the purposes of better understanding and are not intended to be limiting in scope. The apparatuses and methods in the appended claims are not limited to those apparatuses and methods that function in the manner described by such theories of operation.
Although the operations of some of the disclosed methods are described in a particular, sequential order for convenient presentation, it is to be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth herein. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the attached figures may not show the various ways in which the disclosed methods can be used in conjunction with other methods.
The following examples pertain to additional embodiments of technologies disclosed herein.
