The present invention relates generally to imaging devices and fabrication methods for forming an imaging pixel cell.
Solid state imager devices which include charge-coupled-devices (CCD) and complementary metal oxide semiconductor (CMOS), have commonly been used in photo-imaging applications.
Imager devices typically contain thousands of pixel cells in a pixel array on a single chip. Pixel cells convert light into an electrical signal that can then be stored and recalled by an electrical device such as, for example, a processor. The electrical signals that are stored may be recalled to produce an image on, for example, a computer screen or a printable media.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524, and U.S. Pat. No. 6,333,205, each of which is assigned to Micron Technology, Inc. The disclosures of each of the forgoing patents are hereby incorporated by reference in their entirety.
Solid state imager devices typically have an array of pixel cells containing photosensors, where each pixel cell produces a signal corresponding to the intensity of light impinging on that element when an image is focused on the array. These signals may then be used, for example, to display a corresponding image on a monitor or otherwise used to provide information about the optical image. The photosensors are typically photogates, phototransistors, photoconductors or photodiodes, where the conductivity of the photosensor corresponds to the intensity of light impinging on the photosensor. The magnitude of the signal produced by each pixel cell, therefore, is proportional to the amount of light impinging on the photosensor.
CMOS active pixel sensor (APS) solid state imaging devices are described, for example, in the foregoing patents. These imaging devices include an array of pixel cells, arranged in rows and columns, that convert light energy into electric signals. Each pixel includes a photodetector and one or more active transistors. The transistors typically provide amplification, read-out control and reset control, in addition to producing the electric signal output from the cell.
While CCD technology has a widespread use, CMOS imagers are being increasingly used as low cost imaging devices. A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, for example, a photogate, photoconductor, phototransistor, or a photodiode for accumulating photo-generated charge in a portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output transistor, which receives photogenerated charges from a doped diffusion region and produces an output signal which is periodically read out through a pixel access transistor. The imager may optionally include a transistor for transferring charge from the photoconversion device to the diffusion region or the diffusion region may be directly connected to or be part of the photoconversion device. A transistor is also typically provided for resetting the diffusion region to a predetermined charge level before it receives the photoconverted charges.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to a floating diffusion region accompanied by charge amplification; (4) resetting the floating diffusion region to a known state; (5) selection of a pixel cell for readout; and (6) output and amplification of a signal representing the pixel cell charge. Photo-charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion region. The charge at the floating diffusion region is typically converted to a pixel output voltage by a source follower output transistor.
To detect color, the spectral components of incident light must be separated and collected. An absorptive color filter array (CFA) on top of an imager chip may be used for color detection in a solid state image sensor, for example, a CCD or CMOS imager. In a typical CFA layout, a color filter for each individual photosensor of the imager allows only a narrow spectral band (red, green, or blue) to pass, and absorbs the rest of the photo energy.
Each pixel cell receives light that may have been focused through one or more micro-lenses. Micro-lenses on a CMOS imager help increase optical efficiency and reduce optical cross-talk between pixel cells. A reduction of the size of the pixel cells allows for a greater number of pixel cells to be arranged in a specific pixel cell array, thereby increasing the resolution of the array. In one process for forming micro-lenses, the radius of each micro-lens is correlated to the size of the pixel cell. Thus, as the pixel cells decrease in size, the radius of each micro-lens also decreases.
Electrical cross-talk is also a problem with imaging devices. Electrical cross-talk occurs when photo-generated charge from a pixel is collected by an adjacent or neighboring pixel. For example, an electron generated in the silicon under the red pixel, rather than diffusing up to be collected by the red photodiode, may have a significant lateral component, and be collected by an adjacent green photodiode.
Cross-talk can bring about undesirable results in the images that are produced. The undesirable results can become more pronounced as the density of pixel cells in imager arrays increases, and as pixel cell size correspondingly decreases. The shrinking pixel cell size also make it increasingly difficult to focus incoming light on the photosensor of each pixel cell, aggravating cross-talk.
Cross-talk can manifest as a blurring or reduction in contrast in images produced by a solid-state imager. In essence, cross-talk in an image sensor array degrades the spatial resolution, reduces overall sensitivity, causes color mixing, and leads to image noise after color correction. As noted above, image degradation can become more pronounced as pixel cell and device sizes are reduced.
Another problem in conventional imager devices is blooming or saturation. Blooming occurs when too many photons strike a particular pixel cell and the generated electrons overflow into adjacent pixel cells, artificially increasing the electron counts of those pixel cells.
Another common problem associated with conventional imager pixel cells is dark current, that is, current generated as a photo-conversion device signal in the absence of light. Dark current may be caused by many different factors, including: photosensor junction leakage, leakage along isolation edges, transistor sub-threshold leakage, drain induced barrier lowering leakage, gate induced drain leakage, trap assisted tunneling, and pixel cell fabrication defects.
There is needed, therefore, an imager device having reduced cross-talk, reduced blooming and decreased dark current. Also needed is a simple method of fabricating and operating such a pixel.
The present invention provides an imager method and apparatus for reducing electrical color cross-talk. The invention also reduces blooming of excess electrons and reduces dark current.
The present invention provides an imager device having a buried doped region in the substrate, preferably an n+ doped region, that collects excess electrons and thus reduces cross-talk, reduces blooming of excess electrons and reduces dark current.
Additional advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and show by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical, and electrical changes may be made without departing from the spirit and scope of the present invention. The progression of processing steps described is exemplary of embodiments of the invention; however, the sequence of steps is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps necessarily occurring in a certain order.
The term “substrate” is to be understood to include any semiconductor-based structure. The semiconductor structure should be understood to include silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), silicon-germanium, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductors and semiconductor structures. When reference is made to the substrate in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation. The semiconductor also need not be formed of silicon, but may be formed of other semiconductor materials.
The terms “pixel” and “pixel cells” as used herein, refer to a photo-element unit cell containing at least one photosensor and additional structure for converting photons to an electrical signal. For purposes of illustration, a single representative pixel cells and its manner of formation are illustrated in the figures and description herein; however, typically fabrication of a plurality of like pixel cells proceeds simultaneously. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
The following description of the invention is provided within the exemplary environment of a CMOS pixel using a pinned photodiode as a photosensor; however, the invention is not limited to use in a CMOS imager or to use in a CMOS imager employing a pinned photodiode as a photosensor. Any type of photosensor may be used in the invention including photodiodes, photogates, and other photosensing devices.
The pixel array is covered by a protective layer 24 that acts as a passivation and planarization layer for the imager 20. Protective layer 24 may be a layer of BPSG, PSG, BSG, silicon dioxide, silicon nitride, polyimide, or other well-known light transmissive insulator.
A color filter layer 100 is formed over the passivation layer 24. The color filter layer 100 comprises an array of red, blue and green sensitive elements which may be arranged in a pattern understood by the person having ordinary skill in the art as exemplified by U.S. Pat. Nos. 6,783,900 and 3,971,065, which are herein incorporated by reference.
As also depicted in the figures, a micro-lens 70 is formed above each pixel cell. Each micro-lens 70 is formed such that its focal point is centered over the photosensitive elements in the corresponding pixel cell. A spacer layer 25 is also formed under the mircolens 70 and under the color filter layer 100. The thickness of spacer layer 25 is adjusted such that the photosensitive element is at a focal point for the light traveling through lenses 70.
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The n+ region 33 may be biased positive in operation. The n+ region 33 is preferably biased in operation at a positive voltage between 0.5V and Vdd. When the n+ region 33 is biased positive, dark current electrons formed in the substrate below the n+ region 33 are collected in the n+ region 33 and swept away prior to reaching the photosensor 34. Electrons generated from photons between photosensors 34 or those generated deep in the substrate and most prone to aggravate cross-talk are also collected in n+ region 33 and swept away, thereby reducing cross-talk. Electrons from pixel blooming will also be collected in n+ region 33.
A patterned n+ region 33, either continuous in the array as illustrated in
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As illustrated in
The imager device 20 described above with reference to
Reference is now made to
The p− epitaxial layer 31 is grown to form a transition between the p+ substrate 30 and the p− epitaxial layer 31. The p− epitaxial layer 31 may be grown with any method for growing single-crystal silicon. The thickness of the p-epitaxial layer 31 is from about 0.05 μm to about 5.0 μm, preferably from about 0.5 μm to about 1.5 μm.
Reference is now made to
Reference is now made to
Reference is now made to
According to the present invention, it is possible to connect the n+ doped region 33 with an n-well region in an imager device. The n-well, while not disclosed in the figures, is known in the imager devices discussed above and incorporated by reference. The incorporation of an n-well in imaging devices described herein are known to the person having ordinary skill in the art. For example, it may be necessary to connect the n+ doped region 33 with the n-well to make adequate top-side contact between the imager device and the n+ doped region.
Reference is now made to
From the resultant structure illustrated in
While the processes have been described with reference to a CMOS imager device, it should be understood that the process may be also used with pixel cells of other types of imagers as well, for example, with a CCD imager. Accordingly, the pixel cell formed as described above may be employed in CCD image sensors as well as CMOS image sensors.
The n+ doped layer 33 reduces cross-talk, blooming and dark current by collecting excess electrons in the imaging device. As discussed below, the n+ doped layer 33 may be biased positive to aid in electron collection within the imaging device. The biasing of the region can be accomplished by well known techniques for biasing a region.
A sample and hold (S/H) circuit 261 associated with the column driver 260 reads a pixel reset signal Vrst and a pixel image signal Vsig for selected pixel cells. A differential signal (Vrst−Vsig) is amplified by differential amplifier (AMP) 262 for each pixel and is digitized by analog-to-digital converter 275 (ADC). The analog-to-digital converter 275 supplies the digitized pixel signals to an image processor 280, which forms a digital image.
If desired, the imager 200 may be combined with a processor, such as a CPU, digital signal processor or microprocessor. The imager 200 and the microprocessor may be formed in a single integrated circuit. An exemplary processor system 300 using a CMOS imager having a n+ region in accordance with the present invention is illustrated in
As shown in
While the invention has been described in detail in connection with exemplary embodiments known at the time, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.