Patent Application
20210134995
This application claims foreign priority to European Patent Application No. EP 19207373.2, filed Nov. 6, 2019, the content of which is incorporated by reference herein in its entirety.
The disclosed technology relates generally to semiconductor devices, and more particularly to a vertical channel device and a method of forming a vertical channel device.
Vertical channel devices are being developed due to a need to provide more powerful and area-efficient semiconductor devices. Due to having regions arranged in the vertical direction, these devices may be scaled more efficiently to decrease the overall device footprint.
Vertical gate-all-around (GAA) devices are one of the main contenders for CMOS scaling beyond 5 nm because they feature excellent channel control by the gate wrapped around the channel, while they enable significant gain in transistor density due to their vertical structure. In addition, they have other benefits, including lower gate edge roughness and sharper junction profiles obtained through vertical processes, such as epitaxial growth and deposition instead of implant and etch used for horizontal channels.
However, there is a need in the art for improved methods for providing vertical channel devices having a self-aligned channel on the gate.
It is an object of the disclosed technology to at least partly overcome one or more limitations of the prior art. In particular, it is an object to provide a vertical channel device having a self-aligned channel on the gate and a method of forming such a vertical channel device.
In a first aspect, a method of forming a vertical channel transistor structure comprises the steps of:
The method of the first aspect of the disclosure is thus a channel-last process flow, in which a channel structure is epitaxially grown on the first, lower source/drain portion to provide a vertical channel transistor structure.
As used herein, the term vertical denotes a direction being parallel to a vertical geometrical axis extending perpendicular to the substrate. The terms “above”, “below”, “upper” and “lower” are thus used to refer to relative positions along the vertical axis. In addition, the term lateral or horizontal refers to the direction perpendicular to the vertical direction, i.e. to the direction parallel to the substrate surface.
In the context of the present disclosure, a “vertical channel structure” is a structure in which the current flow of charge carriers between a source region and a drain region is perpendicular to the substrate surface, i.e. along the normal to the main surface of the substrate, during use of the The vertical channel transistor structure may thus be a semiconductor transistor structure having a channel that is oriented vertically with respect to the substrate surface, i.e. comprising a vertical channel structure as discussed above in which the net direction of charge is along the normal to the surface of the substrate during use. As an example, the vertical channel transistor structure may be a field-effect transistor (FET).
The first aspect of the disclosure is based on the insight that forming a vertically extending portions around a gate in a channel-last process allows for self-alignment of the vertical channel over the gate. The lateral width of the vertical channel may be adjusted by how much spacer material that is deposited at the sidewalls of the vertically extending portions before etching and epitaxial growth of the channel. Thus, the method of the first aspect allows for a straighter channel profile compared to when using e.g. trimming operations.
As an example, the method of the first aspect of the disclosure may be realized by use a gate mask to define two “negative gate” hard masks whose spacers are used to define the opening of the gate around the channel through which the channel is grown. Such an embedded epi growth of the channel enables a self-aligned channel with respect to the gate mask.
Thus, in embodiments of the first aspect, the deposition of the gate material in step b) is performed using a first hard photoresist mask and the formation of the vertically extending portions around the gate in step b) is performed using a second hard photoresist mask, wherein the second hard photoresist mask is the negative of the first hard photoresist mask, at least over the gate region of the device.
Step a) of forming a bottom source/drain region on a substrate surface may for example be performed by straight etching in a substrate wafer, thereby forming a bottom source/drain region. The substrate surface may be a semiconductor material, such as a single crystalline, polycrystalline or amorphous semiconductor material. As an example, the substrate may be single crystalline silicon.
The bottom source/drain region may be of the same material as the substrate or of a different material. As an example, the bottom source/drain region may comprise epitaxially grown SiGe, which is grown on a Si substrate. Other suitable materials for the bottom source/drain region include Si:C on a Si substrate, InGaAs on an InP substrate and GaAs on a GaAs substrate.
In embodiments of the first aspect, step a) also comprises forming insulating material around the sides of the bottom source/drain region. This insulating material may for example be an STI oxide, such as silicon dioxide.
Step a) also comprises depositing a spacer oxide layer over the bottom source/drain region. The spacer oxide may for example be any suitable inter layer dielectric (ILD). As an example, the spacer oxide layer may include a low-k dielectric material such as silicon oxide, boron nitride or silicon carbon boron nitride.
Step b) comprises the formation of vertically extending portions and the deposition of gate material. These substeps may be performed in any order.
Thus, in embodiments of the first aspect, the gate material is deposited before formation of the vertically extending portions in step b). This may then be patterned and thereafter the vertically extending portions may be formed at positions where the gate material is removed, i.e. in a “fill and recess” or “etch-back” process.
However, in embodiments of the first aspect, the gate material is deposited after formation of the vertically extending portions in step b). Thus, the vertically extending portions may first be formed, such as using a “fill and recess” or “etch-back” process, the gate material may then be deposited in between the vertically extending portions.
The vertically extending portions are formed so that they extend over the formed gate. The vertically extending portions may extend all around the gate, thereby forming a continuous vertically extending portion around the gate. The vertically extending portions may also be formed so that they extend on two opposite sides of the gate, as seen in a cross-section through the gate. Thus, step b) may comprise forming two vertically extending portion on either side of the deposited gate material, as seen in a cross-section in a plane parallel to the normal of the substrate.
The vertically extending portions may comprise a dielectric nitride, such as SiN.
In embodiments of the first aspect, the vertically extending portions comprises SiN. Thus, the vertically extending portions may consist of SiN.
The vertically extending portions can be formed utilizing a deposition process such as, for example, physical vapour deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD) or chemical vapour deposition (CVD).
The gate material deposited in step b) may be the material of the final gate of the vertical channel transistor structure, such as a final metal gate. However, the gate material deposited in step b) may also be a dummy gate material that is replaced later in the process, such as after step g).
Depositing spacer material at the sidewalls of step c) may be performed using conventional conformal deposition methods. The spacer material may be SiN. Thus, in embodiments of the first aspect, the vertically extending portions comprises or consist of SiN, and also the spacer material deposited in step c) comprises or consists of SiN.
The spacer material is deposited at the sidewalls such that a small lateral gap is left between the vertical structures. This gap is positioned vertically over the gate material deposited in between the vertically extending portions and over the bottom source/drain portion. The depositing of spacer material of step c) may comprise a first deposition of spacer material, followed by a spacer etch. The spacer etch may include an anisotropic etch to remove spacer material that has been deposited on horizontal surfaces.
Examples of etching that may be used for etching the deposited spacer material is reactive-ion etching (RIE).
Examples of deposition processes that can be used in depositing the spacer material include, for example, CVD, PVD, PECVD or atomic layer deposition (ALD).
Forming the vertical opening of step d) may include lithography and etching.
Lithography may include forming a photoresist layer atop the deposited and etched spacer layer, which may be patterned using a pattern of irradiation as known in the art. Etching may then be performed at the areas exposed in the pattern. Thus, the vertical opening of step d) may include etching processes, such as a straight etch process through the gate down to the bottom source/drain region.
The formation of the vertical opening in step d) may thus lead to the formation of a final gate, e.g., when an opening is formed through the deposited gate material.
Consequently, in embodiments of the first aspect, step d) comprises forming a patterned photoresist layer over the deposited spacer material such that an opening in the photoresist layer overlays with the position of the gap, and wherein step d) further comprises straight etching in the opening to form the opening through the gate material.
As an alternative, forming the vertical opening in step d) may comprise etching without photoresist, with an etch that is self-aligned on the vertically extending portions.
Further, the method may also comprise forming vertically openings on the opposite sides of the vertically extending portions, i.e. at the sides of the vertically extending portions that do not face the gap. These openings may form the position of vertically extending channels in other transistor structures being formed next to the vertically channel transistor structure.
After a vertical opening down to the bottom source/drain region has been performed in step d), an oxide is deposited at the exposed sidewall of the gate in step e). This oxide thus functions as a gate oxide isolating the gate from the subsequently formed vertical channel. The gate oxide may be any material as know for a person skilled in the art such as Silicon oxide (SiO2, SiON), or high-K dielectrics such as HfO2, HfSiN or HfSiO.
Depositing of the oxide at the exposed sidewalls in step e) may comprise a conformal deposition of the oxide, thus covering both the sidewalls of the gate in the vertical opening and the lateral surface in the opening and next to the opening. Step e) may then comprise a straight etch to remove deposited oxide at the lateral surfaces, thereby leaving gate oxide deposited at the exposed sidewalls of the gate. The straight etch may be performed by anisotropic etching, i.e. orientation dependent etching, of the exposed lateral surfaces. The anisotropic etch of the gate oxide, e.g. SiO2 and HfO2, may be performed with plasma (dry) using carbon fluoride chemistry.
The vertical channel portion is epitaxially grown in step f). The channel is grown such that is extends vertically above the gate. The semiconductor material grown on the bottom source/drain portion to form the vertical channel structure may be selected from the group consisting of silicon, silicon germanium (SiGe), silicon carbide (SiC), Silicon carbon germanium (SiCGe), germanium (Ge) and group III-V compounds.
In embodiments of the first aspect, the semiconductor material used for epitaxially growing the vertical channel structure in step f) is a different semiconductor material than the material of the bottom source/drain portion.
The semiconductor material forming the vertical channel structure may be either monocrystalline, polycrystalline or amorphous.
Furthermore, the horizontal cross section of the vertical channel structure may for example be circular, square, hexagonal, rectangular, or triangular.
After growing the vertical channel structure, a step of planarization to reduce the height of the vertical channel structure is performed in step g). This step also reduces the height of the spacer material previously deposited in step c).
The planarization may for example be performed using chemical mechanical planarization (CMP).
In embodiments of the first aspect, the planarization of step g) reduces the spacer material to a targeted spacer thickness of the final vertical channel transistor structure.
Thus, the spacer material as deposited in step c) may form a final gate spacer in the vertical channel transistor structure.
However, as a complement or an alternative, in embodiments of the first aspect, step h) further comprises replacing the spacer material deposited in step c) with a lower-κ material.
Thus, the planarizing of step g) may include complete removal of the deposited spacer material of step c).
A lower κ-material may be a low-κ dielectric material having a dielectric constant that is less than 7.0. Exemplary low-κ dielectric materials that can be used include, but are not limited to, silicon oxide, boron nitride and silicon carbon boron nitride.
In embodiments of the first aspect, the gate is a dummy gate, and wherein the method further comprises a step of replacing the dummy gate with a final gate.
The dummy gate may comprise or consist of sacrificial gate portions. Consequently, the method may comprise a replacement gate process (RMG).
The dummy gate may include a dielectric material that can be selectively removed with respect to other structures of the vertical channel transistor structure. For example, the dummy gate may include a dielectric metal oxide or a dielectric oxide. As an example, the dummy gate may comprise silicon dioxide.
The replacement of a dummy gate with a final gate may be performed after step g).
However, it is also to be understood that the method may be a direct gate process, i.e. the gate material deposited in step b) may be the “real” gate metal of the final vertical channel transistor structure.
In embodiments of the first aspect, the bottom source/drain region has a width (w2) in a horizontal direction that is larger than the width of the gap, such that the vertical channel structure formed in step f) has a width (w1) in a horizontal direction that is equal to or smaller than the width (w2) of the bottom source/drain region.
As an example, the bottom source/drain region may have a width w2 at the interface between the bottom source/drain region and the channel region that is larger than the width of the gap.
As a second aspect of the disclosure, there is provided a vertical channel transistor device comprising
This aspect may generally present the same or corresponding advantages as the former aspect. Effects and features of this second aspect are largely analogous to those described above in connection with the first and second aspects. Embodiments mentioned in relation to the first aspects are largely compatible with the second aspect.
A vertical channel transistor device having a source/drain region with a width (w2) that is equal to or larger in a horizontal direction than the width (w1) of the channel structure may facilitate production of such a device, since it may compensate for any misalignment with any mask used in the process of forming the vertical channel structure, such as with a mask used for forming vertically extending portions around gate material as discussed in relation to the first aspect above.
If w2 is equal to or larger than w1, then the channel epitaxial growth may start at a full semiconductor surface, instead of at a mix of semiconductor/dielectric surface, as could be the case if w1>w2. Thus, having w2 equal to or larger than w1, facilitates a regular shape of the channel structure and a reliable production process.
In embodiments of the second aspect, the bottom source/drain region has a width (w2) that is larger in a horizontal direction than the width (w1) of the channel structure.
As an example, the width w2 may be larger than w1 in all horizontal directions. Thus, the cross-section of the channel structure may have an area that is confined in the area of cross-section of the bottom source/drain region, as seen in a plane parallel to the substrate. Thus, the bottom junction may enclose the vertical channel structure.
The vertical channel transistor device may be a field effect transistor (FET) device.
As an example, the width w2 may be larger than the width w1 in all horizontal directions.
In embodiments of the second aspect, the bottom source/drain region has a width (w2) that is equal to or larger in a horizontal direction than the width (w1) of the channel structure at the interface between the bottom source/drain region and the channel structure.
Thus, the vertically uppermost portion of the bottom source/drain region may have a width that is wider than the width of the vertical channel structure.
In embodiments of the second aspect, the channel structure is formed of a semiconductor material different from the material of the top and bottom source/drain regions.
As an example, the channel structure may be of a material selected from the group consisting of silicon, silicon germanium (SiGe), silicon carbide (SiC), Silicon carbon germanium (SiCGe), germanium (Ge) and group III-V compounds.
The bottom source/drain region may be selected from doped silicon, silicon germanium (SiGe), silicon carbide (SiC), Silicon carbon germanium (SiCGe), germanium (Ge) and group III-V compounds.
Furthermore, the gate may be a metal gate or a replacement gate.
In embodiments of the second aspect, the substrate is of a different material than the bottom source/drain region.
The substrate may be a semiconductor material, such as a single crystalline, polycrystalline or amorphous semiconductor material. As an example, the substrate may be single crystalline silicon. In one embodiment, the semiconductor substrate has a (111) crystalline orientation.
In embodiments of the second aspect, the gate surrounds the channel structure such that the vertical channel transistor device is configured as a gate-all-around field effect transistor.
Thus, the gate material may surround the vertical channel structure on all sides as seen in a horizontal cross-section through the device. The vertical channel structure may thus extend vertically through the gate.
The above, as well as additional objects, features and advantages of the present inventive concept, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.
In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.
The inventors have recognized a particular problem is existing technologies, namely that vertical channels, or vertical nanowires, may be sensitive to gate/channel overlay, which is may not be a problem in horizontal channel devices in which the channel is self-aligned to the gate. However, in a vertical channel device, the channel may not be self-aligned to the gate. As a result of such overlay, misalignment between the gate and channel may occur, and the resulting device characteristics can be degraded, as may be apparent from, e.g., Vth (threshold voltage) deviation if the gate overlap of the channel becomes too thin or even absent on one side of the vertical channel.
Vertical channels may be produced using two different process flows; channel-first, in which the channel is provided by etching, or channel-last, comprising embedded epi growth of the channel.
In U.S. Pat. No. 9,209,247, gate/channel misalignment is compensated by aligning the gate on the channel in a channel-first flow, such that protruding gate portions are used to compensate for any overlay. This solution creates additional parasitic capacitances that are degrading the speed of the semiconductor device.
Furthermore, US 2019/0081156 discloses a channel-first flow to obtain an aligned channel after a trimming operation.
A method according to embodiments comprises forming a bottom source/drain region 3a on the substrate surface 2 and depositing a spacer oxide layer 13 over the bottom source/drain region 3a.
The spacer oxide layer 13 may be provided by, e.g., conformal deposition. As an example, the spacer oxide layer 13 may include a low-k dielectric material having a dielectric constant k that is lower than that of silicon dioxide, such as boron nitride or silicon carbon boron nitride.
Further, an insulating material 12, e.g., a shallow trench isolation (STI) oxide, such as silicon dioxide is formed around the bottom source/drain region 3a, e.g., around the lateral sidewalls of the bottom source/drain region 3a. The bottom source/drain region 3a may have been performed by a straight etch at selected areas in the substrate 2 to provide a bottom source/drain portion 3a extending above the etched substrate 2, and followed by a deposition of isolation material 12 around the bottom source/drain portion 3a.
In some other embodiments, the substrate 2 may comprise or be formed of a different material from the bottom source/drain region 3a. In these embodiments, the bottom source/drain region 3a may have been formed by an epitaxial growth of a material different from the material of the substrate 2 on selected areas of the surface of the substrate 2.
Thereafter, as illustrated in
As discussed above, the gate material 4 is in this example deposited before the formation of the vertically extending portions. However, the structure as illustrated in FIG. 1 may be formed by first forming the vertically extending portions 5 and thereafter depositing spacer material over the bottom source/drain region 3a.
Furthermore, it is to be understood that the substrate 2, the bottom source drain region 3a, the gate material 4 and the vertically extending portions 5 may have other lateral/horizontal extension than that is shown. It may further be noted that the relative dimensions of the shown structures, for instance the relative thickness of layers, is merely schematic and may, for the purpose of illustrational clarity, differ from a physical device structure.
In
After the opening 8 has been formed, an oxide 10 is deposited using a conformal deposition process. This is illustrated in
The vertical channel structure 9 may then be epitaxially grown onto the exposed surface of the bottom source/drain region 3a such that the vertical channel structure extends within the opening 8 vertically above or beyond the gate material 4, as illustrated in
Consequently,
In some embodiments, the semiconductor material of the vertical channel structure 9 may be the same as the semiconductor material of the bottom source/drain region 3a. The material of the vertical channel structure may, e.g., be selected from the group consisting of silicon, silicon germanium (SiGe), silicon carbide (SiC), silicon carbon germanium (SiCGe), germanium (Ge) and group III-V compounds.
However, as an alternative, the vertical channel structure 9 may be formed of a semiconductor material different from the material of the bottom source/drain region 3a.
After epitaxial growth of the vertical channel structure 9, thus formed structure is planarized using, e.g., chemical-mechanical polishing (CMP), as illustrated in
In some other embodiments, however, the step (g) may also comprise replacing the spacer material 6 with a lower-κ material.
A lower κ-material may be a low-κ dielectric material having a dielectric constant that is less than 7.0. Exemplary low-κ dielectric materials that can be used include, but are not limited to, boron nitride and silicon carbon boron nitride.
The gate 4 formed as discussed in relation to
After the planarization of the step (g), a top source/drain region 3b is formed over the vertical channel structure 9. This is illustrated in
Consequently,
The bottom and top source/drain regions 3a, 3b may form source/drain terminals of the final vertical channel transistor structure 15. In an example, the bottom source/drain region 3a is formed by an n-doped selective epitaxial silicon or silicon carbon process, using for instance P, As or Sb as dopants, whereas the top source/drain region 3b is formed by a p-doped selective epitaxial silicon or silicon germanium process. In the latter example, B or Ga may be used as dopants.
However, as discussed herein above, also doped silicon carbide (SiC), silicon carbon germanium (SiCGe), germanium (Ge) and group III-V compounds may be used to form source/drain terminals of the final vertical channel transistor structure 15.
The structure as illustrated in
As an example, the width w2 may be larger than the width w1 in all horizontal directions.
Further, as also illustrated in
The resulting vertical channel transistor device me be refer gate-all-around (GAA). Thus, the gate region 4 may surround the channel structure 9 such that the vertical channel transistor device 15 is configured as a gate-all-around field effect transistor.
GAA devices may provide an improved control of the transistor device at a lower operating voltage.
Further, the vertical channel transistor device may comprise a gate contact (not shown) for providing means for controlling the gate 4 of the device 15.
| Number | Date | Country | Kind |
|---|---|---|---|
| 19207373.2 | Nov 2019 | EP | regional |
