The present invention relates to a vertical field effect transistor and a method for the formation thereof.
In conventional transistors (for example MOSFETs or MISFETs), the actively switchable components are provided by an inversion channel, for example, by the p-area in an npn-transition, in which an electron path is formed by applying a gate voltage. For the application of semiconductors including a wide band gap (for example silicon carbide (SiC) or gallium nitride (GaN)) in power electronics, the use of so-called power FinFETs (Fin=fin, FET=field effect transistor) may be advantageous. The structure of a conventional power FinFET 100 is illustrated in
An object of the present invention is to provide a vertical field effect transistor and a method for its manufacture, which provides a vertical field effect transistor having a higher electric strength and reliability. The object may be achieved according to one aspect of the present invention by a vertical field effect transistor. In accordance with an example embodiment of the present invention, the vertical field effect transistor includes: a drift area including a first conductivity type; a semiconductor fin on or above the drift area, a source/drain electrode being formed on or above the drift area laterally adjacent to at least one side wall of the semiconductor fin; and a shielding structure, which is situated laterally adjacent to the at least one side wall of the semiconductor fin in the drift area, the shielding structure including a second conductivity type, which differs from the first conductivity type. The semiconductor fin is electrically conductively connected to the source/drain electrode.
The shielding structure inside the drift area causes a change of the field distribution. The electrical field is increased at the p-n transitions of the vertical field effect transistor and thus decreases in the insulation underneath the gate metal. With the aid of the shielding structure, the electrical field may be reduced in particular in lockout mode in the insulation and displaced into the drift area. This enables the maximum field peaks reached to be reduced. A field effect transistor having higher electric strength and reliability may thus be provided.
The object may also achieved according to a further aspect of the present invention by a vertical field effect transistor. In accordance with an example embodiment of the present invention, the vertical field effect transistor includes: a drift area including a first conductivity type; a first semiconductor fin on or above the drift area; and a second semiconductor fin which is situated laterally adjacent to the first semiconductor fin on or above the drift area, a source/drain electrode being formed on or above the drift area laterally adjacent to at least one side wall of the first semiconductor fin; and a shielding structure, which is situated laterally adjacent to the at least one side wall of the first semiconductor fin; the shielding structure being situated in the second semiconductor fin; and the shielding structure including a second conductivity type, which differs from the first conductivity type, and the semiconductor fin being electrically conductively connected to the source/drain electrode.
The object may also be achieved according to a further aspect of the present invention by a method for forming a vertical field effect transistor. In accordance with an example embodiment of the present invention, the method includes: forming a drift area including a first conductivity type; forming a semiconductor fin on or above the drift area, a source/drain electrode being formed on or above the drift area laterally adjacent to at least one side wall of the semiconductor fin; and forming a shielding structure, which is situated laterally adjacent to the at least one side wall of the semiconductor fin in the drift area, the shielding structure including a second conductivity type, which differs from the first conductivity type, and the semiconductor fin being electrically conductively connected to the source/drain electrode.
Refinements of the aspects of the present invention are disclosed herein. Specific embodiments of the present invention are illustrated in the figures and are explained in greater detail hereinafter.
In the detailed description below, reference is made to the figures, which form a part of this description and in which specific exemplary embodiments are shown for illustration, in which the present invention may be implemented. Other exemplary embodiments may be used and structural or logical modifications may be carried out without departing from the scope of protection of the present invention. The features of the various exemplary embodiments described herein may be combined with one another if not specifically indicated otherwise. The following detailed description is therefore not to be interpreted restrictively. In the figures, identical or similar elements are provided with identical reference numerals, if appropriate.
In various specific embodiments, a vertical field effect transistor 200 includes a drift area 212 on a semiconductor substrate 216; a semiconductor fin 302 (the longitudinal direction of which extends perpendicularly to the plane of the drawing) on or above drift area 212, a shielding structure 214, a first source/drain electrode (for example, a source electrode 202), a second source/drain electrode (for example, a drain electrode 218). It is assumed by way of example hereinafter that first source/drain electrode 202 is a source electrode and second source/drain electrode 218 is a drain electrode. Vertical field effect transistor 200 furthermore includes a gate electrode 210 adjacent to at least one side wall of semiconductor fin 302, gate electrode 210 being electrically insulated with the aid of an insulation 206 from source electrode 202. A gate dielectric 208 is situated between gate electrode 210 and semiconductor fin 302. A highly-doped connection area 204 may electrically conductively connect semiconductor fin 302 to source electrode 202. Source electrode 202 may additionally be formed laterally adjacent to at least one side wall of semiconductor fin 302 on or above drift area 212. Shielding structure 214 is situated laterally adjacent to the at least one side wall of semiconductor fin 302 in drift area 212. Shielding structure 214 includes a second conductivity type which differs from the first conductivity type.
Semiconductor substrate 216 may be, for example, a GaN substrate 216 or a SiC substrate 216. Weakly n-conductive semiconductor drift area 212 (also referred to as drift zone 212) may be formed (for example applied) on semiconductor substrate 216, for example, a GaN or SiC drift area 212. Above drift area 212, an n-conductive semiconductor area may be formed in the form of semiconductor fin 302, for example, in the form of a GaN or SiC fin 302. An n+-conductive connection area 204 may be formed on semiconductor fin 302 or in an upper subsection of fin 302, with the aid of which source electrode 202 is contacted. Source electrode 202 may contact both shielding structure 214 and semiconductor fin 302. Drain electrode 218 may be located on the rear side of substrate 216.
With the aid of the introduction of shielding structure 214, for example, in the form of highly doped p-GaN or p-SiC areas in drift area 212, shielding the base of semiconductor fin 302 (the area between semiconductor fin 302 and drift area 212) is made possible. A space charge region may be formed during operation between the areas of shielding structure 214 and drift area 212. The area in which a current may flow may thus be reduced, due to which the resistance may be increased. Due to the introduction of shielding structure 214, the overall resistance of field effect transistor 200 is increased in comparison to the variant without shielding structure (
In
The lateral and vertical extension of shielding structure 212 and their doping level are directed specifically to the application according to the degree of shielding of the space charge region below the base of semiconductor fin 302. Gate electrode 210 does not have to be formed completely between two semiconductor fins 302 here, in contrast to the conventional Fin-FET (
In various specific embodiments, a shielding structure 214 is formed on each side of semiconductor fin 302. Shielding structure 214 may be formed in this case between two semiconductor fins 302 (
Shielding structure 214 may be enclosed completely by drift area 212 (see
In various specific embodiments, shielding structures 214 may be formed in adjacent semiconductor fins 302, which are not used as vertical field effect transistors (see, for example,
The trench structures (the area between two adjacent semiconductor fins 302), which contain shielding structures 214 in various specific embodiments, may have a greater lateral extension than the trenches between individual semiconductor fins 302. In another specific embodiment, shielding structures 214 may also be embedded deep in drift area 212, for example, completely enclosed by drift area 212 and spaced apart from the base of semiconductor fin 302. Buried shielding structures 214 may be electrically connected to source/drain electrode 202 at another point of the vertical field effect transistor. The formation of the connections of the vertical field effect transistor takes place, for example, in a super cell structure (not shown).
In various specific embodiments, shielding structure 214 includes an area situated in drift area 212, which extends laterally in the direction of semiconductor fin 302. In various specific embodiments, shielding structure 214 may adjoin the base of semiconductor fin 302, for example, touch it (not shown).
Shielding structure 214 may be electrically conductively connected to semiconductor fin 302 and drift area 212. In various specific embodiments, shielding structures 214 are electrically conductively connected to source/drain electrode 202 (see, for example,
In various specific embodiments having a plurality of semiconductor fins 302, the semiconductor fins may have different widths. As an example, a (second) semiconductor fin with embedded shielding structure 214 may be formed wider than a (first) semiconductor fin without shielding structure.
In various specific embodiments, buried shielding structures 214 of the second conductivity type may be combined with additional areas 312 of the first conductivity type (see, for example,
In various specific embodiments, the semiconductor fin may be formed column-shaped, for example, spatially delimited in all spatial directions. In other words: the semiconductor fin may be a semiconductor column in various specific embodiments. The semiconductor column may have a square, rectangular, round, or hexagonal cross section of the column.
In various specific embodiments, the semiconductor fin may be formed having nonrectangular side walls, for example conical or pyramidal. The shielding structures shown above are also applicable to these structural variants. The buried shielding structures may be formed both in parallel and also perpendicularly and also at any arbitrary angle relatively laterally to the semiconductor fins.
Shielding structures 214 may be formed, for example, with the aid of ion implantation, for example, using aluminum ion implantation in the case of a SiC semiconductor fin or a SiC drift area or using magnesium ions in the case of a GaN semiconductor fin or a GaN drift area. To provide shielding structures embedded deep in the drift area without high-energy ion implantation, an additional trench 310 may be provided, in whose base the implantation takes place (see, for example,
In various specific embodiments, the shielding structures may be designed with the aid of so-called dead implantation. The shielding structures are designed by implanting an ion species, for example, argon ions, which does not cause doping in the SiC or GaN drift area. These shielding structures are no longer electrically conductive. Correspondingly, their shielding effect is retained, but they may no longer be used as the body diode for the reverse operation. Connecting such electrically nonconductive shielding structures to the source electrode is optional.
The specific embodiments described and shown in the figures are only selected as examples. Different specific embodiments may be combined with one another completely or with respect to individual features. One specific embodiment may also be supplemented by features of another specific embodiment.
Furthermore, described method steps may be carried out repeatedly and in a sequence other than that described. In particular, the present invention is not restricted to the specified method.
Number | Date | Country | Kind |
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10 2019 216 138.3 | Oct 2019 | DE | national |
Filing Document | Filing Date | Country | Kind |
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PCT/EP2020/076293 | 9/21/2020 | WO |