Patent Application
20240105617
Embodiments described herein relate to power and signal routing for semiconductor devices. More particularly, embodiments described herein relate to power and signal routing through both topside and backside layers for integrated circuit cells with vertical transistors.
Standard cells are groups of transistors, passive structures, and interconnect structures that can provide logic functions, storage functions, etc. Current trends in standard cell methodology are towards reducing the size of standard cells while increasing the complexity (e.g., circuit density and number of components or transistors) within standard cells. As standard cell designs become smaller, however, it becomes more difficult to provide access (e.g., connections) to components within the standard cells and within design/manufacturing constraints of standard cells.
Features and advantages of the methods and apparatus of the embodiments described in this disclosure will be more fully appreciated by reference to the following detailed description of presently preferred but nonetheless illustrative embodiments in accordance with the embodiments described in this disclosure when taken in conjunction with the accompanying drawings in which:
Although the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described herein in detail. It should be understood, however, that drawings and detailed description thereto are not intended to limit the scope of the claims to the particular forms disclosed. On the contrary, this application is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the disclosure of the present application as defined by the appended claims.
As used herein, the term “standard cell” refers to a group of transistor structures, passive structures, and interconnect structures formed on a substrate to provide logic or storage functions that are standard for a variety of implementations. For example, an individual standard cell may be one cell in a library of multiple cells from which various suitable cells may be selected to implement a specific cell design. Integrated circuit cells may also include custom circuit design cells that are individually designed for a particular implementation. Embodiments of circuit design cells described herein may be implemented in various implementations of logic integrated circuits or memory integrated circuits.
Many current designs of cells provide connections and routing for power or signals to transistors or other structures in areas above the transistors. For example, the connections and routing for power or signals may be provided in topside layers of the device. As used herein, the term “topside” refers to areas in a device that are vertically above an active layer of the device (e.g., above a transistor region of the device when viewed in a typical cross-sectional view). For example, topside may refer to components such as contacts or layers that are above a transistor region in a vertical dimension, as depicted in the figures and described herein. In some instances, the term “frontside” may be used interchangeably with the term “topside”.
Some recent developments for designs of standard cells move connections and routing for power connections to metal layers below the transistors. For example, the connections and routing for power may be provided in the backside layers of the device. As used herein, the term “backside” refers to areas in a device that are vertically below an active layer of the device (e.g., below a transistor region of the device when viewed in a typical cross-sectional view). For example, backside may refer to components such as contacts or layers that are below a transistor region in a vertical dimension, as depicted in the figures and described herein. It is noted that as used herein, backside elements located below an active layer may be situated above, within, or below a silicon substrate on which the active layer is manufactured. That is, as used herein, “backside” is relative to the active layer, rather than the silicon substrate.
The present disclosure is directed to various implementations of stacked transistors or vertical transistors in integrated circuit cells (e.g., standard cells) that utilize connections to both topside metal layers and backside metal layers. The present inventors have recognized that topside and backside layers can be utilized in specific ways to provide technical and space saving advantages for cell layouts implementing stacked transistors or vertical transistors. The disclosed embodiments implement topside and backside metal layers to provide advantageous cell layouts and routing (e.g., paths) for control signals or power signals within the cell layouts.
Stacked transistors (e.g., where two transistor active regions are stacked vertically above a substrate) may provide various technical and space saving advantages due to the proximity of devices in the transistors. The implementation of stacked transistors in a standard cell, however, is challenging due to design and manufacturing constraints associated with standard cell construction. For example, in standard cells that utilize only topside routing, there are typically not enough paths for routing to both transistors without expanding the size of the standard cell. Standard cells that are limited to topside routing for control signals and backside routing for power signals may also lack the necessary routing and connection availability for two stacked transistors without changes to the size of the standard cell.
The present disclosure contemplates various techniques that implement routing in both topside and backside metal layers that allow two stacked transistors to be placed in a standard cell. Various embodiments of standard cell constructions are disclosed that provide basic building blocks for many different types of devices from simple devices (e.g., inverters and NAND devices) to more complex devices (e.g., complex FETs). The disclosed embodiments provide a compact standard cell construction that allows for the implementation of stacked transistors in various circuit logic schemes.
Certain embodiments disclosed herein have four broad elements: 1) a first metal layer located above a transistor region of an integrated circuit cell structure (e.g., a topside metal layer); 2) a second metal layer located below the transistor region (e.g., a backside metal layer), 3) a pair of vertically stacked transistors in the transistor region, and 4) various possible connection paths for both control signals and power signals between either the first or second metal layers and the first and second transistors. In certain embodiments, the pair of vertically stacked transistors includes heterogeneous transistors (e.g., complementary transistor types such as PMOS and NMOS transistors). In some embodiments, the pair of vertically stacked transistors includes homogeneous transistors (e.g., the transistors are of the same type).
In various embodiments, the control signal and power signal connections are made to implement logic associated with specific integrated circuit devices having multiple transistors for the standard cell constructions described herein. For instance, examples of an inverter device or a NAND gate device that may be implemented based on the standard cell construction are described below. Embodiments of various possible connections for control signals and voltage signals to the stacked transistors within the standard cell construction are also described. A person with knowledge in the art would understand that combinations of these various possible connections may be implemented to generate many different desired circuits based on the stacked transistor structure within the standard cell construction.
In short, the present inventors have recognized that providing various routing paths within a standard cell construction allows the implementation of connections to both topside and backside metal layers for control signals and power signals from stacked transistors positioned within the standard cell construction. The routing paths described herein enable standard cell constructions to be utilized in generating a variety of both simple and complex integrated circuit logic devices based on the stacked transistors within the cells. Additionally, the standard cell construction with stacked transistors described herein provides a scalable template that can be implemented in devices having multiple integrated circuit cells. The standard cell construction with stacked transistors within the present disclosure further enables constructions of cells that can be implemented within current manufacturing constraints and without changes to the size or parameters of current standard cells. As used herein, the term “routing” refers to any combination of metal vias, metal wires, metal traces, etc. that provide a path/route between two structures. Additional embodiments may be contemplated where the metal in “routing” is replaced with an alternative conductive material. For instance, the metal in “routing” may be replaced with a superconductor material, a semiconductor material, or a non-metal conductor.
For simplicity in the drawings, only components relevant to the disclosure are shown in the representations of a cell disclosed herein. A person with knowledge in the art would understand that additional components may be present in any of the cells depicted herein. For instance, in
In various embodiments, as shown in
In various embodiments, first active region 104 and second active region 106 are formed in substrate 102. In certain embodiments, active region 104 is positioned vertically above active region 106 in cell 100. For example, active region 104 may be positioned in an upper portion of cell 100 with active region 106 in a lower portion of the cell. It should be noted that active region 104 and active region 106 may not necessarily be positioned directly above/beneath each other. For instance, some portions of active region 104 or active region 106 may be outside the boundaries of the other active region. Thus, when describing that active region 104 is above active region 106, it may be referencing that at least some portion of active region 104 is above at least some portion of active region 106, or vice versa.
In certain embodiments, active region 104 is an active region of a first transistor in cell 100 and active region 106 is an active region of a second transistor in the cell. For example, in one contemplated embodiment, active region 104 is the active region of an NMOS transistor with one or more NMOS gates and active region 106 is the active region of a PMOS transistor with one or more PMOS gates. Alternatively, active region 104 may be the active region of a PMOS transistor while active region 106 is the active region of an NMOS transistor. While transistor stacks with these complementary transistor types (e.g., heterogeneous transistors) are described with respect to
In various embodiments, transistors with active region 104 include upper gates 108 and source/drain regions 124 while transistors with active region 106 include lower gates 116 and source/drain regions 124. The transistors may be positioned between isolation gates 110, as shown in
Upper gates 108 and lower gates 116, may be, for example, poly lines (e.g., polysilicon layers) or high-k/metal gates. In certain embodiments, upper gates 108 and lower gates 116 include gate spacers (not shown for simplicity in the drawing). For instance, gate spacers may be positioned between gates 108/116 and source/drain regions 124. In various embodiments, the gate spacers are formed as parts of gates 108/116 (e.g., the gates and spacers are formed in the same process flow). Source/drain regions 124 may be, for example, epitaxial layers grown on fins or nanosheet stacks or any 2D (two-dimensional) channel materials. Various embodiments may also be contemplated where source/drain regions 124 are at least partially positioned in substrate 102.
In addition to the above-described transistor components, various connections to gates and/or source/drain regions may be made within cell 100. The connections may include, for example, contacts or vias that provide connection between transistor components in cell 100 and topside metal layers 112 or backside metal layers 120. Contact 114 (shown in
In various embodiments, contacts 114 are topside vias that provide connection to topside metal layers 112 from various portions of the transistors (e.g., source/drain regions, gates, etc.) while backside vias 122 provide connection to backside metal layers from various portions of the transistors. Contacts 114 and backside vias 122 are provided as non-limiting examples of connections possible in cell 100. For instance, any number or combination of contacts or vias (along with any horizontal routing) may be implemented in cell 100 to provide connections between various topside metal layers and backside metal layers and transistor components (e.g., upper gates 108, lower gates 116, and source/drain regions 124) within the cell. Connections may also be made depending on whether control signals or power signals are intended for components within the transistors of cell 100. For example, in the embodiment depicted in
As shown in
In various embodiments, as shown in
Metal tracks also may be selected for use as control signal tracks (e.g., control signal rails) or power signal tracks (e.g., power signal rails) based on the desired device usage of cell 100. Control signal tracks may provide input or output signal connections to transistor components in cell 100 while power signal tracks may provide power routing to/from Vdd (e.g., the supply voltage) and Vss (e.g., ground) as well as other contemplated power supply connections. The selection of a track for use as a control signal track or power signal track may also determine connections made to the metal track. For instance, in the depicted embodiment of cell 100, topside metal layer 112B is a control signal track connected to upper gate 108A by contact 114 while backside metal layer 120B is a power signal track connected to source/drain region 124F by backside via 122. It should be noted that any of backside metal layers 120A-C may be used as a power signal track in various contemplated embodiments. The remaining topside metal tracks (e.g., topside metal layers 112A, 112C, 112D) may be used for either additional topside control signal tracks or topside power signal tracks. Similarly, the remaining backside metal tracks (e.g., backside metal layers 120A and 120C) may be used for either additional backside power signal tracks or backside control signal tracks. For instance, in one contemplated embodiment, one of topside metal layers 112A, 112C, 112D may be a topside power signal track that has a contact to a source/drain region in the upper portion of cell 100 (e.g., one of source/drain region 124A-C) to provide a power signal connection to the upper transistor with active region 104. Additionally, one of backside metal layers 120A and 120C may be a backside control signal track that has a contact to lower gate 116B (e.g., the lower gate in the split gate configuration) in the lower portion of cell 100 to provide a control signal connection to the lower transistor with active region 106.
In various contemplated embodiments, one or more topside metal tracks (e.g. topside metal layers 112A-D) may be merged to when the metal tracks are being used as power rails (e.g., power signal tracks). For instance, in some embodiments, when a metal track along the cell edge (e.g., topside metal layer 112A or topside metal layer 112D) is used as a power rail, the metal track may be merged with the metal cell track from the neighboring cell. For example, as shown in
In other contemplated embodiments for merging of metal tracks, metal tracks at or near a center of a cell that are used as power rails may be merged. For instance, as shown in
It should be noted that in the embodiment of cell 100 depicted in
As shown in
While not shown in
In certain embodiments, power routing for the transistors in cell 100 (e.g., the upper transistor and the lower transistor) is divided between the topside metal layers 112 and the backside metal layers 120. For instance, as shown in
Additional embodiments may be contemplated where power routing is provided from one or the other of the topside metal layers 112 and the backside metal layers 120 but not both layers. For instance, as discussed above, the source/drain regions could be merged and a single power signal from either the topside or backside could be provided to the merged regions. In another contemplated embodiment, power may be brought into cell 100 through a backside metal layer (such as backside metal layer 120A) and a via could route power from the backside metal layer to one of the topside metal layers, which then connects to a source/drain region in the upper transistor. The via could be positioned in an open channel in cell 100 between topside metal layers and backside metal layers. One example of a via is shown in
Yet another alternative for routing power from backside layers to the upper could include extending source/drain region 124C to intersect and connect with via 600, as shown by the dotted lines extending from source/drain region 124C in
As discussed above, the embodiment of cell 100 depicted in
In some instances, placing cell 100 next to neighboring cells may cause manufacturing issues due to routing tracks along the boundaries of the cells. With the routing tracks along the boundaries, vias from the routing tracks may create spacing issues between the neighboring cells. One possible solution to this boundary problem is to replace the routing tracks along the edges with via tracks where the vias alternate between being used by the current cell and the neighboring cell.
Various embodiments for connecting to via pillars 710A within cell 700, shown in
In various embodiments, as shown in
Via pillars 710A may also provide routing for control signals from gates in various embodiments of stacked transistors. The gates may, for example, be coupled to as common gates or split gates (e.g., as used in transmission gates).
In certain embodiments,
In the illustrated embodiment, as shown in
In various embodiments, as shown in
Contact 114B, shown in
In the contemplated embodiment of NAND cell 1300, the upper gates and lower gates are merged. For instance, as shown in
In various embodiments, NAND cell 1300 includes backside via 122A and backside via 122C, shown in
In certain embodiments, NAND cell 1300 includes via 1302A and via 1302B. Via 1302A and via 1302B are top-to-back vias that connect upper contact 126C to lower contact 126F, as shown in
NAND cell 1300 further includes backside via 122B, shown in
In various embodiments, stacked transistors, such as those described herein, may be implemented in memory cells such as SRAM cells.
With inverter 1710A, inverter 1710B, pass gate 1720, and pass gate 1722, cell 1700 includes six transistors—two in each of the inverters and one in each of the pass gates. In certain embodiments, the inverters 1710 include two complementary transistors—for example, each inverter includes an NMOS transistor and a PMOS transistor. Pass gates 1720, 1722 may be transistors of the same type. In one embodiment, both pass gates are NMOS transistors. Thus, in various embodiments, cell 1700 includes four NMOS transistors and two PMOS transistors.
The present disclosure contemplates various techniques that implement stacked transistors in a memory cell. For instance, stacked transistors, such as those described above, may be implemented in the 6T SRAM memory cell shown in
Certain embodiments disclosed herein have five broad elements: 1) a first transistor region with first and second active regions in parallel; 2) a second transistor region with third and fourth active regions in parallel where the second transistor region is positioned vertically below the first transistor region, 3) a first inverter formed by a transistor in the first active region and a transistor in the third active region, 4) a second inverter formed by a transistor in the second active region and a transistor in the fourth active region, and 5) a cross-coupling between the first inverter and the second inverter. In certain embodiments, the source/drain regions in the inverters are merged. For instance, the source/drain regions on opposite sides of the gates of the two transistors in the first inverter may be merged. In certain embodiments, the cross-coupling is achieved by coupling a horizontally extended portion of the gate for the transistor in the third active region with a source/drain region of the transistor in the fourth active region and coupling a horizontally extended portion of the gate for the transistor in the fourth active region with a source/drain region of the transistor in the third active region.
In various embodiments, the horizontally extended portions of the gates for cross-coupling are portions that extend towards and possibly into the other active region (e.g., the gate for the transistor in the third active region has a portion extending into the fourth active region). Extending the gates as described herein allows the cross-couple connections to be made in areas of the cell vertically below the active regions of the memory cell. The cross-couplings may also be positioned vertically above any backside layer routing. This area is available for cross-coupling by removing material in inactive portions of the third and fourth active regions.
In short, the present inventors have recognized that stacked transistors may be implemented in a memory cell along with the removal of material for inactive portions of active regions to enable cross-coupling of inverters formed by the transistors in the memory cell. The cross-coupling of the inverters in the areas intended for inactive portions provides a memory cell construction that maintains current design philosophies while also reducing the cell height versus typical memory cells. The cell height may be reduced as the utilization of the cross-coupling in an area below the active regions allows the active regions to be vertically positioned closer together. Minimizing the vertical spacing between the active regions accordingly allows reduction in the overall height of the memory cell.
For simplicity in the drawings, only components relevant to the disclosure are shown in the representations of a cell disclosed herein. A person with knowledge in the art would understand that additional components may be present in any of the cells depicted herein. For instance, in
In the illustrated embodiments, cell 1800 includes two upper active regions 1810, 1820 (shown in
Upper active region 1810 is separated from upper active region 1820 by a diffusion to diffusion spacing distance 1815. Similarly, lower active region 1830 is separated from lower active region 1840 by a diffusion to diffusion spacing distance 1835. In some embodiments, distance 1815 and distance 1835 are substantially the same distances.
In the illustrated embodiments, upper active region 1810 includes upper gate 1812 between source/drain region 1814A and source/drain region 1814B and upper gate 1816 between source/drain region 1814B and source/drain region 1814C. Upper active region 1820 includes upper gate 1822 between source/drain region 1824A and source/drain region 1824B and upper gate 1826 between source/drain region 1824B and source/drain region 1824C. Upper gates 1812, 1816, 1822, 1826 may be poly gates or other types of gates for FET transistor devices. In one embodiment, upper gates 1812, 1816, 1822, 1826 are NMOS gates.
In certain embodiments, upper gate 1812 is separated from upper gate 1822 and upper gate 1816 is separated from upper gate 1826. For instance, the poly for upper gate 1812 is not connected to the poly for upper gate 1822. Similarly, the poly for upper gate 1816 is not connected to the poly for upper gate 1826. The upper gates may be separated by either cutting the poly between the upper gates (e.g., cutting the poly between upper active region 1810 and upper active region 1820) or forming the upper gates from separate poly layers in upper active region 1810 and upper active region 1820. Separation of the upper gates between upper active region 1810 and upper active region 1820 provides distinction between transistors formed by these upper gates to allow the upper gates to form transistors for inverters and pass gates, as described herein.
In the illustrated embodiments, lower active region 1830 includes lower gate 1832 between source/drain region 1834A and source/drain region 1834B. Lower active region 1840 includes lower gate 1846 between source/drain region 1844B and source/drain region 1844C. It should be noted that there are only two gate regions in the lower active regions 1830, 1840 due to the presence of inactive portions 1833, 1842 and as only two transistors are needed in combination with the four transistors in the upper active regions in order to form a memory cell device. Lower gates 1832, 1846 may be poly gates or other types of gates for FET transistor devices. In one embodiment, lower gates 1832, 1846 are PMOS gates.
In certain embodiments, as shown in
An example embodiment of a 6T (six-transistor) SRAM memory cell that may be implemented in cell 1800 is now described with respect to the various connections made within the cell to implement the six transistors (e.g., four NMOS transistors and two PMOS transistors) that are arranged as inverters and pass gates. It should be understood that various additional embodiments of memory cells may be contemplated based on the disclosed structure of cell 1800. As shown in
Turning back to cell 1800, upper gate 1812 along with source/drain region 1814A and source/drain region 1814B, shown in
Additionally for transistor 1850 and transistor 1852, source/drain region 1814B is merged with source/drain region 1834B by S/D merge 1860B (as shown in
Inverter 1710B, shown in
To form inverter 1710B with transistor 1854 and transistor 1856, source/drain region 1824B is merged with source/drain region 1844B by S/D merge 1860C (also shown in
In various embodiments, cell 1800 provides availability for forming pass gate 1720 and pass gate 1722 in addition to the inverters 1710A, 1710B. For instance, pass gate 1720 may be formed with third NMOS transistor 1858 while pass gate 1722 is formed with fourth NMOS transistor 1859, as shown in
Both upper gate 1816 and upper gate 1822 may be coupled to a wordline (e.g. wordline 1730) for the transmission of control signals to the gates. A read/write data connection to a bitline (e.g., bitline 1742) for upper gate 1816 may be provided through source/drain region 1814C while a read/write data connection to a bitline (e.g., bitline 1740) for upper gate 1822 may be provided through source/drain region 1824A. The output of transistor 1859 (which corresponds to pass gate 1722) is provided through source/drain region 1814B, which is also the output of transistor 1850 and merged with the output of transistor 1852 in inverter 1710A. Correspondingly, the output of transistor 1858 (which corresponds to pass gate 1720) is provided through source/drain region 1824B, which is also the output of transistor 1854 and merged with the output of transistor 1856 in inverter 1710B. Thus, transistors 1858, 1859 provide pass gate transistors 1720, 1722 that are coupled to inverter 1710A and inverter 1710B according to the schematic diagram of
As discussed above, in certain embodiments, lower gate 1832 (in transistor 1852 of inverter 1710A) and lower gate 1846 (in transistor 1856 of inverter 1710B) extend towards the inactive portions of the active regions of the opposite transistor region. These extensions provide capability for providing cross-coupling between the inverters below the active regions of cell 1800. For example, as shown in
PMOS transistor gate in inverter 1710A) and source/drain region 1844B (which is the merged PMOS source/drain region in inverter 1710B). Thus, cross-coupling 1864B cross-couples the input of inverter 1710A and the output of inverter 1710B. Similarly, cross-coupling 1864A, shown in
In certain embodiments, cross-couplings 1864A, 1864B are positioned below the active regions and above backside metal layers 120 in cell 1800. For example, as shown in
In various embodiments, in addition to being implemented in memory cells such as SRAM cells (e.g., SRAM bit cells), stacked transistors, such as those described herein, may be implemented in periphery cells associated with SRAM cells. For instance, the present disclosure contemplates various techniques that implement column input/output logic cells that include the stacked transistors. Implementation of stacked transistors in periphery cells, such as column input/output logic cells, may allow utilization of both topside and backside routing in a memory device containing various types of SRAM cells, including the various embodiments of SRAM cells described herein.
Certain embodiments disclosed herein have four broad elements: 1) a plurality of bit cells formed in first and second transistor regions that are vertically disposed relative to each other; 2) a first metal layer located above the bit cells (e.g., a topside metal layer) and a second metal layer located below the bit cells (e.g., a backside metal layer), 3) a first column input/output logic cell coupled a first array of bit cells, and 4) a second column input/output logic cell coupled a second array of bit cells where the second array of bit cells is closer to the logic cells than the first array of bit cells. In certain embodiments, the first metal layer includes first routing that couples the first array of bit cells to the first column input/output logic cell while the second metal layer includes second routing that couples the second array of bit cells to the second column input/output logic cell. In some embodiments, the column input/output logic cells implement stacked transistors, such as those described herein.
Accordingly, in various embodiments, the first column input/output logic cell provides column I/O logic for bit cells that are further away from the periphery region of the device while the second column input/output logic cell provides column I/O logic for bit cells that are closer to the periphery region of the device. Splitting the routing between the topside and backside metal layers reduces routing congestion compared to utilization of only topside or backside routing for routing logic in a memory device. In various embodiments, dummy cells may be utilized for localized routing of bitline signals between topside and backside metal layers. For instance, dummy cells may be utilized for localized routing near bit cells of the first array (e.g., bit cells far away from the logic cells).
In short, the present inventors have recognized that routing for column I/O logic in both topside metal layers and backside metal layers can be utilized in a memory device to relieve metal congestion in the memory device. Additionally, various techniques are implemented to reduce any area penalties associated with front to back transitions (or vice versa) when both topside metal layers and backside metal layers are used for routing logic between bit cells and logic cells. In some embodiments, the various routing paths provide reduced resistance paths for logic within a memory device. With implementation of the various disclosed techniques, the disclosed embodiments of a memory device may have strong signal connectivity with improved read/write speeds and thus improved performance.
In various embodiments, logic circuit cell region 2320 includes multiple column input/output (I/O) logic cells 2322. Column I/O cells 2322 may, for instance, manage read/writes from bit cell arrays 2312. Column I/O cells 2322 may also include portions of sense amplifiers. It should be understood that logic circuit cell region 2320 may include other logic cells in addition to column input/output (I/O) logic cells 2322. For instance, logic circuit cell region 2320 may also include power switch logic cells, wordline logic circuit cells, local I/O circuit cells, global I/O circuit cells, etc. In some embodiments, logic circuit cell region 2320 may be referred to as a periphery region of memory device 2300.
In a contemplated embodiment, logic circuit cell region 2320 includes individual column I/O logic cells 2322 for each bit cell array in memory cell region 2310. For instance, in the illustrated embodiment, logic circuit cell region 2320 includes first column I/O logic cell 2322A and second column I/O logic cell 2322B as memory cell region 2310 has two bit cell arrays 2312A, 2312B.
In various embodiments, first column I/O logic cell 2322A provides column I/O logic for far bit cell array 2312A and second column I/O logic cell 2322B provides column I/O logic for near bit cell array 2312B. Routing in both topside metal layers 112 and backside metal layers 120 may be utilized in memory device 2300 to relieve metal congestion in the memory device. The present disclosure contemplates routing methods that also reduce any front to back transition area penalty in the utilization of both topside metal layers 112 and backside metal layers 120 in routing logic between bit cells and logic cells.
In certain embodiments, memory device 2300 utilizes both topside metal layers 112 and backside metal layers 120 for bitline routing in the memory device. For example, topside metal layers 112 may be utilized for bitline routing between near bit cell array 2312B and second column I/O logic cell 2322B and backside metal layers 120 may be utilized for bitline routing between far bit cell array 2312A and first column I/O logic cell 2322A. In the illustrated embodiment, bitlines 1740A and bitlines 1742A provide bitline routing in far bit cell array 2312A and bitlines 1740B and bitlines 1742B provide bitline routing in near bit cell array 2312B. Bitlines 1740 and bitlines 1742 may be, as described herein, complementary bitlines.
As shown in
In certain embodiments, dummy cells 2340A, 2340B are positioned at or near bitline outputs 2314A, 2316A, respectively. Dummy cell 2340A includes a connection between bitline 1740A in topside metal layers 112 and backside bitline routing 2330 in backside metal layers 120. Dummy cell 2340B includes a connection between bitline 1742A in topside metal layers 112 and backside bitline routing 2332 in backside metal layers 120.
In various embodiments, as shown in
In certain embodiments, dummy cells 2340A, 2340B include trench metal 2420 formed between bitline 1740A and backside bitline routing 2330 and between bitline 1742A and backside bitline routing 2332, as shown in
The use of trench metals 2420 for the connection between bitlines 1740A, 1742A and backside bitline routings 2330, 2332 provides a low electrical resistance path for bitline signals to transition from topside metal layers 112 to backside metal layers 120. Dummy cells 2340 provide localized traffic management for bitline signals at or near far bit cell array 2312A. While dummy cells 2340 have some area penalty in memory device 2300, the area penalty is small as the dummy cells are localized to shallow metal layers and are not associated with any global routing.
Turning back to
Turning now to near bit cell array 2312B, bitline 1740B and bitline 1742B are coupled to bitline output 2314B and bitline output 2316B, respectively. Bitline output 2314B and bitline output 2316B are then coupled to topside bitline routing 2334 and topside bitline routing 2336, respectively. Since both bitlines 1740B, 1742B and topside bitline routings 2334, 2336 are located in topside metal layers 112, no transition between the topside metal layers and backside metal layers 120 is needed at near bit cell array 2312B.
In the illustrated embodiment, topside bitline routing 2334 and topside bitline routing 2336 carry bitline signals from near bit cell array 2312B to bitline input 2324B and bitline input 2326B, respectively, at second column I/O cell 2322B. As noted above and described below, bitline input 2324B and bitline input 2326B are positioned in backside metal layers 120. Accordingly, a transition from topside metal layers 112 to backside metal layers 120 may be needed at bitline input 2324B and bitline input 2326B.
In certain embodiments, dummy cell 2350 is positioned at or near bitline inputs 2324B, 2326B. Dummy cell 2350 includes a connection between topside bitline routing 2334 in topside metal layers 112 and bitline input 2324B in backside metal layers 120 and a connection between topside bitline routing 2336 in topside metal layers 112 and bitline input 2326B in backside metal layers 120.
In various embodiments, as shown in
In certain embodiments, dummy cell 2350 includes trench metal 2820 formed between topside bitline routing 2334 and bitline input 2324B and between topside bitline routing 2336 and bitline input 2326B, as shown in
Similar to dummy cells 2340, the use of trench metals 2820 for the connection between topside bitline routings 2334, 2336 and backside bitline inputs 2324B, 2326B provides a low electrical resistance path for bitline signals to transition from topside metal layers 112 to backside metal layers 120. Dummy cells 2350 provide localized traffic management for bitline signals in logic circuit cell region 2320 (e.g., in the periphery region).
Turning back to
In various embodiments, column I/O cells 2322 may implement stacked transistors to provide connectivity to the various routings described above for memory device 2300.
As shown in
In certain embodiments, the transistors in cell 2322 may be formed by a stacked transistor as described herein. For example, the PMOS transistors are formed in a lower transistor region and the NMOS transistors are formed in an upper transistor region.
In the illustrated embodiment of upper transistor region 3300 in
In the illustrated embodiment of lower transistor region 3350 in
Vias 3322 connect gate 3212, gate 3222, and gate 3232 by PCH 3204. Vias 3322 also connect gate 3242 and 3252 using Rcs 3206. More vias 3322 connect source/drain region 3244B to sense output 3282A and source/drain region 3254B to sense output 3282B. Yet more vias 3322 connect source/drain region 3214B and source/drain region 3244A to bitline input 2324 and source/drain region 3214C and source/drain region 3254A to bitline input 2326. Vdd is connected to source/drain region 3214A and source/drain region 3214D by additional vias 3322.
In some embodiments, source/drain region 3214B in lower transistor region 3350 is merged with source/drain region 3264B in upper transistor region 3300 by source/drain merge 3290A. Additionally, source/drain region 3254A may be merged with source/drain region 3274C by source/drain merge 3290B. Merging of these source/drain regions provides necessary connections between NMOS transistors and PMOS transistors.
The embodiment of memory device 2300 described herein provides a memory device that may provide strong signal connectivity using current layout techniques without significant area penalties. Routing in memory device 2300 utilizes bitline routing through topside and backside metal layers to avoid metal routing congestion in the device. Memory device 2300 also avoids typical complexities involved with unipolar device fabrication utilizing the various routing paths and connection paths described herein. The various connection paths described herein may also reduce resistance within memory device 2300 and thus improve read/writing speeds and the performance of the memory device.
A recent development in transistor design is the implementation of vertical transistors where the cells have vertical transport through vertically displaced source/drain regions and a gate positioned vertically in between the source/drain regions. Current vertical transistor designs typically include wide frontside (e.g., topside) power rails at the boundaries of the cell for power delivery. These wide power rails, however, contribute to an increased and large standard cell height. The larger standard cell height reduces the area efficiency of the vertical transistor while also reducing available connectivity and performance of the transistor.
The present disclosure contemplates various embodiments that utilize backside power routing in vertical transistor designs to reduce scaling, provide better connectivity, and provide better performance of the transistors. Certain embodiments disclosed herein have four broad elements: 1) a pair of vertical transistors in an integrated circuit cell; 2) a topside metal layers above the transistor regions of the vertical transistors with signal routing, 3) a backside metal layer below the transistor regions with power routing, and 4) a metal contact layer between the backside metal layer and source/drain regions of the transistors. In certain embodiments, the transistors are complementary transistors. In some embodiments, vias couple power routing in the backside metal layer to the metal contact layer. In some embodiments, a second pair of vertical transistors may be included in the cell. Additional implementations of gate vias, fins, contact vias, and various other connections and routings may also be contemplated in various embodiments.
In various embodiments, control signal and power signal connections are made using various contacts or vias to implement logic associated with specific integrated circuit devices having multiple vertical transistors for the cell constructions described herein. For instance, examples of an inverter device, a NAND device, and a MUX device that may be implemented based on the vertical transistor cell construction are described below. Embodiments of various possible connections for control signals and voltage signals to the vertical transistors within the cell constructions are also described. A person with knowledge in the art would understand that combinations of these various possible connections may be implemented to generate many different desired circuits based on the vertical transistor structure within the cell constructions disclosed herein.
In short, the present inventors have recognized that the implementation of backside routing for power connections in combination with vertical transistors provides various opportunities for construction of specific transistor designs with reduced scaling. Additionally, various techniques are implemented to provide specific routing for control signal and power routing within the cell constructions with vertical transistors described herein. With implementation of the various disclosed techniques, vertical transistor cell constructions that provide improved performance in a small scale factor are contemplated.
In the illustrated embodiment of
As depicted in
In certain embodiments, transistor 3410 includes upper contact 3418 coupled to upper source/drain region 3416 and transistor 3420 includes upper contact 3428 coupled to upper source/drain region 3426. Contact 3418 and contact 3428 may be, for example, metal contacts for contacting various resources in a first metal layer positioned above transistor 3410 and transistor 3420. For example, as shown in
In various embodiments, transistor 3410 includes lower contact 3419 coupled to lower source/drain region 3412 and transistor 3420 includes lower contact 3429 coupled to lower source/drain region 3422. Contacts 3419, 3429 may be, for example, metal contacts. Contacts 3419, 3429 may be utilized to route to backside power routing layers (e.g., backside power routing 3440A or backside power routing 3440B, as shown in
In certain embodiments, device 3400 includes a backside power layer. In the illustrated embodiment of
In various embodiments, gate 3414 and gate 3424 are interconnected by gate bridge 3450. Gate bridge 3450 may be formed, for example, by extension of the gate material of gate 3414 and gate 3424 to couple the gates together. In some embodiments, gate bridge 3450 may be formed by a single extension of gate material from either gate 3414 or gate 3424 that is extended to the other gate. Gate bridge 3450 may also include extension of material for gate spacers. Gate bridge 3450 merges gate 3414 and gate 3424 for implementation of transistor 3410 and transistor 3420 in various embodiments of CMOS devices, some examples of which are described herein. Various embodiments may also be contemplated where gate 3414 and/or gate 3424 extend in other directions. For instance, a gate may include an extension that extends towards an outer boundary of device 3400 (e.g., towards an outer boundary of the cell structure in an opposite direction of gate bridge 3450).
In the illustrated embodiment of
In another contemplated embodiment, contact 3419 and contact 3429 may be connected by strap 3520. Strap 3520 may also be a metal strap. In some embodiments, strap 3520 is formed as a single contact along with contact 3419 and contact 3429. For example, strap 3520, contact 3419, and contact 3429 may be part of a single metal contact plate formed in the contact layer. Various embodiments may also be contemplated where contact 3419 and/or contact 3429 extends outwards from the bottoms of transistors 3410, 3420. For instance, a contact may have a portion that extends towards an outer boundary of device 3500 (e.g., towards an outer boundary of the cell structure).
It should be understood that while device 3400, shown in
Inverter cell device 3600 may be derived from the structure of device 3400, shown in
In certain embodiments, device 3600 includes backside vias 3610A, 3610B. Backside via 3610A is coupled to lower source/drain region 3412 through lower contact 3419. Backside via 3610A couples lower source/drain region 3412 to backside power routing 3440A. For device 3600, backside power routing 3440A provides power supply (e.g., Vdd) to lower source/drain region 3412 and transistor 3410. Backside via 3610B is coupled to lower source/drain region 3422 through lower contact 3429. Backside via 3610B couples lower source/drain region 3422 to backside power routing 3440B. For device 3600, backside power routing 3440B provides ground supply (e.g., Vss) to lower source/drain region 3422 and transistor 3420.
In various embodiments, device 3600 includes topside vias 3620A, 3620B. Topside via 3620A may be coupled to upper source/drain region 3416 through upper contact 3418 and topside via 3620B may be coupled to upper source/drain region 3426 through upper contact 3428. Topside vias 3620A, 3620B may provide connection to signal routing resources (e.g., routes 3430A-E) in a first metal layer above transistor 3410 and transistor 3420. For example, in the illustrated embodiment, topside via 3620A is coupled to route 3430B and topside via 3620B is coupled to route 3430D. Routes 3430B and 3430D may provide routes for output signals from transistor 3410 and transistor 3420, respectively.
In certain embodiments, a route for an input signal to transistor 3410 and transistor 3420 is provided by route 3430C. As shown in
It should be noted that while
The topside and backside plan views of device 3600 shown in
NAND cell device 4100 may be derived from the structure of device 3400, shown in
In certain embodiments, route for input signals to transistor 3410, transistor 3410′, transistor 3420, and transistor 3420′ are provided by route 3430C. As shown in
In certain embodiments, upper source/drain region 3416 of transistor 3410 and upper source/drain region 3416′ of transistor 3410′ are connected by contact 3418. Similarly, upper source/drain region 3426 of transistor 3420 and upper source/drain region 3426′ of transistor 3420′ are connected by contact 3428. In various embodiments, device 4100 includes topside via 3620 connected to contact 3418. Topside via 3620 may provide connection to route 3430B in the first metal layer above the transistor region of device 4100. In the illustrated embodiment, route 3430B provides a route for output signals from transistor 3410 and transistor 3410′.
In the illustrated embodiment, only transistor 3410, transistor 3410′, and transistor 3420 are connected to backside layers. For instance, transistor 3410 is connected to backside power routing 3440A by contact 3419 and backside via 3610A, transistor 3410′ is connected to backside power routing 3440A by contact 3419′ and backside via 3610A′, and transistor 3420 is connected to backside power routing 3440B by contact 3429 and backside via 3610B, as shown in
In certain embodiments, lower source/drain region 3422′ in transistor 3420′ is connected to contact 3429′, which is not connected to a backside power routing layer. Contact 3429′ extends away from lower source drain region 3422′ and towards a boundary of the cell, as shown in
In the illustrated embodiment, route 3430E provides a route for output signals from transistor 3420 and transistor 3420′. The output signals routed through route 3430E may be combined with output signals from route 3430B. For example, a metal layer above the first metal layer may include a strap (or other connector) coupling route 3430B and route 3430E such that the outputs of the transistors are merged together into a single output.
The various routings and connections in device 4100 form the NAND cell device.
MUX cell device 4600 may be derived from the structure of device 3500, shown in
As MUX cell device 4600 is a transmission device, none of transistor 3410 and transistor 3410″ and none of transistor 3420 and transistor 3420″ are connected to any power in the MUX cell structure. In various embodiments of MUX cell device 4600, the lower source/drain regions of the transistors are connected together (e.g., merged together). For instance, in the illustrated embodiment, contact plate 4620 is connected to lower source/drain region 3412 in transistor 3410, lower source/drain region 3412″ in transistor 3410″, lower source/drain region 3422 in transistor 3420, and lower source/drain region 3422″ in transistor 3420″.
In certain embodiments, contact via 4630 is coupled to contact plate 4620. Contact via 4630 may be connected to contact plate 4620 at or near a center of the contact plate. Contact via 4630 then connects to route 3430C in the first metal layer above the transistor region. In various embodiments, route 3430C provides output routing for MUX cell device 4600. Thus, contact via 4630 may be referred to as an output pin of MUX cell device 4600.
In various embodiments, gates 3414, 3414″, 3424, 3424″ are extended towards the boundary of the cell to provide surfaces for direct vertical connections to the gates from routes in the first metal layer above. For example, as illustrated in
In certain embodiments, upper source/drain region 3416 in transistor 3410 is connected to upper source/drain region 3426 in transistor 3420 by contact 4610A. This connection merges upper source/drain region 3416 with upper source/drain region 3426. Similarly, upper source/drain region 3416″ in transistor 3410″ is connected to upper source/drain region 3426″ in transistor 3420″ by contact 4610B. With the merging of these upper source/drain regions and the common connection between the lower source/drain regions (and single output through contact via 4630), device 4600 may operate as a MUX (multiplexer) where signals are input through gate vias 3630A-D and output through contact via 4630.
Device 5100 may be derived from the structure of device 3400, shown in
In various embodiments, as shown in
Turning next to
A power supply 5308 is also provided which supplies the supply voltages to SoC 5306 as well as one or more supply voltages to the memory 5302 and/or the peripherals 5304. In various embodiments, power supply 5308 represents a battery (e.g., a rechargeable battery in a smart phone, laptop or tablet computer, or other device). In some embodiments, more than one instance of SoC 5306 is included (and more than one external memory 5302 is included as well).
The memory 5302 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of the SDRAMs such as mDDR3, etc., and/or low power versions of the SDRAMs such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled onto a circuit board to form memory modules such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, the devices are mounted with a SoC or an integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.
The peripherals 5304 include any desired circuitry, depending on the type of system 5300. For example, in one embodiment, peripherals 5304 includes devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, global positioning system, etc. In some embodiments, the peripherals 5304 also include additional storage, including RAM storage, solid state storage, or disk storage. The peripherals 5304 include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc.
As illustrated, system 5300 is shown to have application in a wide range of areas. For example, system 5300 may be utilized as part of the chips, circuitry, components, etc., of a desktop computer 5310, laptop computer 5320, tablet computer 5330, cellular or mobile phone 5340, or television 5350 (or set-top box coupled to a television). Also illustrated is a smartwatch and health monitoring device 5360. In some embodiments, smartwatch may include a variety of general-purpose computing related functions. For example, smartwatch may provide access to email, cellphone service, a user calendar, and so on. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health related functionality. For example, a health monitoring device may monitor a user's vital signs, track proximity of a user to other users for the purpose of epidemiological social distancing, contact tracing, provide communication to an emergency service in the event of a health crisis, and so on. In various embodiments, the above-mentioned smartwatch may or may not include some or any health monitoring related functions. Other wearable devices are contemplated as well, such as devices worn around the neck, devices that are implantable in the human body, glasses designed to provide an augmented and/or virtual reality experience, and so on.
System 5300 may further be used as part of a cloud-based service(s) 5370. For example, the previously mentioned devices, and/or other devices, may access computing resources in the cloud (i.e., remotely located hardware and/or software resources). Still further, system 5300 may be utilized in one or more devices of a home 5380 other than those previously mentioned. For example, appliances within the home may monitor and detect conditions that warrant attention. For example, various devices within the home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device and provide an alert to the homeowner (or, for example, a repair facility) should a particular event be detected. Alternatively, a thermostat may monitor the temperature in the home and may automate adjustments to a heating/cooling system based on a history of responses to various conditions by the homeowner. Also illustrated in
The present disclosure includes references to “an “embodiment” or groups of “embodiments” (e.g., “some embodiments” or “various embodiments”). Embodiments are different implementations or instances of the disclosed concepts. References to “an embodiment,” “one embodiment,” “a particular embodiment,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the disclosure.
This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all implementations of these embodiments will necessarily manifest any or all of the potential advantages. Whether an advantage is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are a number of reasons why an implementation that falls within the scope of the claims might not exhibit some or all of any disclosed advantages. For example, a particular implementation might include other circuitry outside the scope of the disclosure that, in conjunction with one of the disclosed embodiments, negates or diminishes one or more the disclosed advantages. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation techniques or tools) could also negate or diminish disclosed advantages. Even assuming a skilled implementation, realization of advantages may still depend upon other factors such as the environmental circumstances in which the implementation is deployed. For example, inputs supplied to a particular implementation may prevent one or more problems addressed in this disclosure from arising on a particular occasion, with the result that the benefit of its solution may not be realized. Given the existence of possible factors external to this disclosure, it is expressly intended that any potential advantages described herein are not to be construed as claim limitations that must be met to demonstrate infringement. Rather, identification of such potential advantages is intended to illustrate the type(s) of improvement available to designers having the benefit of this disclosure. That such advantages are described permissively (e.g., stating that a particular advantage “may arise”) is not intended to convey doubt about whether such advantages can in fact be realized, but rather to recognize the technical reality that realization of such advantages often depends on additional factors.
Unless stated otherwise, embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of claims that are drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative rather than restrictive, absent any statements in the disclosure to the contrary. The application is thus intended to permit claims covering disclosed embodiments, as well as such alternatives, modifications, and equivalents that would be apparent to a person skilled in the art having the benefit of this disclosure.
For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of other dependent claims where appropriate, including claims that depend from other independent claims. Similarly, features from respective independent claims may be combined where appropriate.
Accordingly, while the appended dependent claims may be drafted such that each depends on a single other claim, additional dependencies are also contemplated. Any combinations of features in the dependent that are consistent with this disclosure are contemplated and may be claimed in this or another application. In short, combinations are not limited to those specifically enumerated in the appended claims.
Where appropriate, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims of another format or statutory type (e.g., method).
Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. Public notice is hereby given that the following paragraphs, as well as definitions provided throughout the disclosure, are to be used in determining how to interpret claims that are drafted based on this disclosure.
References to a singular form of an item (i.e., a noun or noun phrase preceded by “a,” “an,” or “the”) are, unless context clearly dictates otherwise, intended to mean “one or more.” Reference to “an item” in a claim thus does not, without accompanying context, preclude additional instances of the item. A “plurality” of items refers to a set of two or more of the items.
The word “may” is used herein in a permissive sense (i.e., having the potential to, being able to) and not in a mandatory sense (i.e., must).
The terms “comprising” and “including,” and forms thereof, are open-ended and mean “including, but not limited to.”
When the term “or” is used in this disclosure with respect to a list of options, it will generally be understood to be used in the inclusive sense unless the context provides otherwise. Thus, a recitation of “x or y” is equivalent to “x or y, or both,” and thus covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, a phrase such as “either x or y, but not both” makes clear that “or” is being used in the exclusive sense.
A recitation of “w, x, y, or z, or any combination thereof” or “at least one of . . . w, x, y, and z” is intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrasings cover any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “at least one of . . . w, x, y, and z” thus refers to at least one element of the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase is not to be interpreted to require that there is at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.
Various “labels” may precede nouns or noun phrases in this disclosure. Unless context provides otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, the labels “first,” “second,” and “third” when applied to a feature do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise.
The phrase “based on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”
The phrases “in response to” and “responsive to” describe one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect, either jointly with the specified factors or independent from the specified factors. That is, an effect may be solely in response to those factors, or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A, or that triggers a particular result for A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase also does not foreclose that performing A may be jointly in response to B and C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B. As used herein, the phrase “responsive to” is synonymous with the phrase “responsive at least in part to.” Similarly, the phrase “in response to” is synonymous with the phrase “at least in part in response to.”
Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation [entity] configured to [perform one or more tasks] is used herein to refer to structure (i.e., something physical). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. Thus, an entity described or recited as being “configured to” perform some task refers to something physical, such as a device, circuit, a system having a processor unit and a memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.
In some cases, various units/circuitslcomponents may be described herein as performing a set of task or operations. It is understood that those entities are “configured to” perform those tasks/operations, even if not specifically noted.
The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform a particular function. This unprogrammed FPGA may be “configurable to” perform that function, however. After appropriate programming, the FPGA may then be said to be “configured to” perform the particular function.
For purposes of United States patent applications based on this disclosure, reciting in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Should Applicant wish to invoke Section 112(f) during prosecution of a United States patent application based on this disclosure, it will recite claim elements using the “means for” [performing a function] construct.
Different “circuits” may be described in this disclosure, These circuits or “circuitry” constitute hardware that includes various types of circuit elements, such as combinatorial logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random-access memory, embedded dynamic random--access memory), programmable logic arrays, and so on. Circuitry may be custom designed, or taken from standard libraries. In various implementations, circuitry can, as appropriate, include digital components, analog components, or a combination of both. Certain types of circuits may be commonly referred to as “units” (e.g., a decode unit, an arithmetic logic unit (ALU), functional unit, memory management unit (MMU), etc.). Such units also refer to circuits or circuitry.
The disclosed circuits/units/components and other elements illustrated in the drawings and described herein thus include hardware elements such as those described in the preceding paragraph. In many instances, the internal arrangement of hardware elements within a particular circuit may be specified by describing the function of that circuit. For example, a particular “decode unit” may be described as performing the function of “processing an opcode of an instruction and routing that instruction to one or more of a plurality of functional units,” which means that the decode unit is “configured to” perform this function. This specification of function is sufficient, to those skilled in the computer arts, to connote a set of possible structures for the circuit.
In various embodiments, as discussed in the preceding paragraph, circuits, units, and other elements defined by the functions or operations that they are configured to implement, The arrangement and such circuits/units/components with respect to each other and the manner in which they interact form a microarchitectural definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitectural definition. Thus, the microarchitectural definition is recognized by those of skill in the art as structure from which many physical implementations may be derived, all of which fall into the broader structure described by the microarchitectural definition. That is, a skilled artisan presented with the microarchitectural definition supplied in accordance with this disclosure may, without undue experimentation and with the application of ordinary skill, implement the structure by coding the description of the circuits/units/components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a fashion that may appear to be functional. But to those of skill in the art in this field, this HDL description is the manner that is used transform the structure of a circuit, unit, or component to the next level of implementational detail. Such an HDL description may take the form of behavioral code (which is typically not synthe sizable), register transfer language (RTL) code (which, in contrast to behavioral code, is typically synthesizable), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may subsequently be synthesized against a library of cells designed for a given integrated circuit fabrication technology, and may be modified for timing, power, and other reasons to result in a final design database that is transmitted to a foundry to generate masks and ultimately produce the integrated circuit. Some hardware circuits or portions thereof may also be custom-designed in a schematic editor and captured into the integrated circuit design along with synthesized circuitry. The integrated circuits may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnect between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuits, and/or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized to a programmable logic array such as a field programmable gate array (FPGA) and may be implemented in the FPGA. This decoupling between the design of a group of circuits and the subsequent low-level implementation of these circuits commonly results in the scenario in which the circuit or logic designer never specifies a particular set of structures for the low -level implementation beyond a description of what the circuit is configured to do, as this process is performed at a different stage of the circuit implementation process.
The fact that many different low-level combinations of circuit elements may be used to implement the same specification of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations may vary according to changes in the fabrication technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a particular project, etc. In many cases, the choices made by different design tools or methodologies to produce these different implementations may be arbitrary.
Moreover, it is common for a single implementation of a particular functional specification of a circuit to include, for a given embodiment, a large number of devices (e.g., millions of transistors). Accordingly, the sheer volume of this information makes it impractical to provide a full recitation of the low-level structure used to implement a single embodiment, let alone the vast array of equivalent possible implementations. For this reason, the present disclosure describes structure of circuits using the functional shorthand commonly employed in the industry.
The present application claims priority to U.S. Provisional App. Ser. No. 63/376,796, entitled “Stacked FET Standard Cell Architecture,” filed Sep. 23, 2022, U.S. Provisional App. Ser. No. 63/376,799, entitled “Stacked SRAM Cell Architecture,” filed Sep. 23, 2022, U.S. Provisional App. Ser. No. 63/376,800, entitled “SRAM Macro Design Architecture,” filed Sep. 23, 2022, U.S. Provisional App. Ser. No. 63/376,802, entitled “Vertical Transistors With Backside Power Delivery,” filed Sep. 23, 2022; the disclosures of each of the above-referenced applications are incorporated by reference herein in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| 63376796 | Sep 2022 | US | |
| 63376799 | Sep 2022 | US | |
| 63376800 | Sep 2022 | US | |
| 63376802 | Sep 2022 | US |
