Patent Application
20150200177
The present invention relates generally to semiconductor packaging and, more particularly, to wafer level package having a redistribution layer formed with metallic powder.
Packaged semiconductors provide external electric connections and physical protection for packaged dies. Continued progress in reduction of the size of the semiconductor dies and increased functionality and complexity of the integrated circuits of the dies requires size reduction of the packaging with the same or greater complexity of the electrical connections with external circuits.
One typical type of packaged semiconductors is Quad Flat Pack (QFP) packages, which are formed with a semiconductor die mounted to a lead frame. The lead frame is formed from a sheet of metal that has a die attach pad often called a flag and leads or lead fingers that attach the flag to a frame. The lead fingers are connected to electrodes of the die with bond wires to provide a means of easily electrically connecting the die to circuit boards and the like. The die and lead frame are encapsulated in a plastic material leaving only sections of the leads exposed. These exposed leads are cut from the frame of the lead frame (singulated) and bent for ease of connection to a circuit board. However, the inherent structure of QFP packages results in limiting the number of leads, and therefore the number of package external electrical connections that can be used for a specific QFP package size. Further, the external electrical connections of the lead frame based grid array packages are typically fabricated from a thin single sheet of conductive material, such as copper or aluminium, and these connections may not be sufficiently held within the encapsulating material and may become loose.
Wafer level chip scale packages, such as grid array packages have been developed as an alternative to QFP packages. Grid array packages increase the number of external electrical connections while maintaining or even decreasing the package size. Such grid array packages include Pin Grid Arrays (PGA), Ball Grid Array (BGA) and Land Grid Arrays (LGA). The assembly of such packages requires numerous masking, depositing and etching steps, which are relatively time consuming and costly.
The invention, together with objects and advantages thereof, may best be understood by reference to the following description of preferred embodiments together with the accompanying drawings in which:
The detailed description set forth below in connection with the appended drawings is intended as a description of presently preferred embodiments of the invention, and is not intended to represent the only forms in which the present invention may be practised. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the invention. In the drawings, like numerals are used to indicate like elements throughout. Furthermore, terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that module, circuit, device components, structures and method steps that comprises a list of elements or steps does not include only those elements but may include other elements or steps not expressly listed or inherent to such module, circuit, device components or steps. An element or step proceeded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements or steps that comprises the element or step. The term semiconductor device, as used herein, refers to a packaged semiconductor die.
In one embodiment, the present invention provides a method of assembling a semiconductor device. The method comprises providing a partially formed package that includes a semiconductor die and an encapsulating region. A support surface of the partially formed package includes an active surface of the die and an adjacent surface of the encapsulating region. Selectively coating of the support surface with a first electrical insulating layer is performed, with bonding pads on the active surface of the die being exposed through access apertures in the first electrical insulating layer. A layer of metallic powder is deposited onto the first electrical insulating layer such that the powder fills the access apertures. Electrically conductive runners are formed from the layer of metallic powder. The runners are selectively connected to the die bonding pads through the access apertures. Regions of the layer of metallic powder that do not form the runners are then removed. The runners are then selectively coated with a further electrical insulating layer such that a mounting area of each runner is exposed through an external connection aperture in the further electrical insulating layer.
In another embodiment, the present invention provides a semiconductor device comprising a semiconductor die and an encapsulating substrate that together form a support surface. The support surface includes an active surface of the die and an adjacent surface of the encapsulating substrate. A first electrical insulating layer selectively coats the support surface so that bonding pads on the active surface of the die are exposed through access apertures in the first electrical insulating layer. Electrically conductive runners are respectively connected to the die bonding pads through the access apertures and insulated from the active surface by the first electrical insulating layer. The runners are formed from a metallic powder deposit. A further electrical insulating layer coats the runners such that a mounting area of each runner is exposed through an external connection aperture in the further electrical insulating layer.
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At a providing block 1210 the partially formed package 200 is provided typically as part of the sheet 100. At a selectively coating block 1220 the support surface 204 is selectively coated with the first electrical insulating layer 302. Bonding pads 108 on the active surface 110 of the die 104 are exposed through the access apertures 304 in the first electrical insulating layer 302. As previously mentioned, excess powder and powder that is purposefully not melted may be removed by vacuuming or washing.
At a depositing block 1230 the layer of metallic powder 402 is deposited onto the first electrical insulating layer 302 so that the powder fills the access apertures 304. The depositing of the layer of metallic powder 402 is typically performed by a depositing and rolling process so that a planar upper powder layer surface is provided. The rolling process also reduces the possibility of unwanted voids in the layer of metallic powder 402. Next, at a forming block 1240, the electrically conductive runners 502 are formed from the layer of metallic powder such that the runners 502 are selectively connected to the bonding pads 108 through their respective access apertures 304. In one embodiment the runners 502 are formed by selective laser melting of the metallic powder. In another embodiment the runners 502 are formed by selective laser sintering process of the metallic powder followed by solidifying of the melted powder. Remaining metallic powder 402 (powder 402 that does not form the runners 502) that was not sintered or melted is removed by a vacuuming process at a removing block 1250. As will be apparent to a person skilled in the art, melting of the metallic powder will form almost full density solids. In contrast, sintering of the metallic powder requires a further baking step to solidify the sintered metallic powder.
A process of selectively coating is performed at a block 1260. The process of block 1260 coats at least the runners 502 with the further electrical insulating layer 702 such that the mounting area 704 of each runner 502 is exposed through their respective external connection aperture 706 in the further electrical insulating layer 702. At a forming block 1270, mounting pads are formed by the solder balls 802, which are mounted to a respective mounting area 704 such that part of each solder ball 800 is located in an external connection aperture 706. In another embodiment electrically conductive mounting pads 1002 are formed by depositing of the further layer of metallic powder in each external connection aperture 706. The further layer of metallic powder is then sintered or melted and solidified to form the electrically conductive mounting pads 1002. Solder balls 1004 are then mounted to their respective external electrically conductive mounting pads 1002 by fluxing and a reflow process. In yet a further embodiment, the electrically conductive mounting pads are formed by a depositing of a further layer of metallic powder over the further electrical insulating layer 702 so that the powder fills the external connection apertures 706. The metallic powder that is in and on top of each of the external connection apertures 706 is sintered or melted and solidified to form external electrically conductive mounting pads 1102. Excess powder is then removed so that the resulting each of the external electrically conductive mounting pads 1102 protrude out from a respective external connection aperture 706.
At a separating block 1280 each package is separated from the sheet 100 by a singulation process to form the semiconductor package 900, 1000 or 1100. The singulation process may comprise cutting, sawing or stamping, as is known in the art.
Advantageously, the present invention provides for assembling a semiconductor device without the need for a lead frame or numerous masking, depositing and etching processes. Also, if required, further depositing of insulating and metallic powder layers can be performed along with sintering or melting to form more elaborate conductive runner formations and grid array structures.
The description of the preferred embodiments of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the forms disclosed. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiment disclosed, but covers modifications within the spirit and scope of the present invention as defined by the appended claims.
