Wireless train management system

Abstract
A robust system processor comprising three parallel processors, each configured to process in parallel an input and emit an output; and a reconciler that compares the three outputs, determines whether at least two of the outputs are equal, and if so validates the majority output and communicates the validated output via a network to at least one other system processor.
Description
FIELD OF THE INVENTION

The field of the present invention and its embodiments relate to a system and method of managing train positions, distances, speeds, and locations within a train system.


BACKGROUND

Communication Based Train Control (CBTCs) systems have been evolving throughout the years, implementing new versions of technology as they are released and although the CBTC components upgrade overtime, the core system architecture still remains the same as it's fruition in the late 1980's.


Advances in data storage and processing now enable far greater digital applications to occur in much smaller footprint and at a fraction of the cost. Along with hardware advances and widespread availability, the adjoining software development has become a much more common skill and is approaching the same commonality as reading and writing skills. With these technological and social advances, an opportunity is presented to redefine the typical CBTC system architecture to elevate train control solutions and make the system relatable to today's world. Train Control processing now has the ability to move from a large centralized control facility into each train, creating autonomy on the rail, presenting tremendous opportunity for optimization in functionality, operation, maintenance, installation, cost, and so much more.


With many of the industrialized nations and cities around the world having to come to grips with their aging public transportations systems a need and an opportunity arose for a modern approach to overseeing these systems. In recent years, multiple disclosures have attempted to fix various aspects of existing systems. Various systems and methodologies are known in the art. However, their structure and means of operation are substantially different from the present disclosure.


Review of Related Technology

U.S. Pat. No. 9,669,850 pertains to a method and system for monitoring rail operations and transport of commodities via rail, a monitoring device including a radio receiver is positioned to monitor a rail line and/or trains of interest. The monitoring device including a radio receiver (or LIDAR) configured to receive radio signals from trains, tracks, or trackside locations in range of the monitoring device. The monitoring device receives radio signals, which are demodulated into a data stream. However, this disclosure requires memory storage of the trains' activities at a central location instead of on the MD tags.


U.S. Pub. 2017/0043797 pertains to Methods and systems that utilize radio frequency identification (RFID) tags mounted at trackside points of interest (POI) together with an RFID tag reader mounted on an end of train (EOT) car. The RFID tag reader and the MD tags work together to provide information that can be used in a number of ways including, but not limited to, determining train integrity, determining a geographical location of the EOT car, and determine that the EOT car has cleared the trackside POI along the track. This publication discloses storing memory on the RFID tags but does not disclose having the memory be volatile.


U.S. Pat. No. 9,711,046 pertains to a control system presenting a configurable virtual representation of at least a portion of a train and associated train assets, including a real-time location, configuration, and operational status of the train and associated train assets traveling along a railway. The control system may include a train position determining system, (such as RFID) and a train configuration determining system.


The train control system disclosed herein establishes a virtual train-to-train communication path, coupled with the on-board processing enabling the trains to operate autonomously and in complete synchronization with all other trains on the line, reducing communication overheads and processing delays inherent n traditional CBTC systems. The open source of software and hardware enable existing train systems to have multiple vendors for the supply chain thereby promoting competitive pricing, and installation flexibility.


SUMMARY OF THE EMBODIMENTS

A robust system processor comprising three parallel processors, each configured to process in parallel an input and emit an output; and a reconciler that compares the three outputs, determines whether at least two of the outputs are equal, and if so validates the majority output and communicates the validated output via a network to at least one other system processor. Such system processors may be advantageously utilized in a wireless train management system.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 shows the three modes of operation of system.



FIG. 2 shows an embodiment of a train set up.



FIG. 3 shows a possible set up of the system along the tracks.



FIG. 4 shows a detail of an operational schematic of an embodiment of the system.



FIG. 5A-5D shows another detail of an operational schematic of an embodiment of the system.



FIG. 6A-6B shows the data flow diagram of an embodiment of the system.



FIG. 7A-7D shows the data verification of an embodiment of the system.



FIG. 8 shows a processor array in accordance with an embodiment.





DETAILED DESCRIPTION

Embodiments of the present invention will now be described with reference to the drawings, in which identical elements in the various figures are identified with the same reference numerals. These embodiments are provided by way of explanation of the present invention, which is not intended to be limited thereto. Those of ordinary skill in the art may appreciate upon reading the present specification and viewing the present drawings that various modifications and variations can be made thereto.


The present invention, sometimes hereinafter referred to as the ‘Acorn’ system, is designed to allow train sets to operate along a railway autonomously while reducing trackside infrastructure to a minimum. Acorn is based upon the principles and standards noted in IEEE 1474.1: “IEEE Standard for Communications-Based Train Control (CBTC) Performance and Functional Requirements”, but, unlike traditional systems using trackside equipment, the equipment located on the train is used to control the movement of trains. At the center of the Acorn design is the placement of Acorn Tags at an interval typically 10-30 feet but preferably at 25 feet along the track. Along straight (or through) track areas, Type 1 Acorn Tags are placed at the typical interval with no hardwire connections. At switch and crossing locations, Type 2 Acorn Tags are deployed at the typical interval with series hardwired connections simulating track circuits. These simulated track circuits can interface with the interlocking controller and communicate with approaching trains, allowing the system to operate seamlessly.


Below, in systems operating at 90 mph, only one Acorn tag and reader interface method is required to achieve a successful read write cycle, simplifying the installation. However, if a deployment needs to support speeds greater than 90 mph, the system can be configured, as is, to leverage a split read write cycle to continue achieving a successful read write cycle.


The Acorn System is an open protocol based system, allowing software applications to be available from multiple vendors and sources and the system being adaptable to various systems around the world, using multiple operating systems on different platforms. This approach, as with the supply of the Acorn Tags, does not lock the Acorn system into a single supplier of the system. Furthermore, this approach removes common failure modes in both software and hardware of the system.


Referring now to FIG. 1, a method for controlling a train system is illustratively depicted, in accordance with an embodiment of the present invention. According to an embodiment, a first train car of a first train set communicates to a first train car of second train set via a centralized data network using radio controlled communication (RCC), wherein the RCC includes a track database, a schedule database, and a route database, with the first train car of the first train set communicating to the first train car of the second train set via a back-up communication system.


According to an embodiment, the system architecture used in the present method enables several layers of communication to transmit and receive the critical data on-board to calculate safe headway. These layers of communication help form the three modes of operation (labelled at 1, 2, and 3 in FIG. 1) to ensure the continuous safe operation of trains. Mode 1 uses all layers of technology to provide the systems minimum headway, leading Mode 1 to be the primary and thus normal mode of operation. According to an embodiment, in Mode 1, normal operation calculates headway with the following redundant inputs: RCC broadcasted Schedule Updates and Train Location confirmations (a); Train to Train broadcasted Train Location confirmations (b); Tag read Train Ahead Time and Speed (c); Tag read Current Train Location confirmation (d); and LIDAR enabled Rail Visual Range sensing clear distance ahead (e).


According to an embodiment, the subsequent mode of operation, Mode 2, is reduced and engages when RCC communication is lost, but allows the system to continue functioning by increasing the minimum headway. Lastly, Mode 3 shows autonomous operation that enables total train autonomy by relying on taps and on-board equipment information only, imposing the most restrictive headway.


According to an embodiment, the backup communication system includes at least a first set of two trackside points located along a path of the first train set and at least one RFID Type 1 tag located at each of the at least two trackside points configured to store characteristics of the first train set as it passes the first set at least two track side points and at least a second set of two trackside points located along at a track switch with at least one RFD Type 2 tag being located at each of the at least two trackside points configured to store characteristics of the train set as it passes the second set of the at least two track points and at least one RFID tag reader being located on the first train set and at least one RFID tag reader located on the second train set.


The RFID type 1 tag or the RFID type tag of the back-up system can store a speed, a brake status, a train ID, a switch status, a time stamp, and a schedule of the latest train to pass the REID type 1 tag or the RFID type 2 tag. The speed, the brake status, the train ID, the switch status, the time stamp, and the schedule of the latest train to pass the REID type 1 tag or the RFID type 2 tag, that are recorded on the tags can be rewritten with information with the next train to pass the RFID type 1 tag or the RFID type 2 tag. The read and write step can be typically completed between approximately 10 milliseconds and approximately 30 milliseconds, but optimally 20 milliseconds is preferred for safe operation of the system.


Each train can car carry three principle databases onboard, these being the track, schedule and route databases. The track database contains details of the track network and makes use of the Tag unique ID as the key for the entry record of that location. The temporary Speed field being variable and all others fields (civil speed, the next approaching train, the visual range, the next way point) being fixed unless maintenance has changed a tag. The schedule database allows the train to determine its location in relationship with other trains in the system. All fields (Train ID, the planned route, Planned time, and confirmed time) can be preloaded be updated throughout the journey. The route database, can contain the information required to navigate the track system. This database contains information pertaining to the expected location of the individual train in relation to time. The location is determined using unique identifiers (UIDs) assigned to each of a plurality of Tags.


Using the current UID and the Train ID, the Planned Time field can be accessed to determine if the train is ahead or behind of the planned schedule. For operation during Modes 2 and 3, the planned location could be determined using the Train Ahead ID and time. The Acorn System databases can be programmed to have in excess of 100.000 records. On initial startup, a search of all the databases to locate the current Tag UID entry and schedule location may take up to a second to locate the record. Fast indexing may be used thereafter as records will be accessed sequentially, hence incremental increase or decrease.


Train spacing is achieved by establishing the train location from Tags and Inertial navigation system, to an accuracy of at least ±12.5 ft. This data will be stored by the on-board network map and broadcasted to all trains along the route. The on-board network map also updates with train locations that it receives from other train broadcasts. Allowing the car computers to calculate the distance to train ahead, target speed and braking point to maintain a safe operating distance. The Tag has data fields for Time of last train, speed, running status. With no other received data this enables an on board calculation to determine where the train ahead is if it had applied its emergency brakes. As a train updates, it will broadcast its location to all other trains along the line every 100 ft or as determined by the trains operating speed.


To calculate the target speed and available headway for a trainset for use in Modes 2 and 3, the onboard processors can adhere to the following processes:


Headway-the Tag Sequence Array, preloaded from the Track Database, can be used to calculate a distance (in number of tags clear) to train ahead. This value can be known as the Clear Tags value. The tag location of the train ahead can be obtained the following methods: in Mode 1, the Location Database holds the current location of the train ahead. The location can be confirmed via a transmission from the train ahead and a validation has from the Route Control Center. If the location of the Train ahead has been received but not validated by the Route Control Center, then Mode 2 is invoked. Using the preceding train's speed and time when the train was at the tag, the ahead train's location can be predicted assuming a constant speed. This estimated train ahead location is compared to the planned location of that train with the location database and with the reported location from the train. The lower number of the two numbers is used to set the value in the Clear Tags field. If the train has not received any train status updates for more than 500 mS then Mode 3 will be invoked. In Mode 3, the train calculates the number of clear tags ahead from the tag data received and uses the scheduled location to amend the tag clear value as required. The Railway Visual Range will be used to modify the maximum speed permissible. From the obtained Tag Clear value, the train length (converted to number of tags) is subtracted. This becomes the planned stop tag for the train. The number of headway tags is then used to address on-board databases to determine the maximum speed that the train can operate at if it is to stop by the stop tag. The maximum speed derived from the on-board databases will then compared to the Civil Speed, Temporary Speed and choose the lowest value. The data received allows the train to calculate the speed and brake profile of the train ahead.


To determine the speed of the trainset, an Interrupt Request (IRQ) can be used to start a timer sequence that will amount the time between tag reads. The counter will be 64 bit using a 100 μS interval enabling the average speed to be determined using the known tag spacing between tags. At a speed of 10 mph, the counter will reach an integer value of 15,957 between tag readings at the tag spacing, as calculated by the formula below. This counter value could be used. to calculate the location of a train between tags, based on the average speed calculated between the previous Tags.








(
velocity
)



[

ft
sec

]


=



25



(

tag





distance

)



[
ft
]





x


(

integer





count

)


*

100


[

μ





S

]




*


1


,


000


,


000


1


[
sec
]











10


[

miles
hour

]


=


15.667


[

ft
sec

]


=


25
1750

*
10


,


000






For example, using the equations above, with a trainset traveling at 10 mph, an accurate location and speed calculation occurs every 1,596 mS, thus an accurate location and speed can be broadcasted to the RCC and other trainsets every 1,596 mS. As the speed of the trainset increases, the travel time decreases, allowing for higher broadcast frequency of accurate location and speed values. For example, at an average speed of 25 mph, location updates will occur every 682 mS, and at 60 mph every 284 mS. These update periods are all within IEEE standard values prescribed.


The Wide Area Network (WAN) Communications may use various technologies and networks to provide various levels of connectivity along different types of track areas. Ideally, communications should exist along the entirety of the track system to support broadcasted trainset locations as mentioned above, although continuous WAN communication is not required to continue operations. The broadcasted trainset locations requires only 1024 bits for data transmission and 1024 bits for confirmation acknowledgement, and thus minimal communications is required along the entirety of the track system.


In addition to trainset locations, the WAN Communications will need to support schedule updates from the RCC to each train car. Unlike trainset locations, schedule updates require reasonable bandwidth and will need to be supported by high bandwidth networks. Reasonable locations where high bandwidth communications should exist are stations and switch locations, also known as waypoints.


Within the databases, each record is less than 256 bits and, for a single route, is based on:


12-hour maximum schedule


Inclusion of both Local and Express lines


120-mile total route length


64 trains operation


Then the number of records to be updated is approximately 250 kB. Allowing for 16 CRC, data verification, and other communication overhead, updating a record of a single train would be 6 Mb, and for a complete schedule update 400 Mb (50 MB). It is noted that various embodiments of the present invention, such as communication and data updating (FIGS. 6A-6B) and data verification (FIGS. 7A-7D) can be presently found in one or more of the present figures (FIGS. 1-7D).


The Acorn System software complexity is significantly less than a typical CBTC system as the need for complex coding has been reduced to simple linear calculations as described in the headway, speed, and location database descriptions above. The individual class structures are defined so that software development of an individual class can be undertaken by different vendors as header file allowing the class to verify independently and not a single source supplier. SIL verification of the code within the header file, if required will be simpler to establish compliance with CENELEC EN 50159 standard, ERA requirements and IEEE standards.


This reduction in coding enables verification to a SIL rating much quicker, as the lines of code are less and multiple vendors can be engaged to provide the code.


At the switch locations, an Acorn Type 2 Tag can be installed for a typical distance of 4,000 feet leading into the actual switch. The Type 2 Tag will allow the interlocking/ARS to communicate with the onboard systems providing status of switch position and target speed for that location. If a dynamic communication between the existing equipment and the Acorn tags is not possible, the interface will provide track circuit emulation using existing trackside signals or in cab signals.


Referring now to FIG. 2, a train control system is illustratively depicted in accordance with an embodiment of the present invention, wherein the system includes a train set having at least one leading car and at least one trailing car, and at least one RFID tag reader located on the at least one leading and the at least one trailing car connected to a network. According to an embodiment, the tag reader, located on the train (as shown in FIG. 2), can include an RF transparent enclosure containing inside at least a pair of reader antennas wired to a chip reader, connected to the at least one leading car or the at least one trailing car by a wire. According to an embodiment, the network database on the leading car can be connected to the network database on the trailing car by a communication backbone tying together diverse networks, such as Bluetooth and Wi-Fi connections and the network of the leading car and/or the rear car can including a radar.


According to an embodiment, the network of the leading car or the trailing car further can be connected to a wireless communication network using an LTE network at locations where the trackside points are at an open track, and a Wi-Fi network at locations where the trackside points are at an enclosed track (as shown in FIG. 4). Alternatively the communication network could use Ultra-Wide Band (UWB) LWIP, WLAN, ADSL or Cable networks for communications.



FIG. 3 shows at least a first set of two trackside points located along a path of the train set to which at least one RFID Type 1 tag (Acorn tag) can be connected and configured to store characteristics of the train set as it passes the first set of at least two track side points. FIG. 3 further shows a second set of two trackside points located along a track switch and at least one RFID Type 2 tag (Acorn tag type 2) located at each of the at least two trackside points configured to store characteristics of the train set as it passes the second set of the at least two track points. According to an embodiment, the RFID type 2 tag can be connected to a second RFID type 2 tag by an RS485 cable. The RFID type 2 tag can include an I2C to RS485 converter connected to an RFID chip connected by I2C BUS connection, connected by a parallel connection to a tag antenna. According to an embodiment, the RFID type 1 tag and the RFID tag reader have a separation between approximately 7 inches and 40 inches, with the RFID tag reader can be located on an underside of the leading car and the underside of the trailing car. According to an embodiment, the RFID type 1 tags are spaced apart between approximately 20 to approximately 30 feet from each other, but optimally 25 feet, as seen in FIG. 3.


Referring now to FIG. 4, a detail of an operational schematic is illustratively depicted, in accordance with an embodiment of the present invention.


The interface at the route control center can translate the current train schedule held by the existing system into an Acorn database format adding the additional granularity of target times at each location. As the trains report their locations, the interface will emulate its positional reporting as currently used by the RCC. The second interface to the existing system is the automatic route setting system. If a route has been changed from that planned, the new routes are converted to an Acorn compatible format and transmitted to the Acorn operating trainsets. These interfaces allow operation with existing and enabling mixed traffic operation, which can also be shown in FIGS. 5A-5D.


As shown in FIG. 4, all train cars within the system will include the Acorn Tag Reader mounted to the underside, Wi-Fi and Bluetooth links between cars, Acorn processing equipment inside or outside the cars, WAN antennas on the top of the cars, radar collision detector on the front of driver cars, and a driver display in driver areas.


The key benefit of the Acorn System is that its introduction into service is by an overlay principle and trackside installation being reduce to a minimum avoiding disruption to the users of the systems while minimizing time and cost. To avoid Cyber hacks of the Tags or communications paths encryption is applied to all transmissions and stored Tag data.


According to an embodiment, introduction of service of the Acorn System will occur seamless as the changeover can be practically overnight.


Comparing the industry standard CBTC solutions, the present invention is the only system to utilize RFIDs with the read and write functions for capturing information from the train ahead. No other CBTC system has the “bread crumb” trail, which is a standalone system that can be used to operate trains when all other systems for wireless communications fail. The read/write tags create a virtual block signaling system with the blocks equal to the tag spacing.


In embodiments, a train control system, for use with a train set having at least one leading car and at least one trailing car, comprises a first set of two trackside points located along a path of the train set. At least one RIM Type 1 tag (Acorn tag) is coupled to the two trackside points. The Type 1 tag is configured to store characteristics of the train set as it passes the first set of two track side points. The embodiment further comprises a second set of two trackside points located along a track switch, and at least one MD Type 2 tag (Acorn tag 2) located at each of the two trackside points. The Type 2 tag is configured to store characteristics of the train set as it passes the second set of track points. The embodiment also comprises at least one RFID tag reader located on the leading car and the trailing car, connected to a network.


In embodiments, a method of controlling a train system comprises a first train car of a first train set communicating with a first car of second train set via a centralized radio controlled communication (RCC) data network, the network containing a track database, a schedule database, and a route database. The first car of the first train set communicates with the first car of the second train set via a back-up communication system, the backup communication system (referred to as mode 1 above) including a first set of two trackside points located along a path of the first train set; an RFID Type 1 tag located at each of the two trackside points configured to store characteristics of the first train set as it passes the first set of two track side points; a second set of two trackside points located along a track switch; an RFID Type 2 tag located at each of the second set of two trackside points configured to store characteristics of the train set as it passes the second set of track points; and at least one RFID tag reader located on each of the first train set and the second train set.


Voting System

Systems such as the Wireless Train Management System and others rely on a plurality of processors to receive inputs, perform functions using the inputs, and provide valid outputs. Some such systems may not be able to tolerate a fault in even a single processor. To make such systems more robust, it may be desirable to replace every processor in the system with a plurality of processors, arranged in such a way as to emulate the operation of the original system. For example, a single original processor that has an input may be replaced with three processors arranged to process the original input in parallel, and to handle their outputs in a manner that gives the same output as the original processor would give, even if one of the three replacement processors fails. To do so, the three processor outputs may be input into a reconciler that compares each output against the others. If at least two out of the three outputs are identical, the identical outputs are deemed by the reconciler to be the correct output, and it is output by the reconciler.


A processor can ordinarily be considered as introducing a possible single point of failure. However, the reconciler eliminates the possible single point of failure through the use of three processors, each one able to compare its own output with that of the other two processors, and if needed, adjust its output to the majority output.


System Architecture

The system architecture is formed of three processors for every one processor of the original system, interconnected to form an array of three columns, with a number of rows equal in number to the number of functions that need to be performed. Thus, each row is representative of a process; and the number of columns is equal to the number of processors independently performing that process.


In the exemplary embodiment, the number of columns must be at least three and may be equal to any value greater than 3 that is odd, so the total number of columns is equal to 2n+1, where n is any positive integer.


All row processors are interconnected by three buses (which may be serial or parallel) for data communication between processors. If the row is using parallel buses the bus width shall be equal to the processor data size, e.g. 8, 16, 32, 64 etc. Each bus is exclusive to one row.


Each row processor connects to the processor row above and below using separate buses for up and down connections.


The processor array accepts inputs or provides outputs to the common bus along the top and bottom of the overall processor array.


Each row of the processor array has an identity bus (ID).


The non-maskable interrupt line (Reset) of each processor is connected to an integrator (an RC network) so that the manufacturing tolerances of the RC network will allow each processor to start after a random number of clock cycles, thus making the row processors start up at different times.


During every initial power on and hard reset process, processors take the first available ID line on the ID bus. Processor IDs are assigned one by one based on the different start times, until all processors have an assigned Processor ID. This process and Processor IDs may be nonsequential or based on the physical locations or connections of the processors.


System Operation

Once the processor has obtained a Processor ID, the next step is to determine if there are at least two other processors active in the row of the processor array. If so, the processor will perform the processing function on the data received from the row above or below, as programmed.


As data is received from the processor in the row above or below, the processor will revalidate that the data from the adjacent processor above or below is identical to that received by all active processors in the row via the row buses.


The processor will take the data and perform the designated row function on the data and on completion of the process broadcast via the row buses its output data.


On receipt of the data on the row bus the bus will validate the data through checking that it is identical on at least one other row bus. If the data is valid the processor will accept the data into the validation array. After the data is received from at least two row processors, the processor will compare its output to the data stored in the validation table.


The received values in the validation table are then compared looking for the majority identical data, which is then compared to the data of the processor. If the processor data matches the majority of the validation table then it is considered a valid result. Otherwise, it will replace its own output data with the majority data value.


The Array top and bottom buses, when operating as input busses, will have all row processors connected to receive the inputs simultaneously. When the top or bottom bus is operating as an output being driven by the row processors, only the lowest ID Processor that is active will be connected to the bus. All other processors will remain in the non-active state. An exemplary Array ID Table is shown below.












Array ID Table



















Processor
Processor
Processor
Processor
Processor


ID 2
ID 1
ID 5
ID 4
ID 3


Processor
Processor
Processor
Processor
Processor


ID 4
ID 3
ID 1
ID 5
ID 2


Processor
Processor
Processor
Processor
Processor


ID 1
ID 5
ID 2
ID 3
ID 4









Although embodiments of the invention have been described with a certain degree of particularity, it is to be understood that the present disclosure has been made only by way of illustration and that numerous changes in the details of construction and arrangement of parts may be resorted to without departing from the spirit and the scope of the invention.

Claims
  • 1. A train control system comprising a robust system processor, the train control system comprising: a train set including at least one railway car;a track switch controller;at least one first set of two track points located along a first track switch section;at least one second set of two track points located along a second track switch section coupled via a track section to the first track switch section;at least one RFID tag having no preprogrammed data and which is located at each of at least the one first set of two track points configured to store dynamic and static characteristics of a train set as it passes the at least one first set of two track points, wherein the dynamic characteristics stored on the at least one RFID tag are configured to be updated at the at least one first set of two track points, according to characteristics of the train set passing by the at least one first set of two track points;the at least one second RFID tag having no preprogrammed data and which is located at each of the at least one first set of two track points and the at least one second set of two track points, the at least one RFID tag being configured to store dynamic and static characteristics of the train set as it passes the at least one second set of the at least two track switches;at least one RFID tag reader located on at least one railway car connected to a network, wherein the at least one railway car writes data to the at least one RFID tag such that the data is read by the at least one RFID tag reader of a following railway car, and wherein the data of the at least one RFID tag is overwritten with new data each time at least one railway car passes by the at least one first set of two track points and as it passes by the at least one second set of the two track points; andthe robust system processor comprising: three parallel processors each configured to process in parallel an input and emit an output, wherein each of the three parallel processors includes a reconciler that is configured to: compare outputs of the three parallel processors;determine whether at least two of the outputs of the three parallel processors are equal;in response to a determination that the at least two of the outputs are equal, validate the at least two of the outputs; andcommunicate the at least two of the outputs as a majority output via a network to at least one second system processor; andin response to a determination that the at least two of the outputs are not equal, adjust a non-majority output of the outputs to the majority output.
  • 2. The system processor of claim 1, wherein the robust system processor and the at least one second system processor are combined to form a system architecture, andwherein each of the three parallel processors of the robust system processor are arranged in the system architecture to be interconnected to form an array of three columns, with a number of rows equal in number to a number of functions that need to be performed by the three parallel processors, in which each row is representative of a process, and a number of columns is equal to a number of the three parallel processors independently performing that process.
  • 3. The system processor of claim 2, wherein the number of columns equals 2n+1, where n is any positive integer.
  • 4. The system processor of claim 2, wherein row processors are interconnected by three buses for data communication between the row processors, andwherein in response to a determination that a row is using parallel buses, a bus width is equal to a processor data size with each bus being exclusive to one row.
  • 5. The system processor of claim 2, wherein each row processor connects to at least one of a processor row above and a processor row below, using separate buses for up and down connections.
  • 6. The system processor of claim 2, wherein the array accepts inputs and provides outputs to a common bus along at least one of a top and a bottom of the array.
  • 7. The system processor of claim 2, wherein each row of the array has an identity bus (UD).
  • 8. The system processor of claim 2, wherein a non-maskable interrupt line (Reset) of each of the three parallel processors is connected to an integrator (an RC network) such that manufacturing tolerances of the RC network cause each of the three parallel processors to start after a random number of clock cycles to make row processors start up at different times.
  • 9. The system processor of claim 2, wherein: during every initial power on and hard reset process of the array, every processor of the three parallel processors in the array takes a first available ID line on an ID bus,processor IDs are assigned one by one based on the different start times, until all of the three parallel processors have an assigned Processor ID, andeach of the processor IDs are non-sequential or based on a physical location or a connection of each processor of the three parallel processors.
  • 10. The system processor of claim 9, wherein: after each of the three parallel processors has obtained a processor ID of the processor IDs, each of the three parallel processors determines if at least two other processors of the three parallel processors are active in a same row of the array; andin the case it is determined there are the at least two other processors of the three parallel processors active in the same row, a processor of the three parallel processors performs its processing function using input data received from a row above or a row below as it is programmed to do.
  • 11. The system processor of claim 2, wherein when input data is received from a processor of the three parallel processors in a row above or a row below, the processor of the three parallel processors validates via row buses that data from an adjacent processor above or below is identical to the data received by the active processors in its own row.
  • 12. The system processor of claim 11, wherein the processor of the three parallel processors performs the designated row function on its input data, and upon completion, broadcasts its output data via the row buses.
  • 13. The system processor of claim 12, wherein: on receipt of the output data on a row bus of the row buses, the row bus validates the output data by checking that it is identical to output data on at least one other row bus of the row buses,in the case the output data is identical to the output data on the at least one other row bus, the output data is stored in a validation table, and after the output data is received from at least two row processors, a third row processor compares its own output data to the data stored in the validation table, and the received values in the validation table are then compared to identify a majority identical data, which is then compared to the data of the processor, in the case the processor output matches the majority of the validation table, then the processor output is considered a valid result, andin the case the processor output does not match the majority of the validation table, the processor replaces its own output data with the majority data value.
  • 14. The system processor of claim 12, wherein when one or more of a top and a bottom of the row buses are operating as input busses, all row processors are connected to receive the inputs simultaneously.
  • 15. The system processor of claim 12, wherein when one or more of a top and a bottom of the row buses are operating as output busses being driven by row processors, only a processor of the three parallel processors associated with a lowest ID that is active is connected to an output bus, and all other processors of the three parallel processors remain in a non-active state.
CLAIM OF PRIORITY

This application is a CIP of U.S. patent application Ser. No. 15/992,883 filed May 30, 2018, which is a Continuation of non-provisional U.S. patent application Ser. No. 15/878,157 filed Jan. 23, 2018, the contents of which are incorporated herein by reference in their entirety.

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20200130716 A1 Apr 2020 US
Continuations (1)
Number Date Country
Parent 15878157 Jan 2018 US
Child 15992883 US
Continuation in Parts (1)
Number Date Country
Parent 15992883 May 2018 US
Child 16723261 US