Patent Application
20140188264
Wafer processing involves several steps, which may include multiple workstations and multiple operators or technicians. When a wafer is diced or separated into multiple coupons or chips, each diced coupon or chip may also undergo several processing steps, which may include multiple workstations and multiple operators. In addition, during research experiments on a coupon or substrate through combinatorial processing techniques, the coupon or substrate may be exposed to multiple processes that require exposure to multiple processing tools and characterization using metrology tools. Tracking each variable for a conventional or combinatorial process work flow becomes more difficult as the substrate or coupon proceeds through the process flow.
Methods of recording each variable of each processing step has been achieved using handwritten logs and/or using computerized plots or spreadsheets. However, manually recording each variable for each processing step for each coupon or substrate is very labor intensive and is prone to human errors and omissions. Therefore, there is a need in the art for a solution which overcomes these drawbacks.
In some embodiments, methods of managing semiconductor workflow are described. A unique wafer tracking identifier is assigned to a semiconductor substrate. Multiple regions of the semiconductor substrate are independently processed in a combinatorial manner. The semiconductor substrate is tracked during any stage of the independent processing, via the unique wafer tracking identifier. In some embodiments, the method is embodied as program instructions on a computer readable medium.
In some embodiments, a method of identifying and tracking semiconductor processing is described. An experiment is designed for each process of a semiconductor substrate, which are independently implemented on respective multiple regions of the semiconductor substrate. A unique identifier is assigned to the semiconductor substrate. The respective design of experiment is implemented for each of the processes of the semiconductor substrate. Process criteria for each process is recorded, where the recording is associated with the assigned unique identifier. Process information is retrieved for each process, via respective assigned unique identifier.
The described embodiments and the advantages thereof may best be understood by reference to the following description taken in conjunction with the accompanying drawings. These drawings in no way limit any changes in form and detail that may be made to the described embodiments by one skilled in the art without departing from the spirit and scope of the described embodiments.
Semiconductor manufacturing may include a series of processing steps such as cleaning, surface preparation, deposition, patterning, etching, thermal annealing, and other related unit processing steps. The precise sequencing and integration of the unit processing steps enables the formation of functional devices meeting desired performance metrics such as efficiency, power production, and reliability.
As part of the discovery, optimization, and qualification of each unit process, it is desirable to be able to i) test different materials, ii) test different processing conditions within each unit process module, iii) test different sequencing and integration of processing modules within an integrated processing tool, iv) test different sequencing of processing tools in executing different process sequence integration flows, and combinations thereof in the manufacture of devices, such as integrated circuits. In particular, there is a need to be able to test i) more than one material, ii) more than one processing condition, iii) more than one sequence of processing conditions, iv) more than one process sequence integration flow, and combinations thereof, collectively known as “combinatorial process sequence integration,” on a single monolithic substrate without the need of consuming the equivalent number of monolithic substrates per material(s), processing condition(s), sequence(s) of processing conditions, sequence(s) of processes, and combinations thereof. This can greatly improve both the speed and reduce the costs associated with the discovery, implementation, optimization, and qualification of material(s), process(es), and process integration sequence(s) required for manufacturing.
Systems and methods for High Productivity Combinatorial (HPC) processing are described in U.S. Pat. No. 7,544,574 filed on Feb. 10, 2006, U.S. Pat. No. 7,824,935 filed on Jul. 2, 2008, U.S. Pat. No. 7,871,928 filed on May 4, 2009, U.S. Pat. No. 7,902,063 filed on Feb. 10, 2006, and U.S. Pat. No. 7,947,531 filed on Aug. 28, 2009 which are all herein incorporated by reference. Systems and methods for HPC processing are further described in U.S. patent application Ser. No. 11/352,077 filed on Feb. 10, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/419,174 filed on May 18, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/674,132 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005, and U.S. patent application Ser. No. 11/674,137 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005 which are all herein incorporated by reference.
HPC processing techniques have been successfully adapted to wet chemical processing, such as etching and cleaning. HPC processing techniques have also been successfully adapted to deposition processes, such as physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD).
For example, thousands of materials are evaluated during a materials discovery stage 102. Materials discovery stage 102 is also known as a primary screening stage, performed using primary screening techniques. Primary screening techniques may include dividing substrates into coupons and depositing materials using varied processes. The materials are then evaluated and promising candidates are advanced to the secondary screen, such as a materials and process development stage 104. Evaluation of the materials is performed using metrology tools such as electronic testers and imaging tools, e.g. microscopes.
The materials and process development stage 104 may evaluate hundreds of materials (i.e., a magnitude smaller than the primary stage) and may focus on the processes used to deposit or develop those materials. Promising materials and processes are again selected and advanced to the tertiary screen, such as a process integration stage 106, where tens of materials and/or processes and combinations are evaluated. The tertiary screen or process integration stage 106 may focus on integrating the selected processes and materials with other processes and materials.
The most promising materials and processes from the tertiary screen are advanced to device qualification stage 108. In device qualification stage 108, the materials and processes selected are evaluated for high volume manufacturing, which normally is conducted on full substrates within production tools, but need not be conducted in such a manner. The results are evaluated to determine the efficacy of the selected materials and processes. If successful, the use of the screened materials and processes can proceed to pilot manufacturing stage 110.
The schematic diagram 100 is an example of various techniques that may be used to evaluate and select materials and processes for the development of new materials and processes. The descriptions of primary, secondary, etc. screening and the various stages, 102-110 are arbitrary and the stages may overlap, occur out of sequence, or be described and performed in many other ways.
The embodiments described herein enable the application of combinatorial techniques to process sequence integration in order to arrive at a globally optimal sequence of semiconductor manufacturing operations by considering interaction effects between the unit manufacturing operations, the process conditions used to effect such unit manufacturing operations, hardware details used during the processing, as well as materials characteristics of components utilized within the unit manufacturing operations. Rather than just considering a series of local optimums, i.e., where the best conditions and materials for each manufacturing unit operation is considered in isolation, the embodiments described herein consider interaction effects introduced due to the multitude of processing operations that are performed and the order in which such multitude of processing operations are performed when fabricating a device. A global optimum sequence order is therefore derived and as part of this derivation, the unit processes, unit process parameters, and materials used in the unit process operations of the optimum sequence order are also considered.
The embodiments described further analyze a portion or sub-set of the overall process sequence used to manufacture a semiconductor device. Once the subset of the process sequence is identified for analysis, combinatorial process sequence integration testing is performed to optimize the materials, unit processes, hardware details, and process sequence used to build that portion of the device or structure. During the processing of some embodiments described herein, structures are formed on the processed substrate, which are equivalent to the structures formed during actual production of the semiconductor device. For example, such structures may include, but would not be limited to, contact layers, buffer layers, absorber layers, or any other series of layers or unit processes that create an intermediate structure found on semiconductor devices. While the combinatorial processing varies certain materials, unit processes, hardware details, or process sequences, the composition or thickness of the layers or structures or the action of the unit process, such as cleaning, surface preparation, deposition, surface treatment, etc. is substantially uniform through each discrete region. Furthermore, while different materials or unit processes may be used for corresponding layers or steps in the formation of a structure in different regions of the substrate during the combinatorial processing, the application of each layer or use of a given unit process is substantially consistent or uniform throughout the different regions in which it is intentionally applied. Thus, the processing is uniform within a region (inter-region uniformity) and between regions (intra-region uniformity), as desired. It should be noted that the process can be varied between regions, for example, where a thickness of a layer is varied or a material may be varied between the regions, etc., as desired by the design of the experiment.
The result is a series of regions on the substrate that contain structures or unit process sequences that have been uniformly applied within that region and, as applicable, across different regions. This process uniformity allows comparison of the properties within and across the different regions such that the variations in test results are due to the varied parameter (e.g., materials, unit processes, unit process parameters, hardware details, or process sequences) and not the lack of process uniformity. In the embodiments described herein, the positions of the discrete regions on the substrate can be defined as needed, but are preferably systematized for ease of tooling and design of experimentation. In addition, the number, variants, and location of structures within each region are designed to enable valid statistical analysis of the test results within each region and across regions to be performed.
The system 200 of
It should be appreciated that various other combinations of conventional and combinatorial processes can be included in the processing sequence with regard to
Under combinatorial processing operations, the processing conditions at different regions can be controlled independently. Consequently, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, deposition order of process materials, process sequence steps, hardware details, etc., can be varied from region to region on the substrate. Thus, for example, when exploring materials, a processing material delivered to a first and second region can be the same or different. If the processing material delivered to the first region is the same as the processing material delivered to the second region, this processing material can be offered to the first and second regions on the substrate at different concentrations. In addition, the material can be deposited under different processing parameters. Parameters which can be varied include, but are not limited to, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, atmospheres in which the processes are conducted, an order in which materials are deposited, hardware details of the gas distribution assembly, etc. It should be appreciated that these process parameters are exemplary and are not meant to be an exhaustive list, as other process parameters used in semiconductor manufacturing may be varied.
As mentioned above, within a region, the process conditions are substantially uniform, in contrast to gradient processing techniques which rely on the inherent non-uniformity of the material deposition. That is, the embodiments described herein may locally perform the processing in a conventional manner, e.g., substantially consistent and substantially uniform, while globally over the substrate, the materials, processes, and process sequences may vary. Thus, the testing will find optimums without interference from process variation differences between processes that are meant to be the same. It should be appreciated that a region may be adjacent to another region in one embodiment or the regions may be isolated and therefore, non-overlapping. When the regions are adjacent, there may be a slight overlap wherein the materials or precise process interactions are not known; however, a portion of the regions, normally at least 50% or more of the area, is uniform and all testing occurs within that region. Further, the potential overlap is only allowed with material of processes that will not adversely affect the result of the tests. Both types of regions are referred to herein as regions or discrete regions.
Methods for monitoring and tracking semiconductor processing, such as cleaning, surface preparation, deposition, patterning, etching, thermal annealing, and any other processing operation from the original wafer to each of the final diced coupons are described. Process variables, such as materials, environmental conditions, operating set points, equipment, operator, time, priority, changes made, and errors encountered are recorded for each wafer, coupon, or substrate at each level of processing.
Embodiments of the invention enable a process user to define a workflow sequence without any restriction on the number of steps, experimental conditions, type and number of HPC tools, etc. Substrate identifiers are created automatically for each substrate, enabling the user to track the progress of the processing of the substrate from a central location. Enhanced data integrity is provided, as controls are in place for revision and updating of the file. Opening multiple file copies at the same time is avoided.
A custom identifier is associated with each wafer, coupon, or substrate, and the custom identifier remains with its associated wafer, coupon, or substrate throughout all stages of processing. The recorded process variables pertain to actual real-time processing, as well as processing to be carried out for each sample at each level of processing. Any stage of the processing for any level can be tracked, via unique tracking identifiers for each sample or group of samples processed together.
In some embodiments, custom identifiers enable tracking even if an initial wafer or substrate is separated or diced. An initial wafer or substrate may have a custom identifier, such as a two-dimensional or three-dimensional bar code, assigned thereto. At a later stage of processing, the wafer may be separated into a plurality of coupons. Each coupon may have the parent wafer custom identifier, in addition to a unique coupon identifier. The format of each divided coupon identifier may be: parent#/coupon1#, parent#/coupon2#, parent#/coupon3#, etc. Where the parent#/coupon2# is further divided into multiple sub-coupons, each sub-coupon may have the parent wafer custom identifier and the coupon2 custom identifier, in addition to a unique sub-coupon identifier. As a result, each sub-coupon may have the unique identifier format of: parent#/coupon2#/sub-coupon1#, parent#/coupon2#/sub-coupon2#, parent#/coupon2#/sub-coupon3#, etc. Any other formatting scheme that provides identification of an original sample with subsequent separation into multiple sub-samples is contemplated by the embodiments described herein.
The data warehouse 510 comprises multiple modules, as illustrated in
As an example of HPC processing using embodiments, a deposition DOE may contain step-by-step instructions for depositing a dielectric layer on a semiconductor sample or region of the semiconductor sample, as well as criteria for the raw materials used, the method of deposition, and all operating temperatures and conditions. Additional DOEs would be created for each deposition layer for the semiconductor sample and/or region of the semiconductor sample. One or more DOEs would also be created for each of the other processes for the semiconductor wafer, coupon, or substrate, i.e., cleaning, surface preparation, patterning, etching, thermal annealing, etc. The individual DOEs may be stored in the DOE module 520.
A unique bar code or custom identifier is assigned to each wafer or substrate and the identifier is stored in the bar code module 530. Any bar-coding system could be utilized for assigning a unique bar code, such as a two-dimensional bar code or a three-dimensional bar code. Some embodiments use a three-dimensional bar code, since much more information can be associated with a three-dimensional bar code. The unique bar code assigned to each semiconductor sample remains with the particular semiconductor sample from the start of processing through final processing. The unique bar code can be produced via an input/output component 560, such as a scanner having label output generation. The unique bar code label can be physically associated with a sample or group of samples in various ways, such as affixing the label to the individual samples or a container in which multiple group processed samples are held. The unique bar code can also be associated with a sample or group of samples through other means, such as laser marking, etching, etc.
The resulting data associated with each stage of processing a semiconductor sample is stored in the processing data module 540. Processing criteria include, but are not limited to materials, equipment, operator, time, priority, changes made, errors encountered, etc. The processing criteria can be the same or can vary for each DOE and the DOE can have variables or parameters varied between regions of the semiconductor sample being processed. The DOE module 520, the bar code module 530, and the processing data module 540 of the data warehouse 510 are all interconnected, such as through multiple software pointers in some embodiments.
A semiconductor wafer, coupon, or substrate is processed through multiple stages, such as the stages of cleaning, surface preparation, deposition, patterning, etching, thermal annealing, etc. When a semiconductor sample enters a processing stage, the unique bar code is scanned, i.e., read by an input/output component 560. The unique bar code can be scanned using a combination of a device capable of recognizing the particular two-dimensional or three-dimensional bar code and associated software. All data that has been recorded up to that point has been stored in the processing data module 540 and can be accessed by scanning the bar code. The processing of scanning and data retrieval is controlled by a server 550, such as a relational database management system in some embodiments.
The following example discusses an embodiment for illustrative purposes. If the semiconductor sample has entered the first stage of processing, then the DOE may be the only recorded data at that point. As the sample proceeds through the first stage of processing, all criteria relating to the first stage of processing is recorded, such as materials and equipment used, operator, time, priority, changes made from the DOE, and errors encountered, as well as any other relevant factors that should be noted. In some embodiments, the sample is scanned prior to each stage and at the conclusion of each stage, however, this is not meant to be limiting as the sample scanning points can be set based on a particular application. When the sample enters the second stage of processing, the unique bar code of the semiconductor sample is scanned again. All data pertaining to the DOE and the first stage of processing for that sample may be retrieved upon the second stage scanning Again, all criteria relating to the second stage of processing is recorded, which is associated with the same unique bar code for that particular sample. A similar process of scanning and recording continues for all processing stages for the particular semiconductor processed sample. When a sample or group of samples is completely processed, all processing data may be retrieved for the sample or group of samples by scanning its unique bar code. Some embodiments provide a filtering component to search for samples during processing, according to one or more particular processing criteria.
An additional embodiment of the method of identifying and tracking semiconductor processing 900 includes separating the semiconductor substrate into multiple coupons. Each coupon comprises multiple discrete regions, which may be processed independently in a combinatorial manner, according to one or more embodiments described above. A unique identifier is assigned to each coupon. A status of each of the coupons may be tracked via their respective assigned unique identifiers. The status of workflow execution or data capture can be tracked and is accessible to a user through the embodiments described herein. It should be appreciated that the instructions for each flowchart of
Although the foregoing embodiments of the invention have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims. In the claims, elements and/or steps do not imply any particular order of operation, unless explicitly stated in the claims.
