Claims
- 1. A semiconductor wafer, comprising:
- a top surface on which a semiconductor circuit pattern is to be fabricated at a first predetermined pitch; and
- a bottom surface on which a plurality of alignment marks for positioning said semiconductor circuit pattern are arranged at a second predetermined pitch;
- wherein said second predetermined pitch is unrelated to the first predetermined pitch.
- 2. A semiconductor wafer according to claim 1, wherein said alignment marks are arranged two-dimensionally on said bottom surface.
- 3. A semiconductor wafer according to claim 1, wherein said top surface is a polished surface.
- 4. A method for fabricating a semiconductor wafer, comprising the steps of:
- preparing a semiconductor substrate having a top surface and a bottom surface; and
- forming a plurality of marks on said bottom surface in accordance with a desired arrangement for positioning a semiconductor circuit pattern to be formed on said top surface;
- wherein the desired arrangement has a predetermined pitch that is unrelated to a pitch of the semiconductor circuit pattern to be formed.
- 5. A method for fabricating a semiconductor wafer according to claim 4, wherein said alignment marks are arranged two-dimensionally on said bottom surface.
- 6. A method for fabricating a semiconductor wafer according to claim 4, further comprising a step of polishing said top surface.
- 7. A semiconductor wafer comprising:
- a top surface on which a plurality of semiconductor circuit chips are to be formed at a first predetermined pitch; and
- a bottom surface on which alignment marks for positioning said semiconductor chips are arranged at a second predetermined pitch;
- wherein said second predetermined pitch differs from the first predetermined pitch.
- 8. A semiconductor wafer according to claim 7, wherein said alignment marks are arranged two-dimensionally on said bottom surface.
- 9. A semiconductor wafer comprising:
- a top surface on which a plurality of semiconductor circuit chips are to be formed with a plurality of shot areas having a predetermined first arrangement; and
- a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement;
- wherein said second arrangement is unrelated to said first arrangement.
- 10. A semiconductor wafer according to claim 9, wherein said alignment marks are arranged two-dimensionally on said bottom surface.
- 11. A semiconductor wafer comprising:
- a top surface on which a plurality of semiconductor circuit chips are to be formed with a plurality of shot areas having a predetermined first arrangement; and
- a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement;
- wherein said second arrangement differs from said first arrangement.
- 12. A semiconductor wafer according to claim 11, wherein said alignment marks are arranged two-dimensionally on said bottom surface.
- 13. A workpiece comprising:
- a top surface on which a plurality of first patterns are to be formed with a plurality of shot areas having a predetermined first arrangement; and
- a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement;
- wherein said second arrangement is unrelated to said first arrangement.
- 14. A workpiece comprising:
- a top surface on which a plurality of first patterns are to be formed with a plurality of shot areas having a predetermined first arrangement; and
- a bottom surface on which a plurality of alignment marks for positioning said plurality of shot areas are provided at a predetermined second arrangement;
- wherein said second arrangement differs from said first arrangement.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2-192946 |
Jul 1990 |
JPX |
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Parent Case Info
This application is a divisional application of Ser. No. 07/734,159, filed Jul. 22, 1991, and now U.S. Pat. No. 5,200,798.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4952060 |
Ina et al. |
Aug 1990 |
|
5127733 |
Allgauga |
Jul 1992 |
|
5200798 |
Katagiri et al. |
Apr 1993 |
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Divisions (1)
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Number |
Date |
Country |
Parent |
734159 |
Jul 1991 |
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