Abraham F. Yee

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Process for manufacturing a printed circuit board having high densi...
- Patent number 10,219,387
- Issue date Feb 26, 2019
- NVIDIA Corporation
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Thermal performance of logic chip in a package-on-package structure
- Patent number 10,096,534
- Issue date Oct 9, 2018
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package structure
- Patent number 10,032,692
- Issue date Jul 24, 2018
- NVIDIA Corporation
- Shantanu Kalchuri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried TSVs used for decaps
- Patent number 9,831,184
- Issue date Nov 28, 2017
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stiffening electronic packages by disposing a stiffener ring betwee...
- Patent number 9,760,132
- Issue date Sep 12, 2017
- NVIDIA Corporation
- Leilei Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System with a high power chip and a low power chip having low inter...
- Patent number 9,728,481
- Issue date Aug 8, 2017
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Open solder mask and or dielectric to increase lid or ring thicknes...
- Patent number 9,716,051
- Issue date Jul 25, 2017
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System, method, and computer program product for a cavity package-o...
- Patent number 9,659,815
- Issue date May 23, 2017
- NVIDIA Corporation
- Ronilo V. Boja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for controlling a semiconductor fabrication process
- Patent number 9,570,284
- Issue date Feb 14, 2017
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-profile chip package with modified heat spreader
- Patent number 9,530,714
- Issue date Dec 27, 2016
- NVIDIA Corporation
- Shantanu Kalchuri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Decoupling capacitors for interposers
- Patent number 9,379,202
- Issue date Jun 28, 2016
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Absorbing excess under-fill flow with a solder trench
- Patent number 9,368,422
- Issue date Jun 14, 2016
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System, method, and computer program product for affixing a post to...
- Patent number 9,087,830
- Issue date Jul 21, 2015
- NVIDIA Corporation
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Buried TSVs used for decaps
- Patent number 8,618,651
- Issue date Dec 31, 2013
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for controlling a semiconductor fabrication process
- Patent number 7,964,422
- Issue date Jun 21, 2011
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with isolation of field oxidation by noble gas i...
- Patent number 6,093,936
- Issue date Jul 25, 2000
- LSI Logic Corporation
- Abraham Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable polysilicon gate array base cell architecture
- Patent number 5,917,207
- Issue date Jun 29, 1999
- LSI Logic Corporation
- Michael J. Colwell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic cells with bent gates and compressed minimum spacin...
- Patent number 5,874,754
- Issue date Feb 23, 1999
- LSI Logic Corporation
- Jasopin Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-rectangular MOS device configurations for gate array type integ...
- Patent number 5,796,130
- Issue date Aug 18, 1998
- LSI Logic Corporation
- Tim Carmichael
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip package with interconnect layers and routing and...
- Patent number 5,777,383
- Issue date Jul 7, 1998
- LSI Logic Corporation
- Mark P. Stager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit structure with vertical isolation from single cr...
- Patent number 5,723,896
- Issue date Mar 3, 1998
- LSI Logic Corporation
- Abraham Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a gate array integrated circuit including int...
- Patent number 5,721,151
- Issue date Feb 24, 1998
- LSI Logic Corporation
- Gobi Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a programmable polysilicon gate array base ce...
- Patent number 5,691,218
- Issue date Nov 25, 1997
- LSI Logic Corporation
- Michael J. Colwell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a CMOS dynamic random-access memory (DRAM)
- Patent number 5,679,598
- Issue date Oct 21, 1997
- LSI Logic Corporation
- Abraham Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a CMOS dynamic random-access memory (DRAM)
- Patent number 5,648,290
- Issue date Jul 15, 1997
- LSI Logic Corporation
- Abraham Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for protecting a semiconductor device with a superconductive...
- Patent number 5,644,143
- Issue date Jul 1, 1997
- LSI Logic Corporation
- Michael D. Rostoker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a CMOS dynamic random-access memory (DRAM)
- Patent number 5,622,882
- Issue date Apr 22, 1997
- LSI Logic Corporation
- Abraham Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for forming superconductive lines
- Patent number 5,593,918
- Issue date Jan 14, 1997
- LSI Logic Corporation
- Michael D. Rostoker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structure including CMOS devices protected by pa...
- Patent number 5,561,319
- Issue date Oct 1, 1996
- LSI Logic Corporation
- Alexander H. Owens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a CMOS integrated circuit with electrostatic dis...
- Patent number 5,538,907
- Issue date Jul 23, 1996
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR A CAVITY PACKAGE-O...
- Publication number 20150206848
- Publication date Jul 23, 2015
- NVIDIA Corporation
- Ronilo V. Boja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STIFFENING ELECTRONIC PACKAGES
- Publication number 20150077918
- Publication date Mar 19, 2015
- NVIDIA Corporation
- Leilei Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IINTEGRATED CIRCUIT PACKAGE USING SILICON-ON-OXIDE INTERPOSER SUBST...
- Publication number 20140339705
- Publication date Nov 20, 2014
- NVIDIA Corporation
- ABRAHAM F. YEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH AN INTERPOSER FORMED FROM A REUSABL...
- Publication number 20140339706
- Publication date Nov 20, 2014
- NVIDIA Corporation
- Abraham F. YEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE STRUCTURE
- Publication number 20140264816
- Publication date Sep 18, 2014
- NVIDIA Corporation
- Shantanu Kalchuri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BURIED TSV'S USED FOR DECAPS
- Publication number 20140239444
- Publication date Aug 28, 2014
- NVIDIA Corporation
- ABRAHAM F. YEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR MANUFACTURING A PRINTED CIRCUIT BOARD HAVING HIGH DENSI...
- Publication number 20140208590
- Publication date Jul 31, 2014
- NVIDIA Corporation
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
STRIPLINE AND REFERENCE PLANE IMPLEMENTATION FOR INTERPOSERS USING...
- Publication number 20140175619
- Publication date Jun 26, 2014
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ABSORBING EXCESS UNDER-FILL FLOW WITH A SOLDER TRENCH
- Publication number 20140175681
- Publication date Jun 26, 2014
- NVIDIA Corporation
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW-PROFILE CHIP PACKAGE WITH MODIFIED HEAT SPREADER
- Publication number 20140167216
- Publication date Jun 19, 2014
- NVIDIA Corporation
- Shantanu KALCHURI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL THROUGH-SILICON VIA CONSTRUCTION
- Publication number 20140151892
- Publication date Jun 5, 2014
- NVIDIA Corporation
- Teckgyu Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SERVER PROCESSING MODULE
- Publication number 20140138815
- Publication date May 22, 2014
- NVIDIA Corporation
- ABRAHAM F. YEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DECOUPLING CAPACITORS FOR INTERPOSERS
- Publication number 20140131834
- Publication date May 15, 2014
- NVIDIA Corporation
- ABRAHAM F. YEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMAL PERFORMANCE OF LOGIC CHIP IN A PACKAGE-ON-PACKAGE STRUCTURE
- Publication number 20140131847
- Publication date May 15, 2014
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF EMBEDDING CPU/GPU/LOGIC CHIP INTO A SUBSTRATE OF A PACKAG...
- Publication number 20140133105
- Publication date May 15, 2014
- NVIDIA Corporation
- Abraham F. Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPEN SOLDER MASK AND OR DIELECTRIC TO INCREASE LID OR RING THICKNES...
- Publication number 20140124913
- Publication date May 8, 2014
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-SOLDER MASK DEFINED COPPER PAD AND EMBEDDED COPPER PAD TO REDUC...
- Publication number 20140124254
- Publication date May 8, 2014
- NVIDIA Corporation
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY 3D PACKAGE
- Publication number 20130277855
- Publication date Oct 24, 2013
- Terry (Teckgyu) Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PREPARING A SUBSTR...
- Publication number 20130256873
- Publication date Oct 3, 2013
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONTROLLING WARPIN...
- Publication number 20130251967
- Publication date Sep 26, 2013
- NVIDIA Corporation
- Leilei Zhang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR AFFIXING A POST TO...
- Publication number 20130252414
- Publication date Sep 26, 2013
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM WITH A HIGH POWER CHIP AND A LOW POWER CHIP HAVING LOW INTER...
- Publication number 20130058067
- Publication date Mar 7, 2013
- Abraham F. YEE
- H01 - BASIC ELECTRIC ELEMENTS

Abraham F. Yee

Person

Patents Grantslast 30 patents

Process for manufacturing a printed circuit board having high densi...

Thermal performance of logic chip in a package-on-package structure

Semiconductor package structure

Buried TSVs used for decaps

Stiffening electronic packages by disposing a stiffener ring betwee...

System with a high power chip and a low power chip having low inter...

Open solder mask and or dielectric to increase lid or ring thicknes...

System, method, and computer program product for a cavity package-o...

Method and system for controlling a semiconductor fabrication process

Low-profile chip package with modified heat spreader

Decoupling capacitors for interposers

Absorbing excess under-fill flow with a solder trench

System, method, and computer program product for affixing a post to...

Buried TSVs used for decaps

Method and system for controlling a semiconductor fabrication process

Integrated circuit with isolation of field oxidation by noble gas i...

Programmable polysilicon gate array base cell architecture

Microelectronic cells with bent gates and compressed minimum spacin...

Non-rectangular MOS device configurations for gate array type integ...

Semiconductor chip package with interconnect layers and routing and...

Integrated circuit structure with vertical isolation from single cr...

Method of fabricating a gate array integrated circuit including int...

Method of fabricating a programmable polysilicon gate array base ce...

Method of making a CMOS dynamic random-access memory (DRAM)

Method of making a CMOS dynamic random-access memory (DRAM)

Method for protecting a semiconductor device with a superconductive...

Method of making a CMOS dynamic random-access memory (DRAM)

Techniques for forming superconductive lines

Integrated circuit structure including CMOS devices protected by pa...

Method for forming a CMOS integrated circuit with electrostatic dis...

Patents Applicationslast 30 patents

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR A CAVITY PACKAGE-O...

STIFFENING ELECTRONIC PACKAGES

IINTEGRATED CIRCUIT PACKAGE USING SILICON-ON-OXIDE INTERPOSER SUBST...

INTEGRATED CIRCUIT PACKAGE WITH AN INTERPOSER FORMED FROM A REUSABL...

SEMICONDUCTOR PACKAGE STRUCTURE

BURIED TSV'S USED FOR DECAPS

PROCESS FOR MANUFACTURING A PRINTED CIRCUIT BOARD HAVING HIGH DENSI...

STRIPLINE AND REFERENCE PLANE IMPLEMENTATION FOR INTERPOSERS USING...

ABSORBING EXCESS UNDER-FILL FLOW WITH A SOLDER TRENCH

LOW-PROFILE CHIP PACKAGE WITH MODIFIED HEAT SPREADER

THREE DIMENSIONAL THROUGH-SILICON VIA CONSTRUCTION

SERVER PROCESSING MODULE

DECOUPLING CAPACITORS FOR INTERPOSERS

THERMAL PERFORMANCE OF LOGIC CHIP IN A PACKAGE-ON-PACKAGE STRUCTURE

METHOD OF EMBEDDING CPU/GPU/LOGIC CHIP INTO A SUBSTRATE OF A PACKAG...

OPEN SOLDER MASK AND OR DIELECTRIC TO INCREASE LID OR RING THICKNES...

NON-SOLDER MASK DEFINED COPPER PAD AND EMBEDDED COPPER PAD TO REDUC...

HIGH DENSITY 3D PACKAGE

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PREPARING A SUBSTR...

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONTROLLING WARPIN...

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR AFFIXING A POST TO...

SYSTEM WITH A HIGH POWER CHIP AND A LOW POWER CHIP HAVING LOW INTER...