Patent Application
20140138815
1. Field of the Invention
The present invention generally relates to integrated circuit packaging, and, more specifically, to processing module packaging.
2. Description of the Related Art
Integrated circuit (IC) fabrication is a multi-step sequence which includes processes such as patterning, deposition, etching, and metallization. Typically, in the final processing steps, the resulting IC die are separated and packaged. IC packaging serves several purposes, including providing an electrical interface with the die, providing a thermal medium through which heat may be removed from the die, and/or providing mechanical protection for the die during subsequent usage and handling.
One type of IC packaging technique is referred to as “flip chip” packaging. In flip chip packaging, after the metallization process is complete, solder bump structures (e.g., solder balls, pads, etc.) are deposited on the die, and the die is separated from the wafer (e.g., via dicing, cutting, etc.). The die is then inverted and positioned on a substrate so that the solder bumps align with electrical connections formed on the substrate. Heat is applied via a solder reflow process to re-melt the solder bumps and attach the die to the substrate. The die/substrate assembly may further be underfilled with a non-conductive adhesive to strengthen the mechanical connection between the die and the substrate.
Over the past decade, datacenters have experienced unprecedented growth as the popularity of Internet-related products and services has increased. However, as providers seek to further increase the processing and storage capacities of datacenters and servers, they confront many obstacles, including increased power consumption and thermal management requirements. Moreover, such datacenters may include tens of thousands of processors and memory devices, each of which must be provided with proper electrical connections and sufficient heat removal. Thus, as the scale of datacenters continues to increase, the complexity, size, and thermal requirements of server components is quickly becoming a limiting factor.
Accordingly, there is a need in the art for a more effective way of providing server component packaging.
One embodiment of the present invention sets forth a processing module including an interposer and a plurality of processing nodes. The interposer includes a plurality of through substrate vias. Each processing node includes a processing unit die coupled directly to a top surface of the interposer with a first plurality of solder bump structures, a memory die coupled directly to the top surface of the interposer with a second plurality of solder bump structures, and a plurality of circuit elements electrically coupling the processing unit die and the memory die. The processing module further includes a plurality of electrical connections formed on a bottom surface of the interposer and electrically coupled to the plurality of processing nodes through the plurality of through substrate vias. The processing module further comprises a plurality of interconnecting circuit elements electrically interconnecting the plurality of processing nodes.
Further embodiments provide a method of fabricating a processing module.
One advantage of the disclosed technique is that a plurality of processing nodes may be disposed on a single interposer wafer, simplifying the fabrication and packaging processes, streamlining thermal management, and allowing a greater number of processing and memory die to be included in a smaller processing module.
So that the manner in which the above recited features of the invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of skill in the art that the present invention may be practiced without one or more of these specific details.
A network-on-chip (NoC) controller 118 provides communication between the streaming multiprocessors 116 and cache memory 120 included in each processing unit 110 via circuit elements 130. Each processing unit 110 further communicates with the DRAM memory units 112 and the nonvolatile memory unit 114 via a memory controller 122. An addressing unit 124 selects streaming multiprocessors 116 for input/output operations. Finally, a network interface controller 126 provides communication between each processing node 106 and the cabinet interconnect 103.
The exemplary processing system 100 illustrated in
The interposer 310 may comprise a silicon wafer having a silicon layer 311 and a redistribution layer 313 and having a thickness of approximately 10 μm to approximately 500 μm. In the exemplary embodiment illustrated in
Each of the processing unit die 302, 304 and memory die 306 may be coupled to the top surface of the interposer 310 with a plurality of solder bump structures 314. The solder bump structures 314 may include, for example, solder balls, solder pads, or any other type of structures capable of mechanically and/or electrically coupling integrated circuit die to the interposer 310. The solder bump structures 314 may be attached directly to the processing unit die 302, 304 or memory die 306, or the solder bump structures 314 may couple to under bump metallurgy (UBM) pads disposed on the die. Further, the solder bump structures 314 may couple the processing unit die 302, 304 and memory die 306 directly to the through substrate vias 312, or the processing unit die 302, 304 and memory die 306 may be indirectly coupled to the through substrate vias 312 with intermediate circuit elements 130, as described below with respect to
As shown in
Prior to mounting the heat sink 330, the processing unit die 302, 304 and/or memory die 306 may be underfilled and/or overmolded with a thermoset material 340, such as an epoxy, resin, or the like, to strengthen the mechanical coupling between the die and the interposer 310. After overmolding, excess material may be removed (e.g., via grinding, chemical mechanical polishing (CMP), etc.) to expose the back surfaces of the processing unit die 302, 304 and/or memory die 306. The heat sink 330 then may be mounted to the processing unit die 302, 304 and/or memory die 306, for example, by disposing a thermal interface material (TIM) on a surface between the die 302, 304, 306 and the heat sink 330.
The heat sink 330 may comprise any thermally conductive material, including metals such as copper, aluminum, and silver. Additionally, although the exemplary heat sink 330 illustrated in
Once the heat sink 330 has been mounted, the heat sink 330 may be used as a carrier during subsequent process steps. For example, the heat sink 330 may serve as a carrier by which to handle the interposer 310 when thinning the interposer 310 to expose the through substrate vias 312. After exposing the through substrate vias 312, electrical connections 322 may be disposed on the bottom surface of the interposer 310. In the exemplary embodiment illustrated in
After disposing electrical connections 322 on the bottom surface of the interposer 310, the interposer 310 and heat sink 330 assembly may be disposed on a printed circuit board (PCB) 320. The printed circuit board 320 may include various electrical components such as decoupling capacitors, power amplifiers, power regulators, rack interconnects, and other types of electrical or optical interconnects for providing communications or electrical power to the processing unit die 302, 304 and/or memory die 306. Further, the printed circuit board 320 may provide electrical connections between processing unit die 302, 304 and/or connections between different processing nodes 106, processing modules 104, and/or cabinets 102.
As discussed with respect to
In the exemplary embodiment provided herein, circuit elements 130 for 64 processing nodes 106, each having dimensions of approximately 26×32 mm, are fabricated on the interposer 310. The circuit elements 130 for each of the 64 processing nodes 106 may be fabricated by performing photolithography with the same reticle, or the circuit elements 130 may be fabricated using more than one reticle. For example, as shown in
Although this exemplary processing module 104 includes 64 processing nodes 106, any number of processing nodes (e.g., 16, 32, 128, or more) may be included in each processing module 104. Each processing node 106 includes processing unit die 302, 304 and memory die 306. Moreover, each processing node 106 may include the same type(s) of processing unit die 302, 304 and memory die 306, or each processing node 106 may include different types of processing unit die 302, 304 and memory die 306. For example, one or more processing nodes 106 may include a plurality of central processing unit die, while one or more other processing nodes 106 may include a plurality of graphics processing unit die. Furthermore, although two processing unit die 302, 304 are illustrated with respect to the exemplary embodiment described herein, each processing node 106 may include any number of processing unit die. Similarly, any number of memory die 306 and any number of other types of integrated circuit die may be included in each processing node 106. Additionally, circuit elements 130 for processing nodes 106 having larger or smaller sizes than those described with respect to the exemplary embodiment may be fabricated. Once the circuit elements 130 and through substrate vias 312 have been fabricated, the interposer 310 may be cut into an appropriate shape and size (e.g., a rectangle, square, etc.)
The method begins at step 610, where a plurality of circuit elements 130 (e.g., interconnecting circuit elements 130-1) and a plurality of through substrate vias 312 are formed on the interposer 310. As discussed above with respect to
Each processing unit die 302, 304 and/or memory die 306 may be directly coupled to the top surface of the interposer 310, or the processing unit die 302, 304 and/or memory die 306 may be coupled via an intermediate layer or structure which does not substantially affect the footprint of the processing unit die 302, 304 and memory die 306. The processing unit die 302, 304 and memory die 306 may be overmolded with a thermoset material and/or a thermal interface material. Excess overmolding material 340 may be removed via a grinding or polishing process.
Next, at step 618, a heat sink 330 may be disposed on the plurality of processing nodes 106. The heat sink 330 may contact a back surface of each processing unit die 302, 304 and/or memory die 306. Additionally, a thermal interface material may be disposed between the heat sink 330 and the processing unit die 302, 304 and/or memory die 306.
At step 620, a plurality of electrical connections 322 may be formed on a bottom surface of the interposer 310. The plurality of electrical connections 322 may electrically couple to one or more of the plurality of processing nodes 106 through the plurality of through substrate vias 312. Forming the plurality of electrical connections 322 may include thinning the bottom surface of the interposer 310. Further, forming the plurality of electrical connections 322 may include disposing ball grid array, pin grid array, or land grid array structures on the bottom surface of the interposer 310. Finally, at step 622, the interposer is electrically coupled to a printed circuit board (PCB) 320 via the plurality of electrical connections 322.
In sum, a plurality of integrated circuit (IC) die (e.g., central processing unit(s), graphics processing unit(s), memory structure(s), and/or the like) may be mounted on an interposer, such as a semiconductor wafer. The interposer may provide electrical connections between the plurality of die disposed on its surface. Additionally, the server interposer may include through-substrate vias for providing electrical connections to the circuit board on which the interposer is mounted. Finally, the backsides of the plurality of die may be covered with a thermally conductive and electrically insulating material, and a heat sink and/or carrier may be mounted on the backside of the die.
One advantage of the disclosed technique is that a plurality of processing nodes may be disposed on a single interposer wafer, simplifying the fabrication and packaging processes, streamlining thermal management, and allowing a greater number of processing and memory die to be included in a smaller processing module.
The invention has been described above with reference to specific embodiments. Persons of ordinary skill in the art, however, will understand that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The foregoing description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Therefore, the scope of embodiments of the present invention is set forth in the claims that follow.
