Brian L. Tessier

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Field effect device with reduced thickness gate
- Patent number 8,492,803
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Ricky S. Amos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a guard ring or contact to an SOI substrate
- Patent number 7,888,738
- Issue date Feb 15, 2011
- International Business Machines Corporation
- Amanda L. Tessier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device structure having low and high performance devi...
- Patent number 7,776,695
- Issue date Aug 17, 2010
- International Business Machines Corporation
- John C. Arnold
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a guard ring or contact to an SOI substrate
- Patent number 7,718,514
- Issue date May 18, 2010
- International Business Machines Corporation
- Amanda L. Tessier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly filled substrate contact on SOI structure
- Patent number 7,592,245
- Issue date Sep 22, 2009
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned dual stressed layers for NFET and PFET
- Patent number 7,485,521
- Issue date Feb 3, 2009
- International Business Machines Corporation
- Huilong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect device with reduced thickness gate
- Patent number 7,459,382
- Issue date Dec 2, 2008
- International Business Machines Corporation
- Ricky S. Amos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly filled substrate contact on SOI structure
- Patent number 7,358,172
- Issue date Apr 15, 2008
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Undercut and residual spacer prevention for dual stressed layers
- Patent number 7,244,644
- Issue date Jul 17, 2007
- International Business Machines Corporation
- Huilong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diffused extrinsic base and method for fabrication
- Patent number 6,900,519
- Issue date May 31, 2005
- International Business Machines Corporation
- Marc W. Cantell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diffused extrinsic base and method for fabrication
- Patent number 6,869,854
- Issue date Mar 22, 2005
- International Business Machines Corporation
- Marc W. Cantell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET device with in-situ doped, raised source and drain structures
- Patent number 6,858,903
- Issue date Feb 22, 2005
- International Business Machines Corporation
- Wesley C. Natzle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacture of MOSFET device with in-situ doped, raised s...
- Patent number 6,774,000
- Issue date Aug 10, 2004
- International Business Machines Corporation
- Wesley C. Natzle
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF FORMING A GUARD RING OR CONTACT TO AN SOI SUBSTRATE
- Publication number 20100109119
- Publication date May 6, 2010
- International Business Machines Corporation
- Amanda L. Tessier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A GATE STRUCTURE
- Publication number 20090311855
- Publication date Dec 17, 2009
- Richard A. Bruff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD EFFECT DEVICE WITH REDUCED THICKNESS GATE
- Publication number 20090159934
- Publication date Jun 25, 2009
- International Business Machines Corporation
- Ricky S. Amos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A GATE STRUCTURE AND THE STRUCTURE THEREOF
- Publication number 20090101980
- Publication date Apr 23, 2009
- International Business Machines Corporation
- Richard A. Bruff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A GUARD RING OR CONTACT TO AN SOI SUBSTRATE
- Publication number 20090001465
- Publication date Jan 1, 2009
- International Business Machines Corporation
- Amanda L. Tessier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE
- Publication number 20080286916
- Publication date Nov 20, 2008
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESS...
- Publication number 20080173942
- Publication date Jul 24, 2008
- International Business Machines Corporation
- Huilong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE
- Publication number 20080113507
- Publication date May 15, 2008
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE AND RELA...
- Publication number 20070281405
- Publication date Dec 6, 2007
- International Business Machines Corporation
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD EFFECT DEVICE WITH REDUCED THICKNESS GATE
- Publication number 20070221964
- Publication date Sep 27, 2007
- International Business Machines Corporation
- Ricky S. Amos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE
- Publication number 20070196963
- Publication date Aug 23, 2007
- International Business Machines Corporation
- David M. Dobuzinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVI...
- Publication number 20070158753
- Publication date Jul 12, 2007
- International Business Machines Corporation
- John C. Arnold
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNDERCUT AND RESIDUAL SPACER PREVENTION FOR DUAL STRESSED LAYERS
- Publication number 20070020838
- Publication date Jan 25, 2007
- International Business Machines Corporation
- Huilong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED DUAL STRESSED LAYERS
- Publication number 20070007552
- Publication date Jan 11, 2007
- International Business Machines Corporation
- Huilong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
A MANUFACTURABLE METHOD AND STRUCTURE FOR DOUBLE SPACER CMOS WITH O...
- Publication number 20050275034
- Publication date Dec 15, 2005
- International Business Machines Corporation
- Sadanand V. Deshpande
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOSFET DEVICE WITH IN-SITU DOPED, RAISED SOURCE AND DRAIN STRUCTURES
- Publication number 20040248368
- Publication date Dec 9, 2004
- Wesley C. Natzle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Diffused extrinsic base and method for fabrication
- Publication number 20040222495
- Publication date Nov 11, 2004
- Marc W. Cantell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of manufacture of MOSFET device with in-situ doped, raised s...
- Publication number 20040097047
- Publication date May 20, 2004
- International Business Machines Corporation
- Wesley C. Natzle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Diffused extrinsic base and method for fabrication
- Publication number 20040014271
- Publication date Jan 22, 2004
- International Business Machines Corporation
- Marc W. Cantell
- H01 - BASIC ELECTRIC ELEMENTS

Brian L. Tessier

Person

Patents Grantslast 30 patents

Field effect device with reduced thickness gate

Method of forming a guard ring or contact to an SOI substrate

Semiconductor device structure having low and high performance devi...

Method of forming a guard ring or contact to an SOI substrate

Poly filled substrate contact on SOI structure

Self-aligned dual stressed layers for NFET and PFET

Field effect device with reduced thickness gate

Poly filled substrate contact on SOI structure

Undercut and residual spacer prevention for dual stressed layers

Diffused extrinsic base and method for fabrication

Diffused extrinsic base and method for fabrication

MOSFET device with in-situ doped, raised source and drain structures

Method of manufacture of MOSFET device with in-situ doped, raised s...

Patents Applicationslast 30 patents

METHOD OF FORMING A GUARD RING OR CONTACT TO AN SOI SUBSTRATE

METHOD OF FABRICATING A GATE STRUCTURE

FIELD EFFECT DEVICE WITH REDUCED THICKNESS GATE

METHOD OF FABRICATING A GATE STRUCTURE AND THE STRUCTURE THEREOF

METHOD OF FORMING A GUARD RING OR CONTACT TO AN SOI SUBSTRATE

METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE

STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESS...

POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE

METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE AND RELA...

FIELD EFFECT DEVICE WITH REDUCED THICKNESS GATE

POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE

SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVI...

UNDERCUT AND RESIDUAL SPACER PREVENTION FOR DUAL STRESSED LAYERS

SELF-ALIGNED DUAL STRESSED LAYERS

A MANUFACTURABLE METHOD AND STRUCTURE FOR DOUBLE SPACER CMOS WITH O...

MOSFET DEVICE WITH IN-SITU DOPED, RAISED SOURCE AND DRAIN STRUCTURES

Diffused extrinsic base and method for fabrication

Method of manufacture of MOSFET device with in-situ doped, raised s...

Diffused extrinsic base and method for fabrication