SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVICES OF SAME CONDUCTIVE TYPE ON SAME SUBSTRATE

Abstract

A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 through FIG. 5 are side schematic views of sequential semiconductor device structures resulting from the various sequential steps according to one preferred embodiment of the present invention, when used to make a two device structure including two nFETs having respective channels C; the sidewall spacer SP and additional spacer RSPS have a combined maximum width W.

FIG. 6 is a diagram with explanatory legends showing a relationship between a maximum resulting stress in the channel of one device verses a combined maximum width (2w) of both additional spacers RSPS and both conventional sidewall spacers (SP), for 90 nm technology and a 50 nm 1.2 GPa stress film 30.

FIG. 7 is a side schematic view of a semiconductor device structure according to the present invention including two pFETs.

FIG. 8 is a side schematic view of an nFET according to the prior art.

Claims

1. A method for making a semiconductor device structure, comprising: providing a substrate;forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, suicides on the first gate, the second gate and respective source and drain regions;forming additional spacers on only the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

2. The method as claimed in claim 1, said step of forming additional spacers further comprising: disposing a first dielectric layer over the silicided first gate with first spacers, the silicided second gate with second spacers, silicided respective source and drain regions, and the isolation region, andcovering the first dielectric layer disposed over the silicided first gate with first spacers, the silicided respective source and drain regions adjacent to the first gate, and a portion of the isolation region, and then removing the first dielectric layer from portions of the structure not covered by said covering step.

3. The method as claimed in claim 2, said step of removing comprising anistropically etching the first dielectric layer from the portions of the structure.

4. The method as claimed in claim 2, futher comprising: uncovering the first dielectric layer disposed over the silicided first gate with spacers, and the silicided respective source and drain regions adjacent to the first gate, and the portion of the isolation region;covering the second dielectric layer disposed over the silicided second gate with second spacers, the silicided respective source and drain regions adjacent to the second gate and another portion of the isolation region; and thenremoving the first dielectric layer except from certain portions disposed on the first spacers to form the additional spacers.

5. The method as claimed in claim 3, said step of anistropically etching comprising reactive ion etching the first dielectric layer.

6. The method as claimed in claim 1, wherein the first spacers have a maximum width of not greater than 60 nanometers.

7. The method as claimed in claim 1, wherein each of the additional spacers has a maximum width selected from the group consisting of 15 nm, 30 nm and 50 nm.

8. The method as claimed in claim 1, said step of disposing further comprising depositing a stress layer selected from the group consisting essentially of silicon nitride and silicon carbide.

9. The method as claimed in claim 2, said step of disposing the first dielectric layer further comprising depositing the first dielectric layer from the group consisting essentially of silicon nitride, silicon carbide and silicon dioxide.

10. The method as claimed in claim 2, wherein the first spacers and the first dielectric layer together have a maximum thickness of not greater than 70 nm.

11. The method as claimed in claim 1, wherein the same conductive type is n-type.

12. The method as claimed in claim 1, wherein the same conductive type is p-type.

13. A semiconductor device structure, comprising: a first field effect transistor and a second field effect transistor disposed on a same substrate, the transistors being of a same conductive type and including respective sidewall spacers;additional spacers disposed only on the sidewall spacers of the first field effect transistor, and a stress film disposed on the first field effect transistor, the additional spacers and the second field effect transistor, so that a maximum stress resulting in the channel of the first field effect transistor is different than a maximum stress resulting in the channel of the second field effect transistor.

14. The semiconductor device structure as claimed in claim 13, wherein the maximum stress resulting in the channel of the first field effect transistor is less than the maximum stress resulting in the channel of the second field effect transistor.

15. The semiconductor device structure as claimed in claim 13, the first field effect transistor being a first nFET and the second field effect transistor being a second nFET.

16. The semiconductor device structure as claimed in claim 13, the first field effect transistor being a first pFET and the second field effect transistor being a second pFET.

17. The semiconductor device structure as claimed in claim 13, the additional spacers and the stress film consisting essentially of silicon nitrides.

18. The semiconductor device structure as claimed in claim 13, the additional spacers having a chemical composition differing from a chemical composition of the stress film.

19. The semiconductor device structure as claimed in claim 13, each of the additional spacers comprising a plurality of integral parts.

20. The semiconductor device structure as claimed in claim 19, wherein the plurality is two.