Cathal Phelan

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Latency reduction in touch sensitive systems
- Patent number 11,016,600
- Issue date May 25, 2021
- Beechrock Limited
- Owen Drumm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for super speed packet transfer
- Patent number 8,825,925
- Issue date Sep 2, 2014
- Cypress Semiconductor Corporation
- Gaurav Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speed power efficient USB method
- Patent number 6,839,778
- Issue date Jan 4, 2005
- Cypress Semiconductor Corp.
- Ronald H. Sartore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with fixed length non interruptible burst
- Patent number 6,651,134
- Issue date Nov 18, 2003
- Cypress Semiconductor Corp.
- Cathal G. Phelan
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile static memory cell
- Patent number 6,556,487
- Issue date Apr 29, 2003
- Cypress Semiconductor Corp.
- Nirmal Ratnakumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, architecture and circuitry for independently configuring a...
- Patent number 6,499,089
- Issue date Dec 24, 2002
- Cypress Semiconductor Corp.
- Cathal G. Phelan
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory having independent read port and write port an...
- Patent number 6,445,645
- Issue date Sep 3, 2002
- Cypress Semiconductor Corporation
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Grant
Direct bit line-bit line defect detection test mode for SRAM
- Patent number 6,388,927
- Issue date May 14, 2002
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory having a read/write address bus and process fo...
- Patent number 6,385,128
- Issue date May 7, 2002
- Cypress Semiconductor Corp.
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit, architecture and method for reducing power consumption in...
- Patent number 6,363,031
- Issue date Mar 26, 2002
- Cypress Semiconductor Corp.
- Cathal Phelan
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for implementing single-cycle read/write operati...
- Patent number 6,292,403
- Issue date Sep 18, 2001
- Cypress Semiconductor Corp.
- Ashish Pancholy
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan path circuitry including a programmable delay circuit
- Patent number 6,286,118
- Issue date Sep 4, 2001
- Cypress Semiconductor Corporation
- Jonathan F. Churchill
- G01 - MEASURING TESTING
Information Patent Grant
Random access memory having independent read port and write port an...
- Patent number 6,262,936
- Issue date Jul 17, 2001
- Cypress Semiconductor Corp.
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous random access memory having a read/write address bus an...
- Patent number 6,262,937
- Issue date Jul 17, 2001
- Cypress Semiconductor Corp.
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for hidden DRAM refresh
- Patent number 6,256,249
- Issue date Jul 3, 2001
- Cypress Semiconductor Corp.
- Cathal G. Phelan
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit, architecture and method for reducing power consumption in...
- Patent number 6,166,991
- Issue date Dec 26, 2000
- Cypress Semiconductor Corp.
- Cathal Phelan
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan path circuitry for programming a variable clock pulse width
- Patent number 6,115,836
- Issue date Sep 5, 2000
- Cypress Semiconductor Corporation
- Jonathan F. Churchill
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for implementing single-cycle read/write operati...
- Patent number 6,069,839
- Issue date May 30, 2000
- Cypress Semiconductor Corp.
- Ashish Pancholy
- G11 - INFORMATION STORAGE
Information Patent Grant
Test mode features for synchronous pipelined memories
- Patent number 6,006,347
- Issue date Dec 21, 1999
- Cypress Semiconductor Corporation
- Jonathan F. Churchill
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan path circuitry including an output register having a flow thro...
- Patent number 5,953,285
- Issue date Sep 14, 1999
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan path circuitry including a programmable delay circuit
- Patent number 5,936,977
- Issue date Aug 10, 1999
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- G01 - MEASURING TESTING
Information Patent Grant
Sense amplifier with limited output voltage swing
- Patent number 5,525,919
- Issue date Jun 11, 1996
- Cypress Semiconductor Corporation
- Cathal G. Phelan
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential latch sense amlifiers using feedback
- Patent number 5,504,443
- Issue date Apr 2, 1996
- Cypress Semiconductor Corp.
- Eric Gross
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory having a decoder with improved address hold time
- Patent number 5,493,241
- Issue date Feb 20, 1996
- Cypress Semiconductor, Inc.
- Gregory J. Landry
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexibilitiy for column redundancy in a divided array architecture
- Patent number 5,491,664
- Issue date Feb 13, 1996
- Cypress Semiconductor Corporation
- Cathal G. Phelan
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel TESTMODE
- Patent number 5,383,157
- Issue date Jan 17, 1995
- Cypress Semiconductor Corporation
- Cathal G. Phelan
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with limited output voltage swing and cross-coupled...
- Patent number 5,347,183
- Issue date Sep 13, 1994
- Cypress Semiconductor Corporation
- Cathal G. Phelan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LATENCY REDUCTION IN TOUCH SENSITIVE SYSTEMS
- Publication number 20200012408
- Publication date Jan 9, 2020
- Rapt IP Limited
- Owen Drumm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RANDOM ACCESS MEMORY HAVING A READ/WRITE ADDRESS BUS AND PROCESS FO...
- Publication number 20020054535
- Publication date May 9, 2002
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Application
Random access memory having independent read port and write port an...
- Publication number 20010043506
- Publication date Nov 22, 2001
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit, architecture and method for reducing power consumption in...
- Publication number 20010000995
- Publication date May 10, 2001
- CYPRESS SEMICONDUCTOR CORP.
- Cathal Phelan
- G11 - INFORMATION STORAGE

Cathal Phelan

Person

Patents Grantslast 30 patents

Latency reduction in touch sensitive systems

Systems and methods for super speed packet transfer

Speed power efficient USB method

Memory device with fixed length non interruptible burst

Non-volatile static memory cell

Method, architecture and circuitry for independently configuring a...

Random access memory having independent read port and write port an...

Direct bit line-bit line defect detection test mode for SRAM

Random access memory having a read/write address bus and process fo...

Circuit, architecture and method for reducing power consumption in...

Circuit and method for implementing single-cycle read/write operati...

Scan path circuitry including a programmable delay circuit

Random access memory having independent read port and write port an...

Synchronous random access memory having a read/write address bus an...

Method for hidden DRAM refresh

Circuit, architecture and method for reducing power consumption in...

Scan path circuitry for programming a variable clock pulse width

Circuit and method for implementing single-cycle read/write operati...

Test mode features for synchronous pipelined memories

Scan path circuitry including an output register having a flow thro...

Scan path circuitry including a programmable delay circuit

Sense amplifier with limited output voltage swing

Differential latch sense amlifiers using feedback

Memory having a decoder with improved address hold time

Flexibilitiy for column redundancy in a divided array architecture

Parallel TESTMODE

Sense amplifier with limited output voltage swing and cross-coupled...

Patents Applicationslast 30 patents

LATENCY REDUCTION IN TOUCH SENSITIVE SYSTEMS

RANDOM ACCESS MEMORY HAVING A READ/WRITE ADDRESS BUS AND PROCESS FO...

Random access memory having independent read port and write port an...

Circuit, architecture and method for reducing power consumption in...