Christophe J. Chevallier

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bias temperature instability correction in memory arrays
- Patent number 11,837,285
- Issue date Dec 5, 2023
- Applied Materials, Inc.
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-terminal reversibly switchable memory device
- Patent number 11,672,189
- Issue date Jun 6, 2023
- Hefei Reliance Memory Limited
- Darrell Rinerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retention drift correction in non-volatile memory arrays
- Patent number 11,605,426
- Issue date Mar 14, 2023
- Applied Materials, Inc.
- Christophe J. Chevallier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 11,502,249
- Issue date Nov 15, 2022
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM with address dependent power usage
- Patent number 11,443,795
- Issue date Sep 13, 2022
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Local bit lines and methods of selecting the same to access memory...
- Patent number 11,398,256
- Issue date Jul 26, 2022
- Unity Semiconductor Corporation
- Chang Hua Siau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-uniform state spacing in multi-state memory element for low-pow...
- Patent number 11,127,458
- Issue date Sep 21, 2021
- Applied Materials, Inc.
- Deepak Kamalanathan
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits and techniques to compensate memory access signals for var...
- Patent number 11,069,386
- Issue date Jul 20, 2021
- Unity Semiconductor Corporation
- Christophe Chevallier
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Two-terminal reversibly switchable memory device
- Patent number 11,063,214
- Issue date Jul 13, 2021
- Hefei Reliance Memory Limited
- Darrell Rinerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Access signal adjustment circuits and methods for memory cells in a...
- Patent number 11,011,226
- Issue date May 18, 2021
- Unity Semiconductor Corporation
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Preservation circuit and methods to maintain values representing da...
- Patent number 10,971,227
- Issue date Apr 6, 2021
- Unity Semiconductor Corporation
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage switching circuitry for a cross-point array
- Patent number 10,971,224
- Issue date Apr 6, 2021
- Unity Semiconductor Corporation
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with error correction in retention mode
- Patent number 10,885,972
- Issue date Jan 5, 2021
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 10,833,125
- Issue date Nov 10, 2020
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 10,797,106
- Issue date Oct 6, 2020
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-terminal reversibly switchable memory device
- Patent number 10,680,171
- Issue date Jun 9, 2020
- Hefei Reliance Memory Limited
- Darrell Rinerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High voltage switching circuitry for a cross-point array
- Patent number 10,672,467
- Issue date Jun 2, 2020
- Unity Semiconductor Corporation
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits and techniques to compensate memory access signals for var...
- Patent number 10,650,870
- Issue date May 12, 2020
- Unity Semiconductor Corporation
- Christophe Chevallier
- B82 - NANO-TECHNOLOGY
Information Patent Grant
SRAM with error correction in retention mode
- Patent number 10,629,257
- Issue date Apr 21, 2020
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local bit lines and methods of selecting the same to access memory...
- Patent number 10,622,028
- Issue date Apr 14, 2020
- Unity Semiconductor Corporation
- Chang Hua Siau
- G11 - INFORMATION STORAGE
Information Patent Grant
Access signal adjustment circuits and methods for memory cells in a...
- Patent number 10,614,882
- Issue date Apr 7, 2020
- Unity Semiconductor Corporation
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Preservation circuit and methods to maintain values representing da...
- Patent number 10,453,525
- Issue date Oct 22, 2019
- Unity Semiconductor Corporation
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Access signal adjustment circuits and methods for memory cells in a...
- Patent number 10,354,726
- Issue date Jul 16, 2019
- Unity Semiconductor Corporation
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage switching circuitry for a cross-point array
- Patent number 10,347,332
- Issue date Jul 9, 2019
- Unity Semiconductor Corporation
- Christophe Chevallier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SRAM with multiple power domains
- Patent number 10,347,328
- Issue date Jul 9, 2019
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 10,340,312
- Issue date Jul 2, 2019
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for controlling substrate and well biases for...
- Patent number 10,332,589
- Issue date Jun 25, 2019
- Ambiq Micro, Inc.
- Scott Hanson
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with error correction in retention mode
- Patent number 10,319,429
- Issue date Jun 11, 2019
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Write assist thyristor-based SRAM circuits and methods of operation
- Patent number 10,283,185
- Issue date May 7, 2019
- TC Lab, Inc.
- Harry Luan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-terminal reversibly switchable memory device
- Patent number 10,224,480
- Issue date Mar 5, 2019
- Hefei Reliance Memory Limited
- Darrell Rinerson
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
BIAS TEMPERATURE INSTABILITY CORRECTION IN MEMORY ARRAYS
- Publication number 20230058423
- Publication date Feb 23, 2023
- Applied Materials, Inc.
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
RETENTION DRIFT CORRECTION IN NON-VOLATILE MEMORY ARRAYS
- Publication number 20220343975
- Publication date Oct 27, 2022
- Applied Materials, Inc.
- Christophe J. Chevallier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
- Publication number 20210193917
- Publication date Jun 24, 2021
- Hefei Reliance Memory Limited
- Darrell RINERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20210013262
- Publication date Jan 14, 2021
- Hefei Reliance Memory Limited
- Christophe J. CHEVALLIER
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY
- Publication number 20200365205
- Publication date Nov 19, 2020
- UNITY SEMICONDUCTOR CORPORATION
- Christophe Chevallier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VAR...
- Publication number 20200335144
- Publication date Oct 22, 2020
- UNITY SEMICONDUCTOR CORPORATION
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A...
- Publication number 20200303005
- Publication date Sep 24, 2020
- UNITY SEMICONDUCTOR CORPORATION
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...
- Publication number 20200302973
- Publication date Sep 24, 2020
- UNITY SEMICONDUCTOR CORPORATION
- Chang Hua Siau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
- Publication number 20200259079
- Publication date Aug 13, 2020
- Hefei Reliance Memory Limited
- Darrell RINERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM with Error Correction in Retention Mode
- Publication number 20200227115
- Publication date Jul 16, 2020
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRESERVATION CIRCUIT AND METHODS TO MAINTAIN VALUES REPRESENTING DA...
- Publication number 20200118625
- Publication date Apr 16, 2020
- UNITY SEMICONDUCTOR CORPORATION
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A...
- Publication number 20200013460
- Publication date Jan 9, 2020
- UNITY SEMICONDUCTOR CORPORATION
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY
- Publication number 20190392895
- Publication date Dec 26, 2019
- UNITY SEMICONDUCTOR CORPORATION
- Christophe Chevallier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20190305047
- Publication date Oct 3, 2019
- Hefei Reliance Memory Limited
- Christophe J. CHEVALLIER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SRAM with Error Correction in Retention Mode
- Publication number 20190259450
- Publication date Aug 22, 2019
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VAR...
- Publication number 20190252011
- Publication date Aug 15, 2019
- UNITY SEMICONDUCTOR CORPORATION
- Christophe Chevallier
- B82 - NANO-TECHNOLOGY
Information Patent Application
TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
- Publication number 20190173006
- Publication date Jun 6, 2019
- Hefei Reliance Memory Limited
- Darrell RINERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A...
- Publication number 20190103161
- Publication date Apr 4, 2019
- UNITY SEMICONDUCTOR CORPORATION
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM with Error Correction in Retention Mode
- Publication number 20190074056
- Publication date Mar 7, 2019
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM With Address Dependent Power Usage
- Publication number 20190019550
- Publication date Jan 17, 2019
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY
- Publication number 20190013070
- Publication date Jan 10, 2019
- UNITY SEMICONDUCTOR CORPORATION
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...
- Publication number 20180342268
- Publication date Nov 29, 2018
- UNITY SEMICONDUCTOR CORPORATION
- Chang Hua Siau
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH MULTIPLE POWER DOMAINS
- Publication number 20180336945
- Publication date Nov 22, 2018
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
Low Power Buffer with Voltage Conversion
- Publication number 20180226972
- Publication date Aug 9, 2018
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VAR...
- Publication number 20180226110
- Publication date Aug 9, 2018
- UNITY SEMICONDUCTOR CORPORATION
- Christophe Chevallier
- B82 - NANO-TECHNOLOGY
Information Patent Application
SRAM WITH ACTIVE SUBSTRATE BIAS
- Publication number 20180211702
- Publication date Jul 26, 2018
- Ambiq Micro, Inc.
- Scott Hanson
- G11 - INFORMATION STORAGE
Information Patent Application
PRESERVATION CIRCUIT AND METHODS TO MAINTAIN VALUES REPRESENTING DA...
- Publication number 20180182454
- Publication date Jun 28, 2018
- UNITY SEMICONDUCTOR CORPORATION
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
- Publication number 20180130946
- Publication date May 10, 2018
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM With Multiple Power Domains
- Publication number 20180130520
- Publication date May 10, 2018
- Ambiq Micro, Inc.
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20180122857
- Publication date May 3, 2018
- UNITY SEMICONDUCTOR CORPORATION
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE

Christophe J. Chevallier

Person

Patents Grantslast 30 patents

Bias temperature instability correction in memory arrays

Two-terminal reversibly switchable memory device

Retention drift correction in non-volatile memory arrays

Memory element with a reactive metal layer

SRAM with address dependent power usage

Local bit lines and methods of selecting the same to access memory...

Non-uniform state spacing in multi-state memory element for low-pow...

Circuits and techniques to compensate memory access signals for var...

Two-terminal reversibly switchable memory device

Access signal adjustment circuits and methods for memory cells in a...

Preservation circuit and methods to maintain values representing da...

High voltage switching circuitry for a cross-point array

SRAM with error correction in retention mode

Memory element with a reactive metal layer

Memory element with a reactive metal layer

Two-terminal reversibly switchable memory device

High voltage switching circuitry for a cross-point array

Circuits and techniques to compensate memory access signals for var...

SRAM with error correction in retention mode

Local bit lines and methods of selecting the same to access memory...

Access signal adjustment circuits and methods for memory cells in a...

Preservation circuit and methods to maintain values representing da...

Access signal adjustment circuits and methods for memory cells in a...

High voltage switching circuitry for a cross-point array

SRAM with multiple power domains

Memory element with a reactive metal layer

Method and apparatus for controlling substrate and well biases for...

SRAM with error correction in retention mode

Write assist thyristor-based SRAM circuits and methods of operation

Two-terminal reversibly switchable memory device

Patents Applicationslast 30 patents

BIAS TEMPERATURE INSTABILITY CORRECTION IN MEMORY ARRAYS

RETENTION DRIFT CORRECTION IN NON-VOLATILE MEMORY ARRAYS

TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY

CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VAR...

ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A...

LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...

TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

SRAM with Error Correction in Retention Mode

PRESERVATION CIRCUIT AND METHODS TO MAINTAIN VALUES REPRESENTING DA...

ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A...

HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

SRAM with Error Correction in Retention Mode

CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VAR...

TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A...

SRAM with Error Correction in Retention Mode

SRAM With Address Dependent Power Usage

HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY

LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...

SRAM WITH MULTIPLE POWER DOMAINS

Low Power Buffer with Voltage Conversion

CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VAR...

SRAM WITH ACTIVE SUBSTRATE BIAS

PRESERVATION CIRCUIT AND METHODS TO MAINTAIN VALUES REPRESENTING DA...

TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

SRAM With Multiple Power Domains

MEMORY ELEMENT WITH A REACTIVE METAL LAYER