Consuelo N. Tangpuz

Person

Lapulapu, PH

People

Patents Grantslast 30 patents

Information Patent Grant
Dual metal stud bumping for flip chip applications
- Patent number 7,932,171
- Issue date Apr 26, 2011
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Integrated transistor module and method of fabricating same
- Patent number 7,842,555
- Issue date Nov 30, 2010
- Fairchild Semiconductor Corporation
- Rajeev D. Joshi
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Substrate based unmolded package
- Patent number 7,682,877
- Issue date Mar 23, 2010
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip in leaded molded package and method of manufacture thereof
- Patent number 7,582,956
- Issue date Sep 1, 2009
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual metal stud bumping for flip chip applications
- Patent number 7,501,337
- Issue date Mar 10, 2009
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Integrated transistor module and method of fabricating same
- Patent number 7,501,702
- Issue date Mar 10, 2009
- Fairchild Semiconductor Corporation
- Rajeev D. Joshi
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Substrate based unmolded package
- Patent number 7,439,613
- Issue date Oct 21, 2008
- Fairchild Semicondcutor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual metal stud bumping for flip chip applications
- Patent number 7,271,497
- Issue date Sep 18, 2007
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip in leaded molded package and method of manufacture thereof
- Patent number 7,215,011
- Issue date May 8, 2007
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip in leaded molded package and method of manufacture thereof
- Patent number 7,154,168
- Issue date Dec 26, 2006
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including molded wireless exposed drain packaging
- Patent number 6,989,588
- Issue date Jan 24, 2006
- Fairchild Semiconductor Corporation
- Maria C. Y. Quinones
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip in leaded molded package and method of manufacture thereof
- Patent number 6,949,410
- Issue date Sep 27, 2005
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for maintaining solder thickness in flipchip attach packagin...
- Patent number 6,943,434
- Issue date Sep 13, 2005
- Fairchild Semiconductor Corporation
- Consuelo N. Tangpuz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level coated copper stud bumps
- Patent number 6,731,003
- Issue date May 4, 2004
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip in leaded molded package and method of manufacture thereof
- Patent number 6,720,642
- Issue date Apr 13, 2004
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low Resistance package for semiconductor devices
- Patent number 6,423,623
- Issue date Jul 23, 2002
- Fairchild Semiconductor Corporation
- Izak Bencuya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Column ball grid array package
- Patent number 6,391,687
- Issue date May 21, 2002
- Fairchild Semiconductor Corporation
- Elsie A. Cabahug
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LEADLESS SEMICONDUCTOR DEVICE TERMINAL
- Publication number 20110095417
- Publication date Apr 28, 2011
- Fairchild Semiconductor Corporation
- Jocel P. Gomez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL METAL STUD BUMPING FOR FLIP CHIP APPLICATIONS
- Publication number 20090186452
- Publication date Jul 23, 2009
- Rajeev Joshi
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
INTEGRATED TRANSISTOR MODULE AND METHOD OF FABRICATING SAME
- Publication number 20090117690
- Publication date May 7, 2009
- Rajeev D. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE BASED UNMOLDED PACKAGE
- Publication number 20080213946
- Publication date Sep 4, 2008
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP IN LEADED MOLDED PACKAGE AND METHOD OF MANUFACTURE THEREOF
- Publication number 20080036056
- Publication date Feb 14, 2008
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual metal stud bumping for flip chip applications
- Publication number 20060189116
- Publication date Aug 24, 2006
- Rajeev Joshi
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
Integrated transistor module and method of fabricating same
- Publication number 20050285238
- Publication date Dec 29, 2005
- Rajeev D. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flip chip in leaded molded package and method of manufacture thereof
- Publication number 20050280126
- Publication date Dec 22, 2005
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for maintaining solder thickness in flipchip attach packagin...
- Publication number 20050224940
- Publication date Oct 13, 2005
- Consuelo N. Tangpuz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Filp chip in leaded molded package and method of manufacture thereof
- Publication number 20050167848
- Publication date Aug 4, 2005
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Substrate based unmolded package
- Publication number 20040207052
- Publication date Oct 21, 2004
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual metal stud bumping for flip chip applications
- Publication number 20040178481
- Publication date Sep 16, 2004
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for maintaining solder thickness in flipchip attach packagin...
- Publication number 20040130009
- Publication date Jul 8, 2004
- Consuelo N. Tangpuz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flip chip in leaded molded package and method of manufacture thereof
- Publication number 20040056364
- Publication date Mar 25, 2004
- Fairchild Semiconductor Corporation
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer-level coated copper stud bumps
- Publication number 20030173684
- Publication date Sep 18, 2003
- Rajeev Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device including molded wireless exposed drain packaging
- Publication number 20030052408
- Publication date Mar 20, 2003
- Fairchild Semiconductor Corporation
- Maria C.Y. Quinones
- H01 - BASIC ELECTRIC ELEMENTS

Consuelo N. Tangpuz

Person

Patents Grantslast 30 patents

Dual metal stud bumping for flip chip applications

Integrated transistor module and method of fabricating same

Substrate based unmolded package

Flip chip in leaded molded package and method of manufacture thereof

Dual metal stud bumping for flip chip applications

Integrated transistor module and method of fabricating same

Substrate based unmolded package

Dual metal stud bumping for flip chip applications

Flip chip in leaded molded package and method of manufacture thereof

Flip chip in leaded molded package and method of manufacture thereof

Semiconductor device including molded wireless exposed drain packaging

Flip chip in leaded molded package and method of manufacture thereof

Method for maintaining solder thickness in flipchip attach packagin...

Wafer-level coated copper stud bumps

Flip chip in leaded molded package and method of manufacture thereof

Low Resistance package for semiconductor devices

Column ball grid array package

Patents Applicationslast 30 patents

LEADLESS SEMICONDUCTOR DEVICE TERMINAL

DUAL METAL STUD BUMPING FOR FLIP CHIP APPLICATIONS

INTEGRATED TRANSISTOR MODULE AND METHOD OF FABRICATING SAME

SUBSTRATE BASED UNMOLDED PACKAGE

FLIP CHIP IN LEADED MOLDED PACKAGE AND METHOD OF MANUFACTURE THEREOF

Dual metal stud bumping for flip chip applications

Integrated transistor module and method of fabricating same

Flip chip in leaded molded package and method of manufacture thereof

Method for maintaining solder thickness in flipchip attach packagin...

Filp chip in leaded molded package and method of manufacture thereof

Substrate based unmolded package

Dual metal stud bumping for flip chip applications

Method for maintaining solder thickness in flipchip attach packagin...

Flip chip in leaded molded package and method of manufacture thereof

Wafer-level coated copper stud bumps

Semiconductor device including molded wireless exposed drain packaging