Patent Application
20110095417
In semiconductor manufacturing, an integrated circuit die can be coupled to a printed circuit board or an integrated circuit package using one or more conductive bumps.
This document discusses, among other things, a semiconductor die having a first conductive bump coupled to a first electrical terminal at a first die surface of a semiconductor die and a dielectric substantially covering the first die surface and substantially surrounding the first conductive bump. In an example, the dielectric can be configured to support the first conductive bump or the semiconductor die, or to secure the first conductive bump to the first die surface. In certain examples, the dielectric can include a polymer configured to be activated to conductive plating deposition using laser ablation, and a second terminal can be formed on the dielectric, coupled to the first conductive bump, using laser ablation and conductive plating deposition.
In Example 1, a semiconductor device includes a semiconductor die having a first die surface and a first electrical terminal at the first die surface, a first copper (Cu) bump having a first bump surface coupled to the first electrical terminal and a second opposite bump surface, a dielectric configured to be activated to Cu plating deposition using laser ablation, the dielectric substantially covering the first die surface and substantially surrounding the first Cu bump between the first and second bump surfaces, the dielectric having a first dielectric surface proximate the first die surface and a second dielectric surface opposite the first dielectric surface, the second dielectric surface including a recessed terminal area, a second electrical terminal coupled to the second bump surface in the recessed terminal area, the second electrical terminal configured to provide an electrical connection to the first electrical terminal at the first die surface, wherein the recessed terminal area includes a recess created using laser ablation of the second dielectric surface, and wherein the recessed terminal area includes the second bump surface, and wherein the second electrical terminal includes a laser activated Cu plating deposition in the recessed terminal area.
In Example 2, a semiconductor device includes a semiconductor die having a first die surface and a first electrical terminal at the first die surface, a first conductive bump having a first bump surface coupled to the first electrical terminal and a second opposite bump surface, a dielectric substantially covering the first die surface and substantially surrounding the first conductive bump between the first and second bump surfaces, the dielectric having a first dielectric surface proximate the first die surface and a second dielectric surface opposite the first dielectric surface, the second dielectric surface including a recessed terminal area, and a second electrical terminal coupled to the second bump surface in the recessed terminal area, the second electrical terminal configured to provide an electrical connection to the first electrical terminal at the first die surface.
In Example 3, the dielectric of any one or more of Examples 1-2 optionally includes a polymer configured to be activated to conductive plating deposition using laser ablation, and wherein the recessed terminal area includes a recess created using laser ablation of the second dielectric surface, and the second electrical terminal of any one or more of Examples 1-2 optionally includes a laser activated conductive plating deposition in the recessed terminal area.
In Example 4, the recessed terminal area of any one or more of Examples 1-3 optionally includes the second bump surface.
In Example 5, the second bump surface of any one or more of Examples 1-4 is optionally exposed in the recessed terminal area using laser ablation of the second dielectric surface.
In Example 6, the first conductive bump of any one or more of Examples 1-5 optionally includes a first copper (Cu) bump, wherein the polymer includes a polymer configured to be activated to Cu plating deposition using laser ablation, and wherein the second electrical terminal includes a laser activated Cu plating deposition.
In Example 7, the polymer of any one or more of Examples 1-6 optionally includes at least one of thermoplastic, crosslink, an epoxy mold compound (EMC), or a Polybutylene Terephthalate (PBT).
In Example 8, any one or more of Examples 1-7 optionally includes a second conductive bump coupled to the second electrical terminal, wherein the second conductive bump includes a solder bump configured to provide a contact for external board mounting soldering.
In Example 9, the second electrical terminal of any one or more of Examples 1-8 optionally includes the second conductive bump.
In Example 10, the first conductive bump of any one or more of Examples 1-9 optionally includes a first Cu bump having a first distance between the first and second bump surfaces, and wherein the dielectric includes a thickness corresponding to the first distance of the first conductive bump.
In Example 11, the first conductive bump of any one or more of Examples 1-10 optionally includes a substantially round portion having the first bump surface opposite the second bump surface.
In Example 12, the recessed terminal area of any one or more of Examples 1-11 optionally includes a shape formed at the second dielectric surface using laser ablation, and wherein the second electrical terminal is configured to be deposited in the recessed terminal area, taking the shape of the recessed terminal area.
In Example 13, the shape of the second electrical terminal of any one or more of Examples 1-12 optionally includes at least one of a circular shape, a square shape, or a rectangular shape.
In Example 14, the dielectric of any one or more of Examples 1-13 optionally includes a polymer configured to provide rigid support between the first conductive bump and the first electrical terminal at the first die surface.
In Example 15, the semiconductor die of any one or more of Examples 1-14 optionally includes a stacked die.
In Example 16, the semiconductor die of any one or more of Examples 1-15 optionally includes a plurality of first electrical terminals at the first die surface and a plurality of corresponding first conductive bumps coupled to each of the plurality of electrical terminals, and the recessed terminal area of any one or more of Examples 1-15 optionally covers at least two of the plurality of first conductive bumps, wherein the second electrical terminal is coupled to the at least two of the plurality of first conductive bumps in the recessed terminal area.
In Example 17, the dielectric of any one or more of Examples 1-16 optionally includes a polymer configured to be activated to conductive plating deposition using laser ablation, and wherein the recessed terminal area includes a recess created using laser ablation of the second dielectric surface, and the second electrical terminal of any one or more of Examples 1-16 optionally includes a laser activated conductive plating deposition in the recessed terminal area.
In Example 18, a semiconductor device includes a semiconductor die having a first die surface and a plurality of first electrical terminals at the first die surface, a plurality of first conductive bumps corresponding to each of the plurality of electrical terminals at the first die surface, each of the first conductive bumps having a first bump surface coupled to one of the plurality of electrical terminals and having a second opposite bump surface, a dielectric substantially covering the first die surface and substantially surrounding the plurality of first conductive bumps between the first and second bump surfaces of each first conductive bump, the dielectric having a first dielectric surface proximate the first die surface and a second dielectric surface opposite the first dielectric surface, the second dielectric surface including a recessed terminal area, a second electrical terminal coupled to at least one of the second bump surfaces in one of the recessed terminal configured to provide an electrical connection to at least one of the plurality of first electrical terminals at the first die surface, wherein the dielectric includes a polymer configured to be activated to plating deposition using laser ablation, and wherein the recessed terminal area includes a recess created using laser ablation of the second surface, and wherein the second electrical terminal includes a laser activated conductive plating deposition in the recessed terminal area.
In Example 19, the plurality of first conductive bumps of any one or more of Examples 1-18 optionally includes a plurality of first Cu bumps, wherein the polymer includes a polymer configured to be activated to copper plating deposition using laser ablation, and wherein the second electrical terminal includes a laser activated copper plating deposition.
In Example 20, the recessed terminal area of any one or more of Examples 1-19 optionally includes at least one second bump surface of one or more of the plurality of first conductive bumps.
In Example 21, a method can include forming a first conductive bump on a first electrical terminal on a die surface of a semiconductor die, substantially covering the first die surface and substantially surrounding the first conductive bump using a dielectric, providing a recessed terminal area in the dielectric, and forming a second electrical terminal coupled to the first conductive bump in the recessed terminal area, the electrical terminal configured to provide an electrical connection to the first electrical terminal at the first die surface.
In Example 22, the substantially covering the first die surface and substantially surrounding the first conductive bump of any one or more of Examples 1-21 optionally includes using a polymer configured to be activated to conductive plating deposition using laser ablation, and the providing the recessed terminal area and the forming the electrical terminal of any one or more of Examples 1-21 optionally includes using laser ablation of the polymer.
In Example 23, the providing the recessed terminal area of any one or more of Examples 1-22 optionally includes exposing at least a portion of the first conductive bump.
In Example 24, the forming the first conductive bump of any one or more of Examples 1-23 optionally includes forming a first copper (Cu) bump, the substantially covering the first die surface and substantially surrounding the first conductive bump of any one or more of Examples 1-23 optionally includes using a polymer configured to be activated to Cu plating deposition using laser ablation, and the forming the electrical terminal of any one or more of Examples 1-23 optionally includes using a laser activated Cu plating deposition.
In Example 25, the substantially covering the first die surface and substantially surrounding the first conductive bump of any one or more of Examples 1-24 optionally includes using at least one of thermoplastic, crosslink, an epoxy mold (EMC) compound, or a Polybutylene Terephthalate (PBT).
In Example 26, any one or more of Examples 1-25 optionally includes forming a second conductive bump on the second electrical terminal.
In Example 27, the substantially covering the first die surface and substantially surrounding the first conductive bump using the dielectric of any one or more of Examples 1-26 optionally includes providing rigid support between the first conductive bump and the first electrical terminal.
In Example 28, the forming the first conductive bump of any one or more of Examples 1-27 optionally includes forming a plurality of first conductive bumps on a plurality of first electrical terminals on the first die surface, the providing the recessed terminal area of any one or more of Examples 1-27 optionally includes providing a recessed terminal area over at least two of the plurality of first conductive bumps, and the forming the second electrical terminal of any one or more of Examples 1-27 optionally includes forming a second electrical terminal coupled to the at least two of the plurality of first conductive bumps, providing an electrical connection to at least two of the plurality of first electrical terminals on the first die surface.
This overview is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.
In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
In certain examples, solder bumps can be attached to a semiconductor die prior to coupling the semiconductor die to a printed circuit board or an integrated circuit package. In various examples, solder bumps can crack, can become detached, or can be otherwise compromised, for example, due to thermal changes or mechanical stresses of or on the solder bumps. Further, in semiconductor manufacturing, changing the size, shape, or configuration of an integrated circuit terminal can require one or more different masks.
The present inventors have recognized, among other things, that a dielectric can be configured to support a first conductive bump coupled to a first terminal on a semiconductor die. Further, the present inventors have recognized that the dielectric can include a polymer configured to be activated to conductive plating deposition using laser ablation, and that a second terminal can be formed on the dielectric, coupled to the first conductive bump, using laser ablation and conductive plating deposition (e.g., copper (Cu) plating deposition).
In an example, a molded chip scale semiconductor device can include one or more terminals coupled to one or more conductive bumps or conductive bumped structures (e.g., Cu bump, etc.). In an example, a conductive bump can be directly bonded on a device terminal or a device die bonding pad.
In certain examples, one or more semiconductor device terminals (e.g., one or more wafer level semiconductor device terminals) can be formed using a molded surface. In an example, the molded surface can include a polymer material (e.g., thermoplastic, crosslink, or one or more other polymer materials) activated to conductive plating deposition (e.g., Cu plating deposition) when the surface of the polymer material is ablated using a laser. In certain examples, the polymer material can replace the conventional printed circuit board (PCB) and can be used to form a semiconductor device terminal. Further, the polymer material can be applied on leadless or bump molded chip scale packages.
In an example, the semiconductor device disclosed herein can include a chip scale package having a smaller footprint or a thinner or lighter weight package than a conventional leadframe based molded device and can be applied to portable (e.g., ultraportable) products requiring condensed circuitry or small size. In certain examples, the semiconductor device terminal disclosed herein can be applied to a leadless or a bump molded chip scale package, stacked dies, or a die coupled to a metal structure (e.g., a frame, a heat sink, etc.).
In an example, the semiconductor die 105 can include a wafer-level chip scale semiconductor device having a first terminal (e.g., a device die bonding pad) on a first die surface. In an example, the first conductive bump 110 can include a first bump surface directly bonded to or otherwise in contact with the first terminal. In an example, the first conductive bump 110 can include a Cu bump or one or more other conductive bumps coupled to the semiconductor die 105, and the dielectric 115 can be configured to support the first conductive bump 110, or one or more other conductive bumps, between the first bump surface and a second bump surface on the semiconductor die 105. In an example, the second bump surface can include a top of the first conductive bump 110. In other examples, the second bump surface can include at least a portion of the surface of the first conductive bump 110 not in contact with the semiconductor die 105.
In an example, the dielectric 115 can include a polymer or other dielectric material configured to be activated to conductive plating deposition using laser ablation. In an example, the dielectric 115 can include thermoplastic, crosslink, an epoxy mold compound (EMC), polybutylene terephthalate (PBT), or one or more other dielectrics. In an example, the dielectric 115 can at least partially include a conductive component, such as one or more metallic compounds mixed into the dielectric material (e.g., an organometallic complex, etc.). In certain examples, the dielectric 115 can be substantially reduced to the metallic compound, or otherwise activated to conductive plating deposition, by irradiation with a laser (e.g., a CO2 laser).
In other examples, the dielectric 115 can include one or more other materials (e.g., a polymer matrix material including non-conductive polyacrylonitrile fibers) that, when subjected to laser irradiation, can carbonize, pyrolize, or otherwise decompose to form a conductive network that can be converted to a desired metallization thickness by chemical or electroplating reinforcement.
In certain examples, the dielectric 115 can be modified using a laser without a conductive phase forming locally, such as by creating catalytic centres on a dielectric material, or by using fine ceramic particles or catalytic micro-capsule or other fillers that can serve as sees for a following metallization process. Further, in various examples, the dielectric 115 can include an at least partially translucent mold compound, allowing visibility of the semiconductor die 105, the first conductive bump 110, or one or more other features of the device, reducing the need for added fiducial markers for laser ablation reference.
In various examples, the dielectric 315 can be configured to support the semiconductor die 305 or the first conductive bump 310, or to secure the first conductive bump 310 to the semiconductor die 305, in certain examples, providing a rigid device, less susceptible to mechanical or thermal stresses.
In an example, a recessed terminal area can be formed at a surface of the dielectric 315 (e.g., using laser ablation). In certain examples, the recessed terminal area can expose at least a portion of the first conductive bump 310, and a second electrical terminal 320 can be formed in the recessed terminal area coupled to a first conductive bump 310.
In certain examples, the dielectric 615 can partially surround the first conductive bump 610, or the dielectric 615 can completely surround the first conductive bump 610.
In certain examples, the dielectric 815 can include a fully dielectric material, or a dielectric material having a metallic or other component. In an example, the dielectric 815 can be activated to conductive plating deposition using laser ablation.
In an example, laser ablation of the dielectric 915 can free seeds on the surface of the material, enabling selective wet-chemical reduction metal precipitation. In other examples, one or more other methods utilizing laser ablation can be used to form the second electrical terminal 920.
In certain examples, one or more of process steps 500-1200 can be excluded, or one or more other process steps or variations can be introduced to those described above.
The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” All publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.
In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
The above description is intended to be illustrative, and not restrictive. In other examples, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. §1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
