David B. Papworth

Person

Framingham, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses and methods for a processor architecture
- Patent number 12,130,740
- Issue date Oct 29, 2024
- Intel Corporation
- Jason W. Brandt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for a processor architecture
- Patent number 11,294,809
- Issue date Apr 5, 2022
- Intel Corporation
- Jason W. Brandt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
QoS based binary translation and application streaming
- Patent number 10,469,557
- Issue date Nov 5, 2019
- Intel Corporation
- Bharath Muthiah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Zeroing a cache line
- Patent number 10,282,296
- Issue date May 7, 2019
- Intel Corporation
- Jason W. Brandt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
QoS based binary translation and application streaming
- Patent number 9,525,586
- Issue date Dec 20, 2016
- Intel Corporation
- Bharath Muthiah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for pipeline streamlining where resources are...
- Patent number 6,393,550
- Issue date May 21, 2002
- Intel Corporation
- Michael A. Fetterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Linear address extension and mapping to physical memory using 4 and...
- Patent number 6,349,380
- Issue date Feb 19, 2002
- Intel Corporation
- Shahrokh Shahidzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for maximum throughput scheduling of dependent...
- Patent number 6,101,597
- Issue date Aug 8, 2000
- Intel Corporation
- Robert P. Colwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor that redirects an instruction fetch pipeline immediately...
- Patent number 6,079,014
- Issue date Jun 20, 2000
- Intel Corporation
- David B. Papworth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Exception handling in a processor that performs speculative out-of-...
- Patent number 5,987,600
- Issue date Nov 16, 1999
- Intel Corporation
- David B. Papworth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for efficiently overlapping multiple operand types in a m...
- Patent number 5,974,523
- Issue date Oct 26, 1999
- Intel Corporation
- Andrew F. Glew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a set-associative branch targ...
- Patent number 5,944,817
- Issue date Aug 31, 1999
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a branch instruction pointer table
- Patent number 5,918,046
- Issue date Jun 29, 1999
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing address-size backward compatibil...
- Patent number 5,913,050
- Issue date Jun 15, 1999
- Intel Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a branch target buffer in CIS...
- Patent number 5,903,751
- Issue date May 11, 1999
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for scheduling instructions by predicting future...
- Patent number 5,842,036
- Issue date Nov 24, 1998
- Intel Corporation
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register alias table update to indicate architecturally visible state
- Patent number 5,826,094
- Issue date Oct 20, 1998
- Intel Corporation
- Robert P. Colwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing multiple load operations to the...
- Patent number 5,826,109
- Issue date Oct 20, 1998
- Intel Corporation
- Jeffery M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual prediction branch system having two step of branch recovery pr...
- Patent number 5,812,839
- Issue date Sep 22, 1998
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for scheduling instructions by predicting future...
- Patent number 5,809,325
- Issue date Sep 15, 1998
- Intel Corporation
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for changing flow of control in a processor
- Patent number 5,809,271
- Issue date Sep 15, 1998
- Intel Corporation
- Robert P. Colwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for determining operating characteristics of...
- Patent number 5,778,407
- Issue date Jul 7, 1998
- Intel Corporation
- Andrew F. Glew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamic allocation of multiple buffers in...
- Patent number 5,778,245
- Issue date Jul 7, 1998
- Intel Corporation
- David B. Papworth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for predicting and handling resolving return f...
- Patent number 5,768,576
- Issue date Jun 16, 1998
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with self-consistent ordering mechanism
- Patent number 5,751,986
- Issue date May 12, 1998
- Intel Corporation
- Michael A. Fetterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Out-of-order processor with a memory subsystem which handles specul...
- Patent number 5,751,983
- Issue date May 12, 1998
- Jeffrey M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for predicting, clearing and redirecting unpre...
- Patent number 5,729,728
- Issue date Mar 17, 1998
- Intel Corporation
- Robert P. Colwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for pipeline processing of instructions by controlling acces...
- Patent number 5,721,855
- Issue date Feb 24, 1998
- Intel Corporation
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dispatching and executing a load operation...
- Patent number 5,717,882
- Issue date Feb 10, 1998
- Intel Corporation
- Jeffrey M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a set-associative branch targ...
- Patent number 5,706,492
- Issue date Jan 6, 1998
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE
- Publication number 20220237123
- Publication date Jul 28, 2022
- Intel Corporation
- Jason W. Brandt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE
- Publication number 20190012266
- Publication date Jan 10, 2019
- Intel Corporation
- Jason W. Brandt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE
- Publication number 20180165199
- Publication date Jun 14, 2018
- Intel Corporation
- Jason W. Brandt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QOS BASED BINARY TRANSLATION AND APPLICATION STREAMING
- Publication number 20170237797
- Publication date Aug 17, 2017
- Intel Corporation
- Bharath Muthiah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
QOS BASED BINARY TRANSLATION AND APPLICATION STREAMING
- Publication number 20140281008
- Publication date Sep 18, 2014
- Bharath Muthiah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

David B. Papworth

Person

Patents Grantslast 30 patents

Apparatuses and methods for a processor architecture

Apparatuses and methods for a processor architecture

QoS based binary translation and application streaming

Zeroing a cache line

QoS based binary translation and application streaming

Method and apparatus for pipeline streamlining where resources are...

Linear address extension and mapping to physical memory using 4 and...

Method and apparatus for maximum throughput scheduling of dependent...

Processor that redirects an instruction fetch pipeline immediately...

Exception handling in a processor that performs speculative out-of-...

Mechanism for efficiently overlapping multiple operand types in a m...

Method and apparatus for implementing a set-associative branch targ...

Method and apparatus for a branch instruction pointer table

Method and apparatus for providing address-size backward compatibil...

Method and apparatus for implementing a branch target buffer in CIS...

Circuit and method for scheduling instructions by predicting future...

Register alias table update to indicate architecturally visible state

Method and apparatus for performing multiple load operations to the...

Dual prediction branch system having two step of branch recovery pr...

Circuit and method for scheduling instructions by predicting future...

Method and apparatus for changing flow of control in a processor

Methods and apparatus for determining operating characteristics of...

Method and apparatus for dynamic allocation of multiple buffers in...

Method and apparatus for predicting and handling resolving return f...

Computer system with self-consistent ordering mechanism

Out-of-order processor with a memory subsystem which handles specul...

Method and apparatus for predicting, clearing and redirecting unpre...

Method for pipeline processing of instructions by controlling acces...

Method and apparatus for dispatching and executing a load operation...

Method and apparatus for implementing a set-associative branch targ...

Patents Applicationslast 30 patents

APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE

APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE

APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE

QOS BASED BINARY TRANSLATION AND APPLICATION STREAMING

QOS BASED BINARY TRANSLATION AND APPLICATION STREAMING