David Jefferson

Person

Morgan Hill, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
FPGA configuration bitstream protection using multiple keys
- Patent number 9,208,357
- Issue date Dec 8, 2015
- Altera Corporation
- Martin Langhammer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
FPGA configuration bitstream encryption using modified key
- Patent number 9,054,859
- Issue date Jun 9, 2015
- Altera Corporation
- Keone Streicher
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
FPGA configuration bitstream protection using multiple keys
- Patent number 8,826,038
- Issue date Sep 2, 2014
- Altera Corporation
- Martin Langhammer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
FPGA configuration bitstream encryption using modified key
- Patent number 8,750,503
- Issue date Jun 10, 2014
- Altera Corporation
- Keone Streicher
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
One-time programmable memories for key storage
- Patent number 8,433,930
- Issue date Apr 30, 2013
- Altera Corporation
- Juju Joyce
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
FPGA configuration bitstream encryption using modified key
- Patent number 8,363,833
- Issue date Jan 29, 2013
- Altera Corporation
- Keone Streicher
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible RAM clock enable
- Patent number 8,271,821
- Issue date Sep 18, 2012
- Altera Corporation
- Jinyong Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
FPGA configuration bitstream protection using multiple keys
- Patent number 8,209,545
- Issue date Jun 26, 2012
- Altera Corporation
- Martin Langhammer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
FPGA configuration bitstream encryption using modified key
- Patent number 7,984,292
- Issue date Jul 19, 2011
- Altera Corporation
- Keone Streicher
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory elements with leakage compensation
- Patent number 7,864,603
- Issue date Jan 4, 2011
- Altera Corporation
- John Henry Bui
- G11 - INFORMATION STORAGE
Information Patent Grant
One-time programmable memories for key storage
- Patent number 7,818,584
- Issue date Oct 19, 2010
- Altera Corporation
- Juju Joyce
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Encryption key obfuscation and storage
- Patent number 7,734,043
- Issue date Jun 8, 2010
- Altera Corporation
- David Jefferson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA configuration bitstream protection using multiple keys
- Patent number 7,725,738
- Issue date May 25, 2010
- Altera Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA configuration bitstream encryption using modified key
- Patent number 7,606,362
- Issue date Oct 20, 2009
- Altera Corporation
- Keone Streicher
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Device programmable to operate as a multiplexer, demultiplexer, or...
- Patent number 7,606,081
- Issue date Oct 20, 2009
- Altera Corporation
- David Jefferson
- G11 - INFORMATION STORAGE
Information Patent Grant
Device programmable to operate as a multiplexer, demultiplexer, or...
- Patent number 7,463,544
- Issue date Dec 9, 2008
- Altera Corporation
- David Jefferson
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible RAM clock enable
- Patent number 7,397,726
- Issue date Jul 8, 2008
- Altera Corporation
- Jinyong Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for sequentially transferring data from a memory device...
- Patent number 7,343,470
- Issue date Mar 11, 2008
- Altera Corporation
- Juju Joyce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable memory access parameters
- Patent number 7,236,411
- Issue date Jun 26, 2007
- Altera Corporation
- Rahul Saini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable clock network for distributing clock signals to and be...
- Patent number 7,228,451
- Issue date Jun 5, 2007
- Altera Corporation
- Triet Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple size memories in a programmable logic device
- Patent number 7,161,381
- Issue date Jan 9, 2007
- Altera Corporation
- Srinivas Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory array operating as a shift register
- Patent number 7,051,153
- Issue date May 23, 2006
- Altera Corporation
- Yi-Wen Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable clock network for distributing clock signals to and be...
- Patent number 6,996,736
- Issue date Feb 7, 2006
- Altera Corporation
- Triet Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with redundant circuitry
- Patent number 6,965,249
- Issue date Nov 15, 2005
- Altera Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device architectures with super-regions having l...
- Patent number 6,879,183
- Issue date Apr 12, 2005
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flexible I/O routing resources
- Patent number 6,826,741
- Issue date Nov 30, 2004
- Altera Corporation
- Brian D. Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic array integrated circuit devices
- Patent number 6,815,981
- Issue date Nov 9, 2004
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with hierarchical interconnection resources
- Patent number 6,798,242
- Issue date Sep 28, 2004
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Line segmentation in programmable logic devices having redundancy c...
- Patent number 6,759,871
- Issue date Jul 6, 2004
- Altera Corporation
- Triet Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple size memories in a programmable logic device
- Patent number 6,720,796
- Issue date Apr 13, 2004
- Altera Corporation
- Srinivas Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Flexible RAM Clock Enable
- Publication number 20080253220
- Publication date Oct 16, 2008
- Altera Corporation
- Jinyong Yuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Line segmentation in programmable logic devices having redundancy c...
- Publication number 20030201793
- Publication date Oct 30, 2003
- Altera Corporation
- Triet Nguyen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20030201794
- Publication date Oct 30, 2003
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic array integrated circuit devices
- Publication number 20030128051
- Publication date Jul 10, 2003
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device architectures with super-regions having l...
- Publication number 20030080778
- Publication date May 1, 2003
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20030076130
- Publication date Apr 24, 2003
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with redundant circuitry
- Publication number 20030072185
- Publication date Apr 17, 2003
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic array integrated circuit devices
- Publication number 20030016053
- Publication date Jan 23, 2003
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device architectures with super-regions having l...
- Publication number 20020084801
- Publication date Jul 4, 2002
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with hierarchical interconnection resources
- Publication number 20020041191
- Publication date Apr 11, 2002
- Altera Corporation
- Srinivas T. Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Line segmentation in programmable logic devices having redundancy c...
- Publication number 20020003742
- Publication date Jan 10, 2002
- Triet Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
Redundancy circuitry for programmable logic devices with interleave...
- Publication number 20010006347
- Publication date Jul 5, 2001
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device architectures
- Publication number 20010006348
- Publication date Jul 5, 2001
- Altera Corporation
- David E. Jefferson
- H03 - BASIC ELECTRONIC CIRCUITRY

David Jefferson

Person

Patents Grantslast 30 patents

FPGA configuration bitstream protection using multiple keys

FPGA configuration bitstream encryption using modified key

FPGA configuration bitstream protection using multiple keys

FPGA configuration bitstream encryption using modified key

One-time programmable memories for key storage

FPGA configuration bitstream encryption using modified key

Flexible RAM clock enable

FPGA configuration bitstream protection using multiple keys

FPGA configuration bitstream encryption using modified key

Memory elements with leakage compensation

One-time programmable memories for key storage

Encryption key obfuscation and storage

FPGA configuration bitstream protection using multiple keys

FPGA configuration bitstream encryption using modified key

Device programmable to operate as a multiplexer, demultiplexer, or...

Device programmable to operate as a multiplexer, demultiplexer, or...

Flexible RAM clock enable

Techniques for sequentially transferring data from a memory device...

Programmable memory access parameters

Programmable clock network for distributing clock signals to and be...

Multiple size memories in a programmable logic device

Memory array operating as a shift register

Programmable clock network for distributing clock signals to and be...

Programmable logic device with redundant circuitry

Programmable logic device architectures with super-regions having l...

Flexible I/O routing resources

Programmable logic array integrated circuit devices

Programmable logic device with hierarchical interconnection resources

Line segmentation in programmable logic devices having redundancy c...

Multiple size memories in a programmable logic device

Patents Applicationslast 30 patents

Flexible RAM Clock Enable

Line segmentation in programmable logic devices having redundancy c...

Programmable logic device with hierarchical interconnection resources

Programmable logic array integrated circuit devices

Programmable logic device architectures with super-regions having l...

Programmable logic device with hierarchical interconnection resources

Programmable logic device with redundant circuitry

Programmable logic array integrated circuit devices

Programmable logic device architectures with super-regions having l...

Programmable logic device with hierarchical interconnection resources

Line segmentation in programmable logic devices having redundancy c...

Redundancy circuitry for programmable logic devices with interleave...

Programmable logic device architectures