Gary K. Giust

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Silicon germanium CMOS channel
- Patent number 6,977,400
- Issue date Dec 20, 2005
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laser-breakable fuse link with alignment and break point promotion...
- Patent number 6,770,947
- Issue date Aug 3, 2004
- LSI Logic Corporation
- Gary K. Giust
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laser-breakable fuse link with alignment and break point promotion...
- Patent number 6,566,730
- Issue date May 20, 2003
- LSI Logic Corporation
- Gary K. Giust
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon germanium CMOS channel
- Patent number 6,544,854
- Issue date Apr 8, 2003
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System to improve ser immunity and punchthrough
- Patent number 6,455,363
- Issue date Sep 24, 2002
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single channel four transistor SRAM
- Patent number 6,442,061
- Issue date Aug 27, 2002
- LSI Logic Corporation
- Weiran Kong
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-aligned fuse structure and method with dual-thickness dielectric
- Patent number 6,413,848
- Issue date Jul 2, 2002
- LSI Logic Corporation
- Gary K. Giust
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned fuse structure and method with heat sink
- Patent number 6,259,146
- Issue date Jul 10, 2001
- LSI Logic Corporation
- Gary K. Giust
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide encapsulation of polysilicon gate and interconnect
- Patent number 6,218,276
- Issue date Apr 17, 2001
- LSI Logic Corporation
- Yauh-Ching Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming thin polygates for sub quarter micron CMOS process
- Patent number 6,162,714
- Issue date Dec 19, 2000
- LSI Logic Corporation
- Ruggero Castagnetti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Depletion free polysilicon gate electrodes
- Patent number 6,090,651
- Issue date Jul 18, 2000
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned fuse structure and method with anti-reflective coating
- Patent number 6,061,264
- Issue date May 9, 2000
- LSI Logic Corporation
- Gary K. Giust
- G11 - INFORMATION STORAGE
Information Patent Grant
Metal-encapsulated polysilicon gate and interconnect
- Patent number 6,037,233
- Issue date Mar 14, 2000
- LSI Logic Corporation
- Yauh-Ching Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming self-aligned metal silicide contacts for MOS st...
- Patent number 5,953,614
- Issue date Sep 14, 1999
- LSI Logic Corporation
- Yauh-Ching Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Laser-breakable fuse link with alignment and break point promotion...
- Publication number 20030155629
- Publication date Aug 21, 2003
- Gary K. Giust
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicon germanium CMOS channel
- Publication number 20030146494
- Publication date Aug 7, 2003
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System to improve SER immunity and punchthrough
- Publication number 20020173087
- Publication date Nov 21, 2002
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS

Gary K. Giust

Person

Patents Grantslast 30 patents

Silicon germanium CMOS channel

Laser-breakable fuse link with alignment and break point promotion...

Laser-breakable fuse link with alignment and break point promotion...

Silicon germanium CMOS channel

System to improve ser immunity and punchthrough

Single channel four transistor SRAM

Self-aligned fuse structure and method with dual-thickness dielectric

Self-aligned fuse structure and method with heat sink

Silicide encapsulation of polysilicon gate and interconnect

Method of forming thin polygates for sub quarter micron CMOS process

Depletion free polysilicon gate electrodes

Self-aligned fuse structure and method with anti-reflective coating

Metal-encapsulated polysilicon gate and interconnect

Process for forming self-aligned metal silicide contacts for MOS st...

Patents Applicationslast 30 patents

Laser-breakable fuse link with alignment and break point promotion...

Silicon germanium CMOS channel

System to improve SER immunity and punchthrough