Gary R. Lawman

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus using device defects as an identifier
- Patent number 7,328,384
- Issue date Feb 5, 2008
- Xilinx, Inc.
- Chidamber R. Kulkarni
- G01 - MEASURING TESTING
Information Patent Grant
Tunable clock distribution system for reducing power dissipation
- Patent number 6,882,182
- Issue date Apr 19, 2005
- Xilinx, Inc.
- Robert O. Conn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA customizable to accept selected macros
- Patent number 6,381,732
- Issue date Apr 30, 2002
- Xilinx, Inc.
- James L. Burnham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods to securely configure an FPGA to accept selected macros
- Patent number 6,357,037
- Issue date Mar 12, 2002
- Xilinx, Inc.
- James L. Burnham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for configuring circuits over a data communications link
- Patent number 6,324,672
- Issue date Nov 27, 2001
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA customizable to accept selected macros
- Patent number 6,324,676
- Issue date Nov 27, 2001
- Xilinx, Inc.
- James L. Burnham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods to securely configure an FPGA using macro markers
- Patent number 6,301,695
- Issue date Oct 9, 2001
- Xilinx, Inc.
- James L. Burnham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA system with user-programmable configuration ports and method f...
- Patent number 6,172,520
- Issue date Jan 9, 2001
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory map computer control system for programmable ICS
- Patent number 6,118,938
- Issue date Sep 12, 2000
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip logic analysis and method for using the same
- Patent number 6,107,821
- Issue date Aug 22, 2000
- Xilinx, Inc.
- Steven H. Kelem
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuring an FPGA using embedded memory
- Patent number 6,049,222
- Issue date Apr 11, 2000
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PROM with built-in JTAG capability for configuring FPGAs
- Patent number 6,044,025
- Issue date Mar 28, 2000
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoder structure and method for FPGA configuration
- Patent number 6,028,445
- Issue date Feb 22, 2000
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for configuring circuits over a data communications link
- Patent number 6,023,565
- Issue date Feb 8, 2000
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Schematic design entry with annotated timing
- Patent number 5,949,690
- Issue date Sep 7, 1999
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating a secure macro element of a design for a prog...
- Patent number 5,946,478
- Issue date Aug 31, 1999
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for providing temporary registers in a local bus device by r...
- Patent number 5,928,338
- Issue date Jul 27, 1999
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
HDL design entry with annotated timing
- Patent number 5,870,309
- Issue date Feb 9, 1999
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent electronic circuit design and implementation
- Patent number 5,673,198
- Issue date Sep 30, 1997
- Xilinx, Inc.
- Gary R. Lawman
- G06 - COMPUTING CALCULATING COUNTING

Gary R. Lawman

Person

Patents Grantslast 30 patents

Method and apparatus using device defects as an identifier

Tunable clock distribution system for reducing power dissipation

FPGA customizable to accept selected macros

Methods to securely configure an FPGA to accept selected macros

Method for configuring circuits over a data communications link

FPGA customizable to accept selected macros

Methods to securely configure an FPGA using macro markers

FPGA system with user-programmable configuration ports and method f...

Memory map computer control system for programmable ICS

On-chip logic analysis and method for using the same

Configuring an FPGA using embedded memory

PROM with built-in JTAG capability for configuring FPGAs

Decoder structure and method for FPGA configuration

Method for configuring circuits over a data communications link

Schematic design entry with annotated timing

Method for generating a secure macro element of a design for a prog...

Method for providing temporary registers in a local bus device by r...

HDL design entry with annotated timing

Concurrent electronic circuit design and implementation