George V. Rouse

Person

Indialantic, FL, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bonded substrate for an integrated circuit containing a planar intr...
- Patent number 7,052,973
- Issue date May 30, 2006
- Intersil Americas Inc.
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer with metal silicidation
- Patent number 6,909,146
- Issue date Jun 21, 2005
- Intersil Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded substrate for an integrated circuit containing a planar intr...
- Patent number 6,825,532
- Issue date Nov 30, 2004
- Intersil Americas Inc.
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
BICMOS process with low temperature coefficient resistor (TCRL)
- Patent number 6,812,108
- Issue date Nov 2, 2004
- Intersil Corporation
- Donald Hemmenway
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
BiCMOS process with low temperature coefficient resistor (TCRL)
- Patent number 6,798,024
- Issue date Sep 28, 2004
- Intersil Americas Inc.
- Donald Hemmenway
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power trench transistor device source region formation using silico...
- Patent number 6,455,379
- Issue date Sep 24, 2002
- Fairchild Semiconductor Corporation
- Linda S. Brush
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a bonded substrate containing a planar intrinsic...
- Patent number 6,255,195
- Issue date Jul 3, 2001
- Intersil Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power trench transistor device source region formation using silico...
- Patent number 6,246,090
- Issue date Jun 12, 2001
- Intersil Corporation
- Linda S. Brush
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SC-2 based pre-thermal treatment wafer cleaning process
- Patent number 5,932,022
- Issue date Aug 3, 1999
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer processing with oxidative bonding
- Patent number 5,849,627
- Issue date Dec 15, 1998
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer
- Patent number 5,744,852
- Issue date Apr 28, 1998
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer and method of fabrication thereof
- Patent number 5,603,779
- Issue date Feb 18, 1997
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer processing with metal silicidation
- Patent number 5,569,620
- Issue date Oct 29, 1996
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer processing
- Patent number 5,517,047
- Issue date May 14, 1996
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer processing with metal silicidation
- Patent number 5,387,555
- Issue date Feb 7, 1995
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer processing
- Patent number 5,362,667
- Issue date Nov 8, 1994
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer bonding using trapped oxidizing vapor
- Patent number 5,334,273
- Issue date Aug 2, 1994
- Harris Corporation
- John P. Short
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer bonding process employing liquid oxidant
- Patent number 5,266,135
- Issue date Nov 30, 1993
- Harris Corporation
- John P. Short
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating SOI wafer with SiGe as an etchback film in a...
- Patent number 5,240,876
- Issue date Aug 31, 1993
- Harris Corporation
- Stephen J. Gaul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI wafer with sige
- Patent number 5,218,213
- Issue date Jun 8, 1993
- Harris Corporation
- Stephen J. Gaul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-thin circuit fabrication by controlled wafer debonding
- Patent number 5,091,331
- Issue date Feb 25, 1992
- Harris Corporation
- Jose A. Delgado
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing ultra-thin dielectrically isolated wafers
- Patent number 5,081,061
- Issue date Jan 14, 1992
- Harris Corporation
- George V. Rouse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing ultra-thin wafer using a handle wafer
- Patent number 5,034,343
- Issue date Jul 23, 1991
- Harris Corporation
- George V. Rouse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating back diffused bonded oxide substrates
- Patent number 4,968,628
- Issue date Nov 6, 1990
- Harris Corporation
- Jose A. Delgado
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric isolation process using double wafer bonding
- Patent number 4,851,078
- Issue date Jul 25, 1989
- Harris Corporation
- John P. Short
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Bonded substrate for an integrated circuit containing a planar intr...
- Publication number 20040180512
- Publication date Sep 16, 2004
- INTERSIL AMERICAS INC.
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BiCMOS process with low temperature coefficient resistor (TCRL)
- Publication number 20030157778
- Publication date Aug 21, 2003
- INTERSIL CORPORATION
- Donald Hemmenway
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SC-2 BASED PRE-THERMAL TREATMENT WAFER CLEANING PROCESS
- Publication number 20020189640
- Publication date Dec 19, 2002
- JACK H. LINN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Power trench transistor device source region formation using silico...
- Publication number 20010022379
- Publication date Sep 20, 2001
- INTERSIL CORPORATION
- Linda S. Brush
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a bonded substrate containing a planar intrinsic...
- Publication number 20010016399
- Publication date Aug 23, 2001
- HARRIS CORPORATION
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS

George V. Rouse

Person

Patents Grantslast 30 patents

Bonded substrate for an integrated circuit containing a planar intr...

Bonded wafer with metal silicidation

Bonded substrate for an integrated circuit containing a planar intr...

BICMOS process with low temperature coefficient resistor (TCRL)

BiCMOS process with low temperature coefficient resistor (TCRL)

Power trench transistor device source region formation using silico...

Method for forming a bonded substrate containing a planar intrinsic...

Power trench transistor device source region formation using silico...

SC-2 based pre-thermal treatment wafer cleaning process

Bonded wafer processing with oxidative bonding

Bonded wafer

Bonded wafer and method of fabrication thereof

Bonded wafer processing with metal silicidation

Bonded wafer processing

Bonded wafer processing with metal silicidation

Bonded wafer processing

Wafer bonding using trapped oxidizing vapor

Wafer bonding process employing liquid oxidant

Method of fabricating SOI wafer with SiGe as an etchback film in a...

SOI wafer with sige

Ultra-thin circuit fabrication by controlled wafer debonding

Manufacturing ultra-thin dielectrically isolated wafers

Manufacturing ultra-thin wafer using a handle wafer

Method of fabricating back diffused bonded oxide substrates

Dielectric isolation process using double wafer bonding

Patents Applicationslast 30 patents

Bonded substrate for an integrated circuit containing a planar intr...

BiCMOS process with low temperature coefficient resistor (TCRL)

SC-2 BASED PRE-THERMAL TREATMENT WAFER CLEANING PROCESS

Power trench transistor device source region formation using silico...

Method for forming a bonded substrate containing a planar intrinsic...