Grant Villavicencio

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Pressing of wire bond wire tips to provide bent-over tips
- Patent number 10,806,036
- Issue date Oct 13, 2020
- Invensas Corporation
- Reynaldo Co
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pressing of wire bond wire tips to provide bent-over tips
- Patent number 9,888,579
- Issue date Feb 6, 2018
- Invensas Corporation
- Reynaldo Co
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Information Patent Grant
Stiffened wires for offset BVA
- Patent number 9,659,848
- Issue date May 23, 2017
- Invensas Corporation
- Grant Villavicencio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical connector between die pad and z-interconnect for stacked...
- Patent number 9,508,689
- Issue date Nov 29, 2016
- Invensas Corporation
- Reynaldo Co
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical connector between die pad and z-interconnect for stacked...
- Patent number 9,153,517
- Issue date Oct 6, 2015
- Invensas Corporation
- Reynaldo Co
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die array structure
- Patent number 8,884,403
- Issue date Nov 11, 2014
- Iinvensas Corporation
- Reynaldo Co
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die having fine pitch electrical interconnects
- Patent number 8,829,677
- Issue date Sep 9, 2014
- Invensas Corporation
- Keith Lake Barrie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical interconnect for die stacked in zig-zag configuration
- Patent number 8,680,687
- Issue date Mar 25, 2014
- Invensas Corporation
- Reynaldo Co
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level surface passivation of stackable integrated circuit chips
- Patent number 8,324,081
- Issue date Dec 4, 2012
- Simon J. S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level surface passivation of stackable integrated circuit chips
- Patent number 7,923,349
- Issue date Apr 12, 2011
- Vertical Circuits, Inc.
- Simon J. S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die separation method
- Patent number 7,863,159
- Issue date Jan 4, 2011
- Vertical Circuits, Inc.
- Reynaldo Co
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SUBSTRATE MOUNT
- Publication number 20210134566
- Publication date May 6, 2021
- Reynaldo CORPUZ CO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pressing of Wire Bond Wire Tips to Provide Bent-Over Tips
- Publication number 20180146557
- Publication date May 24, 2018
- Invensas Corporation
- Reynaldo CO
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Information Patent Application
STIFFENED WIRES FOR OFFSET BVA
- Publication number 20170141020
- Publication date May 18, 2017
- Invensas Corporation
- Grant Villavicencio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRESSING OF WIRE BOND WIRE TIPS TO PROVIDE BENT-OVER TIPS
- Publication number 20160262268
- Publication date Sep 8, 2016
- Invensas Corporation
- Reynaldo CO
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Information Patent Application
ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED...
- Publication number 20160027761
- Publication date Jan 28, 2016
- Invensas Corporation
- Reynaldo Co
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Die Having Fine Pitch Electrical Interconnects
- Publication number 20150056753
- Publication date Feb 26, 2015
- Invensas Corporation
- Keith Lake Barrie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor die having fine pitch electrical interconnects
- Publication number 20120248607
- Publication date Oct 4, 2012
- Vertical Circuits, Inc.
- Keith Lake Barrie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrical Connector Between Die Pad and Z-Interconnect for Stacked...
- Publication number 20120119385
- Publication date May 17, 2012
- Vertical Circuits, Inc.
- Reynaldo Co
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS
- Publication number 20110147943
- Publication date Jun 23, 2011
- Vertical Circuits, Inc.
- Simon J.S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Die Separation Method
- Publication number 20110101505
- Publication date May 5, 2011
- Vertical Circuits, Inc.
- Reynaldo Co
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrical interconnect for die stacked in zig-zag configuration
- Publication number 20100327461
- Publication date Dec 30, 2010
- Vertical Circuits, Inc.
- Reynaldo Co
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Die Separation Method
- Publication number 20090315174
- Publication date Dec 24, 2009
- Vertical Circuits, Inc.
- Reynaldo Co
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS
- Publication number 20080315434
- Publication date Dec 25, 2008
- Vertical Circuits, Inc.
- Simon J.S. McElrea
- H01 - BASIC ELECTRIC ELEMENTS

Grant Villavicencio

Person

Patents Grantslast 30 patents

Pressing of wire bond wire tips to provide bent-over tips

Pressing of wire bond wire tips to provide bent-over tips

Stiffened wires for offset BVA

Electrical connector between die pad and z-interconnect for stacked...

Electrical connector between die pad and z-interconnect for stacked...

Semiconductor die array structure

Semiconductor die having fine pitch electrical interconnects

Electrical interconnect for die stacked in zig-zag configuration

Wafer level surface passivation of stackable integrated circuit chips

Wafer level surface passivation of stackable integrated circuit chips

Semiconductor die separation method

Patents Applicationslast 30 patents

SUBSTRATE MOUNT

Pressing of Wire Bond Wire Tips to Provide Bent-Over Tips

STIFFENED WIRES FOR OFFSET BVA

PRESSING OF WIRE BOND WIRE TIPS TO PROVIDE BENT-OVER TIPS

ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED...

Semiconductor Die Having Fine Pitch Electrical Interconnects

Semiconductor die having fine pitch electrical interconnects

Electrical Connector Between Die Pad and Z-Interconnect for Stacked...

WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS

Semiconductor Die Separation Method

Electrical interconnect for die stacked in zig-zag configuration

Semiconductor Die Separation Method

WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS