Guarionex Morales

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for controlling grain growth roughening in con...
- Patent number 6,500,757
- Issue date Dec 31, 2002
- Advanced Micro Devices, Inc.
- Guarionex Morales
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface treatment of low-K SiOF to prevent metal interaction
- Patent number 6,444,593
- Issue date Sep 3, 2002
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of degassing low k dielectric for metal deposition
- Patent number 6,436,850
- Issue date Aug 20, 2002
- Guarionex Morales
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of reducing contact size by spacer filling
- Patent number 6,420,104
- Issue date Jul 16, 2002
- Advanced Micro Devices, Inc.
- Bharath Rangarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure used to measure metal bottom coverage in trenches an...
- Patent number 6,380,556
- Issue date Apr 30, 2002
- Advanced Micro Devices, Inc.
- David Bang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electron microscopy sample having silicon nitride passivation layer
- Patent number 6,335,533
- Issue date Jan 1, 2002
- Advanced Micro Devices, Inc.
- Guarionex Morales
- G01 - MEASURING TESTING
Information Patent Grant
Surface treatment of low-K SiOF to prevent metal interaction
- Patent number 6,335,273
- Issue date Jan 1, 2002
- Advanced Micro Devices, Inc.
- Richard J. Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with improved adhesion between interfaces of con...
- Patent number 6,281,584
- Issue date Aug 28, 2001
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Damascene metal interconnects using highly directional deposition o...
- Patent number 6,281,121
- Issue date Aug 28, 2001
- Advanced Micro Devices, Inc.
- Dirk Dewar Brown
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming rectangular shaped spacers
- Patent number 6,265,273
- Issue date Jul 24, 2001
- Advanced Micro Devices, Inc.
- Steven C. Avanzino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having double bottom anti-reflective coating layer
- Patent number 6,265,294
- Issue date Jul 24, 2001
- Advanced Micro Devices, Inc.
- Stephen Keetai Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tungsten plug formation
- Patent number 6,235,632
- Issue date May 22, 2001
- Advanced Micro Devices, Inc.
- Takeshi Nogami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and arrangements for reducing stress and preventing crackin...
- Patent number 6,211,074
- Issue date Apr 3, 2001
- Advanced Micro Devices, Inc.
- Richard J. Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of silicide film formation onto a semiconductor substrate
- Patent number 6,177,345
- Issue date Jan 23, 2001
- Advanced Micro Devices, Inc.
- Guarionex Morales
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure used to measure metal bottom coverage in trenches an...
- Patent number 6,127,193
- Issue date Oct 3, 2000
- Advanced Micro Devices, Inc.
- David Bang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-low temperature Al fill for sub-0.25 .mu.m generation of ICs...
- Patent number 6,110,829
- Issue date Aug 29, 2000
- Advanced Micro Devices, Inc.
- Paul Raymond Besser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming high integrity tungsten silicide thin films
- Patent number 6,100,192
- Issue date Aug 8, 2000
- Advanced Micro Devices, Inc.
- Guarionex Morales
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper/low dielectric interconnect formation with reduced electromi...
- Patent number 6,096,648
- Issue date Aug 1, 2000
- AMD
- Sergey Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cobalt silicidation using tungsten nitride capping layer
- Patent number 6,083,817
- Issue date Jul 4, 2000
- Advanced Micro Devices, Inc.
- Takeshi Nogami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density plasma oxide gap filled patterned metal layers with im...
- Patent number 6,046,106
- Issue date Apr 4, 2000
- Advanced Micro Devices, Inc.
- Khanh Q. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for reducing copper oxide during integrated circuit fabrica...
- Patent number 6,033,584
- Issue date Mar 7, 2000
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vacuum baked HSQ gap fill layer for high integrity borderless vias
- Patent number 6,030,891
- Issue date Feb 29, 2000
- Advanced Micro Devices, Inc.
- Khanh Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface treatment of low-k SiOF to prevent metal interaction
- Patent number 5,994,778
- Issue date Nov 30, 1999
- Advanced Micro Devices, Inc.
- Richard J. Huang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Methods for characterizing and reducing adverse effects of texture...
- Publication number 20010053600
- Publication date Dec 20, 2001
- Guarionex Morales
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE TREATMENT OF LOW-K SIOF TO PREVENT METAL INTERACTION
- Publication number 20010044203
- Publication date Nov 22, 2001
- RICHARD J. HUANG
- H01 - BASIC ELECTRIC ELEMENTS

Guarionex Morales

Person

Patents Grantslast 30 patents

Method and apparatus for controlling grain growth roughening in con...

Surface treatment of low-K SiOF to prevent metal interaction

Method of degassing low k dielectric for metal deposition

Method of reducing contact size by spacer filling

Test structure used to measure metal bottom coverage in trenches an...

Electron microscopy sample having silicon nitride passivation layer

Surface treatment of low-K SiOF to prevent metal interaction

Integrated circuit with improved adhesion between interfaces of con...

Damascene metal interconnects using highly directional deposition o...

Method of forming rectangular shaped spacers

Integrated circuit having double bottom anti-reflective coating layer

Tungsten plug formation

Methods and arrangements for reducing stress and preventing crackin...

Method of silicide film formation onto a semiconductor substrate

Test structure used to measure metal bottom coverage in trenches an...

Ultra-low temperature Al fill for sub-0.25 .mu.m generation of ICs...

Method of forming high integrity tungsten silicide thin films

Copper/low dielectric interconnect formation with reduced electromi...

Cobalt silicidation using tungsten nitride capping layer

High density plasma oxide gap filled patterned metal layers with im...

Process for reducing copper oxide during integrated circuit fabrica...

Vacuum baked HSQ gap fill layer for high integrity borderless vias

Surface treatment of low-k SiOF to prevent metal interaction

Patents Applicationslast 30 patents

Methods for characterizing and reducing adverse effects of texture...

SURFACE TREATMENT OF LOW-K SIOF TO PREVENT METAL INTERACTION